SONY KE-P37XS1, KE-P42XS1, KDE-P37XS1, KDE-P42XS1, KE-MX42A1 Service Manual

MODIFICATION HISTORY

MODEL NAME : KE-P37XS1/P42XS1

			KE-MX42A1/MX42S1/MX42M1
			KDE-P37XS1/P42XS1
			SERVICE MANUAL
			PARTS No. : 9-878-248-02
			* Blue characters are linking.
No.	DATA		CONTENTS
1	2004. 6	Addition of Hong Kong, ME, China, OCE and UK Models.
		Correction of The Parts Information. (P.83)

KE-P37XS1/P42XS1

KDE-P37XS1/P42XS1 KE-MX42A1/MX42S1/MX42M1

PANEL MODULE SERVICE MANUAL

PDP Module Name

FPF37C128128UB

FPF42C128128UC

KE-P37XS1	AEP Model
KE-P42XS1	AEP Model
KDE-P37XS1	UK Model
KDE-P42XS1	UK Model
KE-MX42A1	Hong Kong Model
KE-MX42A1	ME Model
KE-MX42M1	China Model
KE-MX42S1	OCE Model

FLAT PANEL COLOR TV

	CONTENTS
1 OUTLINE
1.1	Panel Dimension ................................................................................................................	1
1.2	Feature...............................................................................................................................	1
1.3	Specification.......................................................................................................................	2
1.3.1 Functional specification ...............................................................................................		2
1.3.2 Display quality specification .........................................................................................		3
1.3.3 I/O Interface Specification............................................................................................		4
1.3.4 Connector Specifications .............................................................................................		7
2 SAFETY HANDLING of THE PLASMA DISPLAY
2.1	Notes to Follow During Servicing .....................................................................................	10
3 NAME and FUNCTION
3.1	Configuration ....................................................................................................................	11
3.2	Block Diagrams ................................................................................................................	12
3.2.1 Signal Diagrams ........................................................................................................		12
3.2.2 Power Diagrams ........................................................................................................		13
3.3	Function............................................................................................................................	14
3.3.1 Logic board Function .................................................................................................		14
3.3.2 Function of X-SUS Board ..........................................................................................		23
3.3.3 Function of Y-SUS Board ..........................................................................................		23
3.4	Protection function............................................................................................................	24
4 PROBLEM ANALYSIS
4.1	Outline of Repair Flow......................................................................................................	25
4.2	Outline of PDP Module Repair Flow.................................................................................	26
4.3	Checking the Product Requested for Repair....................................................................	29
4.4	Operation Test Procedure ................................................................................................	31
4.5	Fault Symptom .................................................................................................................	32
4.6	Problem Analysis Procedure ............................................................................................	35
4.6.1 "The entire screen does not light.(Main power is turned off)” Problem analysis
procedure............................................................................................................................		35
4.6.2 "Vertical line/Vertical bar" Problem analysis procedure..............................................		42
4.6.3 "Horizontal bar" Problem analysis procedure ............................................................		46
4.7	Problem Analysis Using a Personal Computer.................................................................	47
4.7.1 Connecting a computer..............................................................................................		47
4.7.2 Preparing a computer ................................................................................................		47
4.7.3 Problem Analysis Procedure......................................................................................		48
5 Disassembling and Reassembling
5.1	Exploded View..................................................................................................................	52

5.2	X-SUS Circuit Board Removal/Installation Procedure......................................................	53
5.3	Y-SUS Circuit Board Removal/Installation Procedure......................................................	55
5.4	ABUS-L Circuit Board Removal/Installation Procedure....................................................	57
5.5	ABUS-R Circuit Board Removal/Installation Procedure ...................................................	59
5.6	LOGIC Board Removal/Installation Procedure.................................................................	61
5.7	Complete Panel Chassis Removal/Installation Procedure ...............................................	63
6 Operation Check and Adjustment Method
6.1	List of Check and Adjustment Items.................................................................................	66
6.2	Check and Adjustment Method ........................................................................................	67
6.2.1 Check and adjustment procedure..............................................................................		67
6.2.2 Parameter adjustment ...............................................................................................		68
6.2.3 Operation performance check items..........................................................................		70
6.2.4 Heat Run Test ............................................................................................................		72
6.2.5 Logic board parameter forwarding.............................................................................		74
6.2.6 Accumulation time reset ............................................................................................		76
6.2.7 Setup before shipment...............................................................................................		77
7 37A1 Mechanical drawing
FPF37C128128UB-63, 73 ................................................................................................		78
8 THE PARTS INFORMATION ..................................................................................................		83

Scope; 42A1 series

(Model name; FPF42C128128UC)

Caution Before doing the service operation please be sure to read this service analysis manual. This module has a lot of devices to secure the safety against the fire, electric shock, injury and harmful radiation.

To maintain the safety control, please follow the instructions and remarks described in this service analysis manual.

1 OUTLINE

The module is a plasma display module which can be designed in there is no fan in addition to a general feature of the plasma display such as a flat type, lightness, and high-viewing-angle and terrestrial magnetism.

1.1 PANEL DIMENSION

994

921.6

585

522.24

Pixel pitch(horizontal)		Subpixel pitch(horizontal)
0.90mm				0.30mm

Pixelpitch(Vertical)		0.51 mm

R G B R G B R G B

R G B R G B R G B

R G B R G B R G B

R G B R G B R G B

R G B R G B R G B

R G B R G B R G B

1.2FEATURE

1.For high definition television by ALIS method

2.For FAN Less design(Low consumption electric power

3.Flat type Lightness

4.Customizing of module equipped with communication function

–1 –

1.3 SPECIFICATION

1.3.1 Functional specification

		Item	NO	Specification
				UC-5X
	Externals	Module size	1	994 × 585 × 66mm
		Weight	2	16kg
	Display panel	Display size	3	921.60 × 522.24mm
				(42inch: 16:9)
		Resolution	4	1024 × 1024 pixel
		Pixel pitch	5	0.90(H) × 0.51(V)mm
		Sub pixel pitch	6	0.30(H) × 0.51(V)mm
	Color	Grayscale(standard)	7	RGB each color 256 Grayscale
	BrightNess	White(display load Ratio 100%)	8	140cd/ m2
		White(display load Ratio 1%,standard)	9	(1000) cd/ m2
	Chromaticity	(x,y) white 10%	10	(0.300,0.300)
	Coordinates
	Contrast	Contrast in Darkroom(60Hz)	11	(1000:1)
	Data signal	Video signal (RGB each color)	12	LVDS(10bit)
		Dot clock(max)	13	52MHz
	Sync Signal	Horizontal Sync Signal(max)	14	50KHz(LVDS)
		Vertical Sync Signal	15	50Hz ± 1.9 / 60 ± 1.7Hz (LVDS)
	Powersupply	Input voltage/current	16	+3.3/+5/+75-90/+50-65VDC, 0.05/6/4/2A
		Standby electric power(max)	17	1W
	Noise	Shade noise at 18dB(A) or less	18	25dB(A) or less
	Guarantee	Temperature(operation)	19	0 ~ 45 °C
	environment
		Temperature(storage)	20	0 ~ 45 °C
		Humidity(operation)	21	20 ~ 85 %RH (no condensation)
		Humidity(storage)	22	20 ~ 80 %RH (no condensation)

*It is made to give priority when there is a delivery specification according to the customer.

– 2 –

1.3.2 Display quality specification

		Item	NO	Specification
				UC-51 (Standard)
	Non-lighting cell	Total number (subpixel)	1	15 or less
	defect
		Density (subpixel/cm2)	2	2 or less
				However,1 continuousness or less
		Size (H x V) (subpixel)	3	1x2 or less, Or 2x1 or less
	Non-extinguishing	Total number (subpixel)	4	6 or less each color 2 or less
	cell defect
		Density (subpixel/ cm2)	5	Each color 2 cells max
				However,1 continuousness or less
	Flickering cell defect	Flickering lighting cell defect	6	5 or less
		(sub pixel/cm2)
		Flickering non-extinguishing cell defect	7	Number on inside of
				Non-extinguishing cell defect
	High intensity cell	Twice or more bright point	8	0
	defect
	Brightness variation	White block of 10% load [9 point] (%)	9	20 or less
		In area adjacent 20mm [White] (%)	10	10 or less
	Color variation	White block of 10% load [9 point]	11	X: Average ± 0.015
				y: Average ± 0.015

*It is made to give priority when there is a delivery specification according to the customer.

– 3 –

1.3.3I/O Interface Specification

(1)I/O Signal

				Number
No.	Item	Signal Name		of	I/O	Form		Content of definition
				signals
			RA-	1				Differential serial data signal.
			RA+	1				Input video and timing signals after
			RB-	1				differential serial conversion using a
			RB+	1		LVDS		dedicated transceiver.
		Video Signal	RC-	1	Input
								The serial data signal is transmitted
		Timing Signal	RC+	1		Differential
								seven times faster than the base
			RD-	1
			RD+	1				signal
	data		RE-	1
			RE+	1				Input the clock signal after
1	Display
								Differential clock signal.
		Clock	RXCLKIN-	1	Input	LVDS		differential conversion using a
			RXCLKIN+	1		Differential		dedicated transceiver.
								The clock signal is transmitted at
								the same speed as the base signal.
		Power down	PDWN	1	Input	LVTTL		Low :LVDS receiver outputs are all
								“L”.
		Signal
								High: Input signals are active.
			SDA	1	I/O	LVTTL		I2C bus serial data communication
								signal.
		Communication
						2	C)	Communication with the control
	Control/		SCL	1	I/O	(I
								Low power consumption mode of
								MPU of this product is enabled.
	Communication		CPUGO	1	Input	LVTTL		the control MPU of this product is
2								released.
			PDPGO	1	Input	LVTTL		“High”: This product is started.
								(CPUGO=“High” Effective)
		Control
	MPU							It changes into "Low" → "High"
			IRQ	1	Output	LVTTL		when this product enters the
								undermentioned state.
								1. Vcc/Va/Vs output decrease
								2. Circuit abnormality detection

– 4 –

(2) LVDS Signal Definition and Function

A video signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS transmitter and further converted into four sets of differential signals before input to this product.

These signals are transmitted seven times faster than dot clock signals.

The dot clock signal is converted into one set of differential signals by the transmitter before input to this product.

The LVDS signal definition and function are summarized below:

Signal name

Symbol

Number of

Signal definition and function

signals

Video signal

RA-

1

Display data signal

Timing signal

RA+

1

R2, R3, R4, R5, R6, R7, G2

Transmission line

RB-

1

Display data signal

RB+

1

G3, G4, G5, G6, G7, B2 B4

RC-

1

Display data signal Sync Signal Control signal

RC+

1

B4, B5, B6, B7,

Hsync

,

Vsync

,

BLANK

RD-

1

Display data signal, Control signal

RD+

1

R8, R9, G8, G9, B8, B9, PARITY

RE-

1

Display data signal, Control signal

RE+

1

R0, R1, G0, G1, B0, B1, N.S

Clock transmission

RXCLKIN-

1

Clock signal

line

RXCLKIN+

1

DCLK

– 5 –

(3) Video Signal Definition and Function

The table below summarizes the definitions and functions of input video signals before LVDS conversion.

	Item	Signal name	Number	Input/	Signal definition and function
			of signals	output

Original Display signal (before LVDS transmittance)

Video signal

DATA-R

10

Display data signal

R9/G9/B9 is the highest intensity bit.

DATA-G

10

Input

(digital RGB)

R0/G0/B0 is the lowest intensity bit.

DATA-B

10

Data Clock

Display data timing signal: Data are read when

Input

is lowerd.

is continuously

DCLK

DCLK

DCLK

input.

Horizontal

Regulates one horizontal line of data: Begins

1

Input

Hsync

control of the next screen when Hsync is

sync signal

lowered.

Screen starts up control timing signal: Begins

control of the next screen when

is

Vertical sync

1

Input

Vsync

Vsync

signal

lowered.

Input the same frequency in both

odd-numbered and even-numbered fields.

This signal specifies the display field.

H: Odd-numbered field

Parity signal

PARITY

1

Input

L: Even-numbered field

Parity signal should be alternated in every

cycle.

Vsync

Display period timing signal.

H indicates the display period and L indicates

the non display period.

Note:

Set this timing properly like followings, as is

used internally for signal processing.

Set the blanking period so that the number of

effective display data items in one horizontal

Blanking

1

Input

period is 1024.

BLANK

signal

Set the number of blanking signals in one

vertical period to 512, which is one half the

number of effective scan lines.

If the

changes when the

BLANK

Vsync

frequency is switched, the screen display may

be disturbed or brightness may change.

The screen display is restored to the normal

state later when the

length is

BLANK

constant again.

*This product does not correspond to the progressive display mode by the parity signal fixation. When the parity signal is fixed, this product is reversed arbitrarily internally and used.

– 6 –

1.3.4Connector Specifications

The connector specification is shown below. Please do not connect anything with the terminal NC.

(1) Signal connector [CN1]

Pin No.	Signal name		Pin No.	Signal name
1	RA-		2	GND(LVDS)
3	RA+		4	SCL
5	RB-		6	GND
7	RB+		8	SDA
9	RC-		10	GND(LVDS)
11	RC+		12	CPUGO
13	RXCLKIN-		14	PDPGO
15	RXCLKIN+		16	IRQ
17	RD-		18	PDWN
19	RD+		20	GND(LVDS)
21	RE-		22	GND
23	RE+		24	GND
25	GND		26	GND
27	GND		28	GND
29	GND		30	GND
DF13-30DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)
[Conforming connector]		Housing: DF13-30DS-1.25C
		Contact: DF13-2630SCF

(2)Power Source Connectors (PSU only is used on repair working)

(a)Power input connector [CN61]

Pin No.	Symbol
1	AC(L)
2	N.C
3	AC(N)
4	N.C
5	N.C
6	F.G

B06P-VH (Maker: JST)

[Conforming connector] Housing: VHR-06N(or M) Contact: SVH-21T-P1.1

– 7 –

(b) Power supply output connector for system [CN62]

Pin No.	Symbol
1	VAUX
2	N.C
3	GND

B03P-VH (Maker: JST)

[Conforming connector] Housing: VHR-06N(or M) Contact: SVH-21T-P1.1

(c) Power supply output connector for system [CN63]

Pin No.	Symbol
1	Vpr1
2	N.C.
3	Vpr2
4	N.C.
5	GND

B5B-XH-A (Maker: JST)

[Conforming connector] Housing: XHP-5 Contact: SXH-001T-P0.6

(iii)Power Source Connectors

(a)Power supply output connector for system [CN6]

Pin No.	Symbol
1	Vpr2
2	N.C.
3	GND
4	GND
5	N.C.
6	Vcc

B6B-PH-SM3(JST)

[Conforming connector] Housing: PHR-6

Contact: SPH-002T-P0.5L

– 8 –

(b) [CN23]

Pin No.	Symbol
1	Va
2	N.C.
3	Vcc
4	GND
5	GND
6	GND
7	N.C.
8	Vs
9	Vs
10	Vs

B10P-VH(JST)

[Conforming connector] Housing: VHR-10N Contact: SVH-21T-P1.1

(c) Power supply output connector for system [CN7]

Pin No.	Symbol	Pin No.	Symbol
1	N.C.	11	GND
2	N.C.	12	Vra
3	N.C.	13	GND
4	N.C.	14	Vrs
5	GND	15	GND
6	VSAGO	16	Iak
7	GND	17	GND
8	VCEGO	18	Vak
9	GND	19	GND
10	PFCGO	20	Vsk

00 6200 520 330 000 [ZIF Right Angle Connector] (Kyocera elco)

– 9 –

2 SAFETY HANDLING of THE PLASMA DISPLAY

2.1 NOTES TO FOLLOW DURING SERVICING

The work procedures shown with the Note indication are important for ensuring the safety of the product and the servicing work. Be sure to follow these instructions.

Before starting the work, secure a sufficient working space.

At all times other than when adjusting and checking the product, be sure to turn OFF the main POWER switch and disconnect the power cable from the power source of the display (jig or the display itself) during servicing.

To prevent electric shock and breakage of PC board, start the servicing work at least 30 seconds after the main power has been turned off. Especially when installing and removing the power supply PC board and the SUS PC board in which high voltages are applied, start servicing at least 2 minutes after the main power has been turned off.

While the main power is on, do not touch any parts or circuits other than the ones specified. The high voltage power supply block within the PDP module has a floating ground. If any connection other than the one specified is made between the measuring equipment and the high voltage power supply block, it can result in electric shock or activation of the leakage-detection circuit breaker.

When installing the PDP module in, and removing it from the packing carton, be sure to have at least two persons perform the work while being careful to ensure that the flexible printed-circuit cable of the PDP module does not get caught by the packing carton.

When the surface of the panel comes into contact with the cushioning materials, be sure to confirm that there is no foreign matter on top of the cushioning materials before the surface of the panel comes into contact with the cushioning materials. Failure to observe this precaution may result in the surface of the panel being scratched by foreign matter.

When handling the circuit PC board, be sure to remove static electricity from your body before handling the circuit PC board.

Be sure to handle the circuit PC board by holding the such large parts as the heat sink or transformer. Failure to observe this precaution may result in the occurrence of an abnormality in the soldered areas.

Do not stack the circuit PC boards.

Failure to observe this precaution may result in problems resulting from scratches on the parts, the deformation of parts, and short-circuits due to residual electric charge.

Routing of the wires and fixing them in position must be done in accordance with the original routing and fixing configuration when servicing is completed.

All the wires are routed far away from the areas that become hot (such as the heat sink). These wires are fixed in position with the wire clamps so that the wires do not move, thereby ensuring that they are not damaged and their materials do not deteriorate over long periods of time. Therefore, route the cables and fix the cables to the original position and states using the wire clamps.

Perform a safety check when servicing is completed.

Verify that the peripherals of the serviced points have not undergone any deterioration during servicing. Also verify that the screws, parts and cables removed for servicing purposes have all been returned to their proper locations in accordance with the original setup.

– 10 –

3 NAME and FUNCTION

3.1CONFIGURATION

(1)FPF42C128128UC-53 (LOGIC set out left side)

– 11 –

3.2 BLOCK DIAGRAMS

3.2.1 Signal Diagrams

X-SUS B.

Y-SUS B.

S

X

X-SUS

D

B

Y-SUS

EVEN SW

EVEN SW

M

B

X-SCAN

Y-SCAN

EVEN SW

EVEN SW

S

X

X-SUS

Y-SUS

D

B

ODD SW

ODD SW

M

B

X-SCAN

Y-SCAN

ODD SW

ODD SW

ADM1

ADM2

ADM3

ADM4

ADM5

ADM6

ADM7

ADM8

ABUSL B

ABUSR B.

POS

POS /NEG

RESET

RESET SW

CN51

CN41

CN31	CN21

LOGIC B.

TIMMING ROM

CN3

CN2

SCAN CONTROLLER

24MHz

OSC

SIGNAL

DATA PROCESSOR

DATA CONVERTER

CN1

INPUT

CN5

LVDS

γ comp.

RGB

DITHER

SUB FIELD

MEMORY

GAIN

/ERR

PRC.

CONTROLLER

		MPU			CN4
	V-SYNC cont.		OSC	OSC	FRAME
					MEMORY
			40MH	80MH
I2C	SCI.
			EEPROM
Analog Sw	Failure DET.	APC cont.		Vrs
OSC	FLASH MEMORY	I/O	D/A	Vra
				Vrw
10MHz				Vrx

CN7

CN69 PFCgo

Vsago

Vcego

PSU B.

*1

– 12 –

3.2.2 Power Diagrams

Y-SUS B.

S

X

X-SUS B.

X-SUS

Y-SUS

D

B

EVEN SW

M

B

EVEN SW

X-SCAN

Y-SCAN

EVEN SW

EVEN SW

S

X

X-SUS

Y-SUS

D

B

ODD SW

ODD SW

M

B

X-SCAN

Y-SCAN

ODD SW

ODD SW

ADM1

ADM2

ADM3

ADM4

ADM5 ADM6

ADM7

ADM8

POS/NEG

CN52

Va 63V

ABUSL B

ABUSR B. Va 63V

CN42

POS/NEG

RESET SW

RESET SW

CN36

Vcc 5V

Vcc 5V

CN26

Vcc 5V

Vcc 5V

Vs 85V

CN32

CN22

Vs 85V

55VVx

Va 63V

Va 63V

Vw

190V

Vxwgo

Vu

55V

DC/DC

CONVERTER

Vra

Vs 85V

YFVE

Vy VE

D/A

Vrs

18V

18V 17V

CPUgo

Vrw

Vrx

XFVE

Vxx

VE

PDPgo

DC/DC

MPU

18V

20V

17V

CONVERTER

Vcc 5V

DC/DC

RST

Vpr2 3.3V

Vrst

CONVERTER

LOGIC B.

Vcc 5V

Vs

CN6

85V

CN23

AC100

10A

~240V

PFC

380V

63V

Va

CN61

Vsago

5V

Vcc

Vcego

CN68

Servce

85V

SW

Vs

PFCgo

5/3.3V

Vpr2

3.3V

Vpr1

5V

PFCgo

control

Vsago

CN64

Vsago

PSU B.

Vra

Vcego

*1:Power supply(jig)

– 13 –

3.3 FUNCTION

3.3.1Logic board Function

(1)Data Processor

-γ adjustment(1 / 2.2 / 2.4 / 2.6 / 2.8)

-NTSC/EBU format(Color matrix) Switch

-RGB gain Control(White balance adjustment, Amplitude limitation)

-Error Diffusion Technology(Grayscale adjustment)

-Dither(Grayscale adjustment)

-Burn-in Pattern generation

(2)Data Converter

-Quasi out-line adjustment (luminous pattern control)

(3)Scan Controller

-Address driver control signal generator(ADM)

-scan driver control signal generator(SDM)

-X/Y sustain control signal generator

(4)Waveform ROM

-Waveform Pattern for drive / Timing memory

(5)MPU

-Synchronous detection

-System control

-Driving voltage(Va, Vs, Vr, Vw) Minute adjustment

-Abnormal watch (breakdown detection)/abnormal processing

-Is(sustain) current control (sustain pulse control)

-Ia(address) current control (sub-field control)

-External communication control

-Flash memory (firmware)

(6)EEPROM

-Control parameter memory

-The accumulation energizing time (Every hour).

-Abnormal status memory (16 careers)

– 14 –

Sub	Data				Setting [hex]
		Symbol	Item	Function
Address	bit				RANGE		INITIAL
							value
00	7-0	MAPVER	address MAP	Indicates the version number of the	00 ~ FF		01
			VERsion	address map.
				Indicates that an error has occurred.
				It can be cleared with the ErrRST	0: Not updated
	7	ERRF	update of	setting.			0
			ERRor Flag	If this flag is set, Error code is	1: Updated
				written. Cannot enter the PDP-ON
				mode.
			update of	Indicates that the drive hours are	0: Not updated
01	6	OHRF	Operation				0
				counted.	1: Updated
			HouRs Flag
			Power Shut	Indicates that shutdown of the AC	0: Not detected
	5	PSDF		power is detected and the PDP has			0
			Down Flag	executed the OFF-sequence. It can	1: Detected
				be cleared with the PSDRST setting.
	4-0	CNDC	CoNDition	Indicates status of the module.	Refer to 4.11.2.6		Irregular
			Code		condition codes.
				Indicates error code.
				The error codes of as many as 16
02	7-0	ERRC	ERRor Code	errors in the past can be retrieved	00~FF		00
				with the ERRS setting. . Same error
				code is not stored continuously.
			Operation	Indicates the higher 8 bits of the	00~FF		00
03	7-0	OHRH	HouRs
				module driving hours.
			Higher bits
			Operation	Indicates the lower 8 bits of the	00~FF		00
04	7-0	OHRL	HouRs Lower
				module driving hours.
			bits

– 15 –

– 16 –

1: 8bit input

Sub	Data					Setting [hex]
			Symbol	Item	Function
Address		bit				RANGE		INITIAL
								value
						0: The single color
						display is switched
				Selecting	It selects the built-in test pattern	every 2 seconds. A
	7		PATSEL		signals of this display. This setting is	total of 8 colors are		0
				patterns
					valid when the PATON setting is 1.	displayed.
						1:All white (Different
						from actual white.)
				Built-in		0: Displaying the
	6		PATON	pattern	Display of the built-in pattern signal	input signal		0
				display is set	in this product is turned ON/OFF.	1: Displaying the
				to ON.		built-in pattern
				Address	The black screen is displayed.	0: Blank
	5		ADEN		0 is set when the input video signal	1: Displaying the		1
				data enable
					has disturbance.	input signal
	4		-	-	Be sure to use the display with the	0~1		0
					setting fixed to 0.
20
	3		DSPPOL	DiSPlay	Input reflection polarity setting	0:Emits light by LOW		1
				POLarity		1:Emits light by High
					When PFCON = 0, If a high voltage
					power is switched on, PFCGO is set
					high before a high voltage power is
				forcing PFC	output.	0: Power OFF		0
	2		PFCON		When PDPON = 1, PFCGO is set
				ON		1: Power ON
					high irrespective of the state of a
					high voltage power.
					Use it for a power control when a
					high voltage power is off.
				High voltage	Switches ON/OFF the high voltage	0: Power OFF
	1		PDPON	power supply				0
					power supply of PDP.	1: Power ON
				ON
	0		DSPBIT	Input Data bit	Switches 8 bit input / 10 bit input	0: 10 bit input		1

Sub	Data				Setting [hex]
		Symbol	Item	Function
Address	bit				RANGE		INITIAL
							value
	7-5	-	-	Be sure to use the display with the	0~7		0
				setting fixed to 0.
			Color		0:Luminance has
				Selecting the color correction modes.	priority.		0
	4	CCFMD	correction
				Valid when the CCFON setting is 1	1:Gradation has
			mode
					priority
			Dynamic	Tracking correction of white balance	0: OFF
	3	DCBON	Color	between the high luminance and the			0
					1: ON
			Balance	low luminance.
				When a picture with high
				luminance/small area is displayed for
				about 3 minutes or longer, the
			Panel Protect	number of pulses is reduced to about	0: OFF		1
	2	PPAON		20% at a maximum. This item can be
			Apc function		1: ON
				used to reduce panel
21				temperature/extend useful life when
				the display is used to show a still
				image.
			Auto Peak	If a low display load picture (less	0: OFF
				than 2%) is inputted continuously 3
	1	APSON	Save				1
				minutes or more, the brightness is	1: ON
			function
				reduced about 50 %.
				Whether the register value is
				reflected to the operating status of
				this product, selected by this item.
				The following switch is executed.
			Data	0:The received register value is	0: Invalid		1
	0	DSETEN	Set	reflected from the next field.
					1: Valid
			Enable	1:The received register value is
				stored so that the DSET setting is
				reflected from the next field.
				(DSET setting: Setting bit 0 of
				address FF)
	7	CCFON	Color	Color collection process is turned	0: OFF		0
			correction	ON/OFF.	1: ON
			Color	Color collection process is switched.	0: NTSC
	6	CCFORM	correction	This item is valid when CCFON			0
					1: EBU
			format	setting is 1.
	5-3	-	-	Be sure to use the display with the	0~7		0
				setting fixed to 0.
22
				Reverse γ correction level is set.	0: OFF
				The setup 7 is the test mode. Do not	1: 1.0 th power
			Selecting the	select the setup 7.	2: 2.2 nd power
				When the setup 6 is selected, setting	3: 2.4 th power		2
	2-0	GAMSEL	reverse γ
				of the addressed in the range of	4: 2.6 th power
			correction
				31~51 become valid.	5: 2.8 th power
					6: USER
					7: TEST

– 17 –

Sub	Data				Setting [hex]
		Symbol	Item	Function
Address	bit				RANGE		INITIAL
							value
				Peak luminance is adjusted.
23	7-0	CONTrast	Peak	When the display picture load is	00~FF		FF
			luminance	heavy, the peak luminance is
				automatically limited.
24	7-0	R-RATIO	R ratio	White balance is adjusted.	00~FF		FF
				Use the display with at least one item
25	7-0	G-RATIO	G ratio		00~FF		FF
				being set to FF (hex).
26	7-0	B-RATIO	B ratio		00~FF		FF
				This item implements control to
			Clearing the	return the IRQ signal from "HIGH" to	0: Normal		0
	7	IRQRST	IRQ output	"Low" level when an error occurs.
					1: IRQ signal clear
			signal	When this item is set to 1, the IRQ
				signal is returned to "Low" level.
				This item implements control to
				return the ERRF flag to 0 when an	0: Normal
	6	ERRRST	Clearing the	error occurs.			0
			ERRF flag	When this item is set to 1, this	1: ERRFflag clear
				setting automatically returns to 0
				after returning the ERRF flag to 0.
	5	OHRRST	Clearing the	The control by which the OHRF flag	0: Normal
			OHRF flag	is returned to 0 is done. This setting			0
				automatically returns to the state of 0	1: OHRF
27				after returning 0 the ERRF flag when	flag clear
				this setting is set to one.
	4	PSDRST	Clearing the	This item exercise control to return
			PSDF flag	the PSDF flag to 0 when this
				machine performs the OFF	0: Normal
				sequence at AC power shutdown.			0
					1: PSDF flag clear
				When this item is set to 1, this
				setting automatically returns to 0
				after returning the PSDF flag to 0.
	3-0	ERRS	Error code	When this setting is changed and the	0: Latest error
			selection	ERRC setting is read out, the error
				contents (as many as 16 errors) of	1: Previous error
				the module that have occurred in the	2:		0
				past can be checked.	|
				If more than 16 errors have occurred,	E:
				the error code is updated starting	F: Oldest error
				from the oldest error.

– 18 –

Sub	Data								Setting [hex]
		Symbol	Item			Function
Address	bit								RANGE		INITIAL
											value
			Power	The PWMAX setting is switched to					When password is
				constant brightness (peak electric
	7	PWMP	Maximam						set		0
				power) control. The password setting
			peek control						0:OFF 1:ON
				is necessary to turn on this setting.
	6	-	-	Be sure to use the display with the					0-1		0
				setting fixed to 0.
				PWMP=0		Setting of the maximum			0: -40W
						electric power.			1: -20W
									2: ±0W
28									3: +20W
			Maximum
				PWMP=1		Setting of peak electric					2
	5-4	PWMAX	power
						power. Electric power by			0: ±0W
			consumption
						which electric power is
									1: +20W
						permitted in addition to
						improve practical			2: +30W
						brightness to the			3: +40W
						maximum electric power
						set 3:+20W
	3-0	-	-	Be sure to use the display with the					0~F		0
				setting fixed to 0.
				Password of peak electric power
		PWM	Password of	setting.The password is described to					51: Permission of
				the delivery specifications. When the
29	7-0		peak electric						PWMP ON		FF
		PASS		password setting is normally done,
			power setting						Another: Prohibition
				the reading value of the real thing
				ground becomes 51.
			Password of	If ‘AA” is written, VRPOL setting can
2A	7-0	VRPASS	VRPOL	be changed.					00~FF		00
			setting
	7-4	-	-	-					0~F		0
				Setting of wait time for Vs/Va
2B				stabilization at the time of start up
	3-0	RISTIM	RISe TIMe	sequence.					0~F		5
				Wait time [ms] = 200×Set value
				(Ma x:3000[ms])
				The maximum				When the
				electric power				amount of an
2C	7-0	PsTPW	Ps-Tank	setting:				over electric	00-FF		28
			PoWer	The maximum				power becomes
				over electric				PsTPW×PsTTM
								or less at
				power from +20W
								PWMP=1, the
				Time which can
								control by which
			Ps-Tank	operate by the				brightness is	00-FF		3C
2D	7-0	PsTTM		maximum over				lowered is
			TiMe
				electric power				done.
				(*10sec)

– 19 –

Sub	Data					Setting [hex]
		Symbol	Item		Function
Address	bit					RANGE		INITIAL
								value
	7-4	-	-	Be sure to use the display with the
				setting fixed to C.
				Setting of Vrs/Vra output polarity.
			Voltage	Set in the following procedures.		0: POSI
30				1) Write “AA” in the address 2A.				0
	3	VRPOL	Reference
				2) Write “0” or “1” in this address.		1:NEGA
			POLarity
				3) Write other than “AA” in the
				address 2A.
	2-0	-	-	Be sure to use the display with the
				setting fixed to 0.
			Reverse γ	Sets the input level that implements		00~FF		1F
31	7-0	GAM00	correction
				the forced 0 [LSB] output.
			DC
32	7-2	-	<no use>	-		00~FF		00
	1-0	GAM01[9: 8]	Reverse γ	Reverse γ coefficient value is set.
33	7-0	GAM01[7: 0]	coefficient 01	Input Output value of 8 [LSB]		00~FF		04
34	7-3	-	<no use>	-		00~FF		00
	2-0	GAM02[10: 8]	Reverse γ	Reverse γ coefficient value is set.
35	7-0	GAM02[7: 0]	correction 02	Input Output value of 16 [LSB]		00~FF		24
	7-4	-	<no use>	-
36	3-0	GAM03[11:8]	Reverse γ	Reverse γ coefficient value is set.		00~FF		00
			correction 03	Input Output value of 24 [LSB]
37	7-0	GAM03 [7: 0]				00~FF		58
	7-4	-	<no use>	-
38	3-0	GAM04[11: 8]	Reverse γ	Reverse γ coefficient value is set.		00~FF		00
			correction 04	Input Output value of 32 [LSB]
39	7-0	GAM04[7: 0]				00~FF		A7
3A	7-5	-	<no use>	-		00~FF		01
	4-0	GAM05[12: 8]	Reverse γ	Reverse γ coefficient value is set.
3B	7-1	GAM05[7: 1]	correction 05	Input Output value of 40 [LSB]		00~FF		12
	0	-	<no use>	-
3C	7-5	-	<no use>	-		00~FF		01
	4-0	GAM06[12: 8]	Reverse γ	Reverse γ coefficient value is set.
3D	7-1	GAM06[7: 1]	correction 06	Input	Output value of 48 [LSB]	00~FF		9A
	0	-	<no use>	-
3E	7-5	-	<no use>	-		00~FF		02
	4-0	GAM07[12: 8]	Reverse γ	Reverse γ coefficient value is set.
3F	7-2	GAM07[7: 2]	correction 07	Input	Output value of 56 [LSB]	00~FF		40
	1-0	-	<no use>	-

– 20 –

Sub	Data						Setting [hex]
		Symbol	Item		Function
Address	bit						RANGE		INITIAL
									value
40	7-5	-	<no use>	-		00~FF			03
	4-0	GAM08[12: 8]	Reverse γ	Reverse γ coefficient value is set.
41	7-2	GAM08[7: 2]	correction 08	Input	Output value of 64 [LSB]				04
						00~FF
	1-0	-	<no use>	-
42	7-6	-	<no use>	-		00~FF			04
	5-0	GAM09[13: 8]	Reverse γ	Reverse γ coefficient value is set.
43	7-4	GAM09[7: 4]	correction 09	Input	Output value of 80 [LSB]	00~FF			F0
	3-0	-	<no use>	-
44	7-6	-	<no use>	-		00~FF			07
	5-0	GAM11[13: 8]	Reverse γ	Reverse γ coefficient value is set.
45	7-4	GAM11[7: 4]	correction 10	Input	Output value of 96 [LSB]	00~FF			60
	3-0	-	<no use>	-
46	7-6	-	<no use>	-		00~FF			0A
	5-0	GAM11[13: 8]	Reverse γ	Reverse γ coefficient value is set.
47	7-4	GAM11[7: 4]	correction 11	Input	Output value of 112 [LSB]	00~FF			50
	3-0	-	<no use>	-
48	7-6	-	<no use>	-		00~FF			0D
	5-0	GAM12[13: 8]	Reverse γ	Reverse γ coefficient value is set.
49	7-4	GAM12[7: 4]	correction 12	Input	Output value of 128 [LSB]	00~FF			D0
	3-0	-	<no use>	-
4A	7-6	-	<no use>	-		00~FF			16
	5-0	GAM13[13: 8]	Reverse γ	Reverse γ coefficient value is set.
4B	7-4	GAM13[7: 4]	correction 13	Input	Output value of 160 [LSB]	00~FF			A0
	3-0	-	<no use>	-
4C	7-6	-	<no use>	-		00~FF			21
	5-0	GAM14[13: 8]	Reverse γ	Reverse γ coefficient value is set.
4D	7-4	GAM14[7: 4]	correction 14	Input	Output value of 192 [LSB]	00~FF			E0
	3-0	-	<no use>	-
4E	7-6	-	<no use>	-		00~FF			2F
	5-0	GAM15[13: 8]	Reverse γ	Reverse γ coefficient value is set.
4F	7-4	GAM15[7: 4]	correction 15	Input	Output value of 224 [LSB]	00~FF			90
	3-0	-	<no use>	-
50	7	-	<no use>	-		00~FF			40
	6-0	GAM16[14: 8]	Reverse γ	Reverse γ coefficient
51	7-5	GAM16[7: 5]	correction 16	Input	Output value of 256 [LSB]	00~FF			00
	4-0	-	<no use>	-

– 21 –

Sub	Data					Setting [hex]
		Symbol	Item	Function
Address	bit					RANGE		INITIAL
								value
E5	7-0	UVrs	USER Vrs	Setting Vrs voltage	Standard	00~AA		Adjusted
				equation: Vrs=2.99*UVrs/255				in factory
E6	7-0	UVra	USER Vra	Setting Vra voltage	Standard	00~AA		Adjusted
				equation: Vra=2.99*UVra/255				in factory
	7-3			Be sure to use the display with the		0		0
				setting fixed to 0.
				Resetting the UVrs, UVra in both of
			UVrs/UVra	register and EEPROM to the initial		0:Normal
	2	RCLVr		value by setting RCLVr to 1.		1: UVrs,UVra		0
			RECALL
				This setting automatically returns to		initialized
FE				0 after resetting the UVrs,Uvra.
				Storing the UVrs,UVra	in register	0:Normal
			UVrs/UVra	to EEPROM by setting EWRVr to 1.
	1	EWRVr				1: UVrs,UVra		0
			Write	This setting automatically returns to
						stored in EEPROM
				0 after resetting the UVrs,UVra.
	0			Be sure to use the display with the		0		0
				setting fixed to 0.
	7-1			Be sure to use the display with the		0		0
				setting fixed to 0.
				When the DSETEN setting is 1,
FF				setting this bit causes all the register
				setups that have been set up to now,		0: Normal
	0	DSET	Data setup	to be reflected to the operation status				0
						1: Execute
				of this product. They are reflected
				from the next field after this bit is
				accepted.

– 22 –