Page 1
—1—
E96638-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Description
The CXB1572Q achieves the 2R optical-fiber
communication receiver functions (Reshaping and
Regenerating) on a single chip. This IC is also
equipped with the signal interruption alarm output
function, which is used to discriminate the existence
of data input.
Features
• Auto-offset canceler circuit
• Signal interruption alarm output
• 2-level switching function of identification maximum voltage amplitude for alarm block
• Single 3.3 V power supply
Applications
• FDDI : 125 Mb/s
• SONET/SDH : 155.52 Mb/s
• ESCON : 200 Mb/s
• Fiber channel : 265.625 Mb/s
• ATM : 155.52 Mb/s
Absolute Maximum Ratings
• Supply voltage VCC – VEE –0.3 to +7.0 V
• Storage temperature Tstg –65 to +150 °C
• Input voltage difference : I VD – VD I Vdif 0 to +2.5 V
• SW input voltage Vi VEE to VCC V
• Output current (Continuous) IO 0 to 50 mA
(Surge current) 0 to 100 mA
Recommended Operating Conditions
• Supply voltage VCC – VEE 3.0 to 3.6 V
• Termination voltage (for data/alarm) VCC – VT1 1.8 to 2.2 V
• Termination voltage (for alarm 2) VT2 VEE V
• Termination resistance (for data/alarm)RT1 46 to 56 Ω
• Termination resistance (for alarm 2) RT2 460 to 560 Ω
• Operating temperature Ta –40 to +85 °C
Structure
Bipolar silicon monolithic IC
Post amplifier for Optical Fiber Communication Receiver
32 pin QFP (Plastic)
CXB1572Q
Page 2
—2—
CXB1572Q
Block Diagram and Pin Configuration
Q
V
CC
DA
SD
Q
SD
V
CC
D
V
CC
DA
VCCA
UP
DOWN
CAP2
CAP3
NC
NC
NC
V
CCA
V
CCD
V
EEA
V
EED
NC
CAP1
R2K
R3K
peak hold
Limiting
Amplifier
Block
peak hold
Alarm
Block
29
26
32
30
31
28
27
20
25
23
22
21
18
19
8
2
1
6
7
5
16
14
12
11
10
9
13
15
R1
R2
R1
R2
4
3
∆V
R3
R4
24
CAP1
V
CC
P
V
EE
I
SW
V
CC
A
D
D
V
CC
A
Rp
17
NC
Page 3
—3—
CXB1572Q
Pin Description
60k
40k
V
REF
VEEA
V
CCA
4
31
30
VccA
V
EEA
SW
986
123.4
123.4
Vcs
3
2
1
5
32
VCCA
V
EEA
100
100
1.5k
1.5k
10k
10k
100p
200
200
3k
2k
5
6
11
10
9
8
Typical pin
Pin No. Symbol voltage (V) Equivalent circuit Description
DC AC
1
2
3
4
5
6
7
8
9
10
11
VCCP
VCCA
VEEI
SW
D
D
VCCA
CAP1
R2K
R3K
CAP1
0 V
–3.3 V
0 V
(OPEN)
or
–3.3 V
–1.3 V
–1.3 V
0 V
–1.8 V
–1.8 V
–0.9 V
to
–1.7 V
–0.9 V
to
–1.7 V
Positive power supply for
external power supply.
Generates the default voltage
between UP and DOWN.
The voltage (5.3 mV for input
conversion) can be generated
between UP and DOWN
(Pins 30 and 31) as alarm setting
level 1 by this pin to Open.
The voltage (12 mV for input
conversion) can be generated as
alarm setting level 2 by
connecting this pin to VEEA.
Switches the identification
maximum voltage amplitude.
High voltage when open; the
identification maximum voltage
amplitude becomes 50 mVp-p.
Low voltage when connecting
this pin to VEE; the amplitude
becomes 20 mVp-p.
Limiting amplifier block input.
Be sure to make this input with
AC coupled.
Positive power supply for analog
block.
Pins 8 and 11 connect a capacitor
which determines the cut-off
frequency for feedback block, and
2 kΩ is connected between Pins 8
and 9; 3 kΩ between Pins 10 and
11. A resistor which is to be
inserted in parallel with a capacitor
can be selected 5 ways by
external wiring, and DC feedback
gain can be varied due to
compensate the input duty cycle
distortion.
Page 4
—4—
CXB1572Q
Typical pin
Pin No. Symbol voltage (V) Equivalent circuit Description
DC AC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VEEA
VCCA
VEED
VCCD
NC
Q
Q
VCCDA
SD
SD
VCCDA
VCCD
NC
–3.3 V
0 V
–3.3 V
0 V
0 V
0 V
0 V
–0.9 V
to
–1.7 V
–0.9 V
to
–1.7 V
–0.9 V
to
–1.7 V
–0.9 V
to
–1.7 V
Negative power supply for
analog block.
Positive power supply for analog
block.
Negative power supply for digital
block.
Positive power supply for digital
block.
No connected.
Data signal output.
Terminate this pin in 50 Ω at
VTT = –2 V.
Positive power supply for output
buffer.
Alarm signal output.
Terminate this pin in 50 Ω at
VTT = –2 V.
Positive power supply for digital
block.
Positive power supply for digital
block.
No connected.
CCDA
V
19
18
VEED
CCDA
V
VEED
21
22
Page 5
—5—
CXB1572Q
Typical pin
Pin No. Symbol voltage (V) Equivalent circuit Description
DC AC
28
29
30
31
32
CAP3
CAP2
DOWN
UP
VCCA
–1.8 V
–1.8 V
–1090 mV
(for
VEEI
= –3.3 V)
–1020 mV
(for
VEEI
= –3.3 V)
0 V
Connects a peak hold circuit
capacitor for alarm block. 470 pF
should be connected to VCCA
each.
CAP2 pin → Peak hold
capacitor connection for
alarm level setting block.
CAP3 pin → Peak hold
capacitor connection for
limiting amplifier signal.
Connects a resistor for alarm
level setting.
Default voltage can be generated
without an external resistor.
(Please refer to pin description of
pin No. 3.)
Positive power supply for analog
block.
31
30
29
80
10p
200 200
28
80
10p
VCCA
5µA
5µA
V
EEA
VccA
986
123.4
123.4
Vcs
SW
EEA
V
3
Page 6
—6—
CXB1572Q
Power supply
Q/Q SD/SD High output voltage
Q/Q SD/SD Low output voltage
SD/SD High output voltage 2
SD/SD Low output voltage 2
SW High input voltage
SW Low input voltage
SW High input current
SW Low input current
D/D input resistance
Internal resistance 1 for alarm level
setting
Internal resistance 2 for alarm level
setting
Resistance between VCCA and VCCP
Pare ratio of internal resistance 2 for
alarm level setting
Resistance between CAP1 and R2K
Resistance between CAP1 and R3K
Electrical Characteristics
• DC characteristics
(VCC = GND, VEE = –3.0 V to –3.6 V, Ta = –40 to +85 °C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA)
Item
IEE
VOH
VOL
VOHb
VOLb
VIH
VIL
IIH
IIL
Rin
Ra1
Ra2A, B
RP
δRa2
R3
R4
RT1 = 51 Ω,
V
T1 = VCC–2 V
termination,
Ta=0 to 85 °C
RT2 = 510 Ω,
VT2 =VEE termination,
Ta=0 to 85 °C
Refer to Fig. 3.
Refer to Fig. 3.
Ra2A/Ra2B
–56
–1025
–1810
–1025
–1860
–500
VEE
–60
1109
739
93
3.3
0.97
1470
2210
–40
1479
986
123
5
1970
2960
–29
–830
–1550
–700
–1500
0
VEE+500
2
1849
1233
154
6.9
1.03
2470
3700
mA
mV
µA
Ω
Ω
Symbol Min. Typ. Max. UnitConditions
Page 7
—7—
CXB1572Q
Maximum input voltage amplitude
Amplifier gain
(except for output buffer)
Identification maximum voltage
amplitude of alarm level
Hysteresis width
SD response assert time
SD response deassert time
SD response assert time for alarm
level default
SD response deassert time for alarm
level default
Alarm setting level 1 for default
Alarm setting level 2 for default
Propagation delay time
Q/Q SD/SD rise time
Q/Q SD/SD fall time
• AC characteristics
(VCC = GND, VEE = –3.0 V to –3.6 V, Ta = –40 to +85 °C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA)
Item
Vmax
GL
VminA1
VminA2
∆P
Tas
Tdas
Tasd
Tdasd
Vdef1
Vdef2
TPD
Tr
Tf
1600
52
20
50
3
0
2.3
0
2.3
4.3
10.5
1.2
0.45
0.45
6
5.3
12.0
1.7
0.85
0.85
7
100
100
100
100
6.3
13.5
2.6
1.3
1.3
mVpp
dB
mVpp
dB
µs
mV
ns
Symbol
Min.
Typ.
Max. Unit
Conditions
∗1
VUP – VDOWN = 100 mV, Vin = 100 mVpp (single ended), SW pin: High
Peak hold capacitance of 470 pF; connect VEEI to VEE.
∗2
VUP – VDOWN = 100 mV, Vin = 1 Vpp (single ended), SW pin: High
Peak hold capacitance of 470 pF; connect VEEI to VEE.
∗3
Vin = 50 mVpp (single ended), SW pin: Low
Peak hold capacitance of 470 pF; connect VEEI to VEE.
∗4
Vin = 1 Vpp (single ended), SW pin: Low
Peak hold capacitance of 470 pF; connect VEEI to VEE.
Single-ended input
SW pin: Low,
single-ended input
SW pin: Open High,
single-ended input
Alarm level is default
value
Low → High
∗1
High → Low
∗2
Low → High
∗3
High → Low
∗4
UP,DOWN,VEEI pins
;Open,connect SW pin
to VEE
UP,DOWN,SW pins
;Open,connect VEEI to
VEE
D to Q
RT1 = 50 Ω, VT1 =
VCC–2 V termination
,
VEE=–3.3 V,
Ta=0 to 85 °C
20 % to 80 %
Page 8
—8—
CXB1572Q
DC Electrical Characteristics Measurement Circuit
V V V
V
51
51
51 51
C3
C3
V
V
V
V
V
VS
VD
C1
C1
A
VEE
–5V
V
C2
V
–2V
V
T1
V
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
peak hold
∆V
peak hold
Alarm
Block
Limiting
Amplifier
Block
R1
R1
R2
R2
R3
R4
RP
Page 9
—9—
CXB1572Q
AC Electrical Characteristics Measurement Circuit
Z0=50
Z0=50
Z0=50
Z0=50
Oscilloscope
50Ωinput
0.22µF
0.022µF
0.022µF
VEE VCC
+3V
+2V
V
REX1
REX2
470pF
470pF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
peak hold
∆V
peak hold
Alarm
Block
Limiting
Amplifier
Block
R1
R1
R2
R2
R3
R4
RP
Page 10
—10—
CXB1572Q
Application Circuit
C2
0.22µF
C1
0.022µF
VEE
–5V
C1
0.022µF
5151 51 51
VT1 –2V
2 3 4 5 6 7 8
9
10
11
12
13
14
15
16
1718192021222324
25
26
27
28
29
30
31
32
1
peak hold
peak hold
Alarm
Block
Limiting
Amplifier
Block
R1
R1
R2
R2
R3
R4
RP
V∆
C3
330pF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 11
—11—
CXB1572Q
C1
C1
C2
R1
R1
R2
R2
To IC interior
D
R3
R4
5
6
8
9
10
11
Fig. 1
f1 f2
Frequency
Gain
Feedback
frequency response
Amplifier
frequency response
Fig. 2
Notes on Operation
1. Limiting amplifier block
The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and
C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and
IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external
capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since
peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on
the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target
values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input
is used, provide AC grounding by connecting Pin 6 to a capacitor which has the same capacitance as
capacitor C1.
R1 (internal): 1.5 kΩ R2 (internal): 10 kΩ
f2: 4.8 kHz f1: 72 Hz
C1 (external): 0.022 µF C2 (external): 0.22 µF
2 kΩ is incorporated between Pins 8 and 9; 3 kΩ between Pins 10 and 11. A resistance value which is to be
inserted in parallel with a capacitor C2 can be selected 5 ways (∞, 5 kΩ, 3 kΩ, 2 kΩ, 2 k//3 kΩ) by external
wiring, and DC feedback can be varied.
Page 12
—12—
CXB1572Q
2. Alarm block
In order to operate the alarm block, give the voltage difference between Pins 30 and 31 to set an alarm level
and connect the peak hold capacitor C3 shown in Fig. 3.
This IC has two setting methods of alarm level; one is to leave Pins 30 and 31 open to set an alarm level
default value (5.3 mV or 12 mV for input conversion). Default value of alarm level is 5.3 mV for input
conversion by leaving Pin3 to open,12 mV by connecting Pin3 to VEE. The other is to connect Pin 3 to VEE and
set a desired alarm level using the external resistors REX1 and REX2 and REX3 shown in Fig. 3.
Connect REX1 between Pins 30 and 31, or connect REX3 between Pin 30 and VCC when less alarm level is
desired to be set than its default value; connect REX2 between Pin 31 and VCC potential when more alarm level
is desired to be set than its default value. However, the Pin 31 voltage must be higher than that of Pin 30.
Refer to Figs. 7 to 9 for this alarm level setting.
This IC also features two-level setting of identification maximum voltage amplitude for the alarm function. The
amplitude is set to 50 mVp-p when Pin 4 is left open (High level) and it is set to 20 mVp-p when Pin 4 is Low
level. Therefore, noise margin can be increased by setting Pin 4 to Low level when small signal is input. The
relation of input voltage and peak hold output voltage is shown in Fig. 5.
In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to
maintain a constant gain (design target value: 6 dB) as shown in Fig. 4. The C3 capacitance value should be
set so as to obtain desired assert time and deassert time settings for the alarm signal.
The electrical characteristics for the SD response assert and deassert times are guaranteed only when the
waveforms are input as shown in the timing chart of Fig. 6.
The typical values of REX1, REX2, REX3 and C3 are as follows: (Approximately 10 pF capacitor is built in Pins 28
and 29 each.)
REX1 : 400 Ω (when the alarm level is set to 3 mV for input conversion.Pin3; open,connect Pin4 to VEE)
REX2 : 4k Ω (when the alarm level is set to 15 mV for input conversion.connect Pin3 to VEE, Pin4; open)
REX3 : 6.2 kΩ (when the alarm level is set to 3 mV for input conversion.Pin3; open,connect Pin4 to VEE)
C3 : 470 pF
The table below shows the alarm logic.
From Limiting
Amplifier
Peak hold
SD
SD
VccA
10p
VccA
10p
Vcc
C3
Vcc
Peak hold
Ra1, Ra2A and Ra2B values
are typical values
C3
∆V
31
30
29
28
Vcc
R
EX1
REX2
4
3
Vcc
R
EX3
Ra2B
123.4
Ra1
VCCA
Internal IC
External IC
30
31
Ra2A
123.4
986
Vcs
3
VEEA
Optical signal input state
Signal input
Signal interruption
High level
Low level
Low level
High level
SD SD
Fig. 3
Page 13
3dB 3dB
Alarm setting
input level
Hysteresis
Input electrical signal amplitude
SD output
High
level
Low
level
Small Large
V
DAS VAS
VDAS → Deassert level
VAS → Assert level
—13—
CXB1572Q
Fig. 4 Fig. 5
Assert time
Alarm setting level
Hysteresis width
Data input
(D)
Deassert time
Data output
(Q)
Alarm output
(SD)
Fig. 6
Fig. 7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
2
10
3
10
4
REX1 (Ω)
Alarm setting level (mV)
VEEI=open
SW=VEE
Ta=27˚C
Peak hold output voltage
0 20mVpp 50mVpp
Input voltage (Vp-p)
SW→Open High
SW→Low
Page 14
—14—
CXB1572Q
3. Others
Pay attention to handling this IC because its electrostatic discharge strength is weak.
A
A
A
A
A
A
A
A
10
15
20
25
30
35
10
1
10
2
10
3
10
4
10
5
Alarm setting level (mV)
VEEI=VEE
SW=open
Ta=27˚C
REX2 (Ω)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
3
10
4
10
5
REX3 (Ω)
Alarm setting level (mV)
VEEI=open
SW=VEE
Ta=27˚C
Fig. 8 Fig. 9
Page 15
—15—
CXB1572Q
Example of Representative Characteristics
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
0.2 0.4 0.6 0.8 1 1.2
Bit error rate vs. Input amplitude level
Data input level (mVp-p)
Bit error rate
VEE=–3.3V
Ta=27°C
D=155.52Mb/s
Vin=3mVp-p, Single Input
pattern : PRBS223–1
Fig. 10
Fig. 11
Output RMS Jitter vs. Data input level
70
60
50
40
30
20
10
0
1 10 100 1000
Data input level (mVp-p)
Output RMS Jitter (ps)
VEE=3.3V
Ta=27°C
D=155.52Mbps
Vin=3mVp-p, Single Input
pattern : PRBS223–1
Q Output waveform
16.4400ns 26.4400ns 36.4400ns
Ch. 1 = 200.0 mVolts/div
Timebase = 2.00 ns/div
Offset = 680.0 mVolts
Delay = 26.4400 ns
VEE=3.3V
Ta=27°C
D=155.52Mbps
Vin=3mVp-p, Single Input
pattern : PRBS223–1
Page 16
Package Outline Unit : mm
CXB1572Q
32PIN QFP (PLASTIC)
9.0 ± 0.2
+ 0.3
7.0 – 0.1
1724
0.24
16
9
M
25
32
1
0.8
+ 0.15
0.3 – 0.1
8
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
0° to 10°
0.1 – 0.1
0.1
(8.0)
+ 0.2
0.50
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-32P-L01
QFP032-P-0707
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
—16—
EPOXY RESIN
SOLDER PLATING
42 ALLOY
0.2g
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