Page 1
—1—
E97319C83-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VCC –0.3 to 4 V
• Operating temperature Topr –55 to +70 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation
PD to 1109 mW
Operating Conditions
Supply voltage VCC 3.14 to 3.46 V
Description
The CXB1586AR is a transceiver IC with a built-in
PLL for Fibre Channel. For a receiver 1.0625
Gbaud serial data is received and output it as the
10-bit parallel data; for transmitter 1.0625 Gbaud 10bit parallel data is output as the serial data.
Features
• Transmitter and receiver in a single chip
• ANSI X3T11 Fibre Channel compatible (FC_0) at
1.0625 Gbaud
• Conforms to 10-bit interface specification
• TTL / ECL compatible
• Single +3.3 V power supply
• PLL for clock generation and clock / data recovery
• Byte sync detector (positive character of comma)
• Local loop back circuit
• Low power consumption (0.8 W typ.)
• 64-pin plastic LQFP package (10 mm × 10 mm)
Applications
1.0625 Gbaud Fibre channel
Structure
Bipolar silicon monolithic IC
10 Bit 1.0625 Gbaud Transceiver
64 pin LQFP (Plastic)
CXB1586AR
For the availability of this product, please contact the sales office.
Page 2
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CXB1586AR
Block Diagram
Pin Configuration (Top View)
TX0-9
D Q
10 10
Pin
P/S Conv.
Sout
LCKREF∗
LBEN
SDOUT∗
SDOUT
REFCLK
(106.25M)
TX_PLL
LCLK
(106.25M)
TCLK
(1.0625G)
REFCLK
LPF_TX0
LPF_TX1
RCLK (1.0625G)
RDATA
1/10
PX_PLL
S/P
Conv.
RX0-9
BYTSYNC
1/2
FCLK (106.25M)
RBC1
RBC0
SDIN∗
SDIN
LPF_RX0
LPF_RX1
BYTSYNCEN
1
0
10
56
LPF_RX1
VCCP_RX
VEEP_RX
SDIN∗
VCCE
SDIN
VCCG
VEEG
VCCG
VEEG
VCCG
VCCE
SDOUT∗
SDOUT
VCCE
VEEE
VEET
RBC0
RBC1
VCCT
VCCG
LCKREF∗
TEST∗
VEEG
BYTSYNCEN
VCCG
REFCLK
VEEG
VCCG
LBEN
VCCP_TX
LPF_TX1
LPF_RX0
BYTSYNC
VEET
RX0
RX1
RX2
VCCT
RX3
RX4
RX5
RX6
VCCT
RX7
RX8
RX9
VEET
VEET
TX0
TX1
TX2
VCCG
TX3
TX4
TX5
TX6
VCCG
TX7
TX8
TX9
VEET
VEEP_TX
LPF_TX0
49
48 40 33
32
17
24
1681
64
Page 3
—3—
CXB1586AR
DC Characteristics (under the recommended conditions)
Symbol
VIH_T
VIL_T
IIH_T
IIL_T
VOH_T
VOL_T
VIH_E
VIL_E
VIS_E
1)
VOH_E
VOL_E
VOS_E
2)
ICC
PD
Item
TTL high level input voltage
TTL low level input voltage
TTL high level input current
TTL low level input current
TTL high level output voltage
TTL low level output voltage
ECL high level input voltage
ECL low level input voltage
ECL peak-to-peak differential
input voltage swing
ECL high level output voltage
ECL low level output voltage
ECL peak-to-peak differential
output voltage swing
Current consumption
Power dissipation
Min.
2
0
–400
2.2
VCC–1.17
VCC–1.81
400
VCC–1.05
VCC–1.81
1200
Typ.
250
825
Max.
5.5
0.8
20
0.5
VCC–0.88
VCC–1.48
2000
VCC–0.81
VCC–1.55
1900
320
1109
Unit
V
V
µA
µA
V
V
V
V
mV
V
V
mV
mA
mW
Conditions
Vin=VCC
Vin=0
IOH=–0.4 mA
IOL=2 mA
AC coupling input
50 Ω terminated
to VCC–2 V
50 Ω terminated
to VCC–2 V
Output pins open
Output pins open
Note :
1) ECL peak-to-peak differential input voltage swing
2) ECL peak-to-peak differential output voltage swing
Vi1
Voltage
VCC
VIH_E
VIL_E
VEE=GND
signal-in
+
signal-in
–
Vi2
1) VIS_E= |Vi1| + |Vi2|
Vo1
Voltage
VCC
VOH_E
VOL_E
VEE=GND
signal-out
+
signal-out
–
Vo2
2) VOS_E= |Vo1| + |Vo2|
Page 4
—4—
CXB1586AR
AC Characteristics (under the recommended operating conditions)
Symbol
Tir_TX
Tif_TX
Tir_REF
Tif_REF
Tor_T
Tof_T
Tor_E
Tof_E
Tp_REF
DC_REF
Ftol_REF
Ts_TX
Th_TX
Ts_RX
Th_RX
Tsk_RBC
DC_RBC
DJ
RJ
JT
Item
TTL input rise time of TX
TTL input fall time of TX
TTL input rise time of REFCLK
TTL input fall time of REFCLK
TTL output rise time
TTL output fall time
ECL output rise time
ECL output fall time
REFCLK period
REFCLK duty cycle
REFCLK frequency tolerance
TX setup time to REFCLK
TX hold time to REFCLK
RX setup time to RBC
RX hold time to RBC
Skew between RBC0 and 1
RBC duty cycle
Deterministic jitter (p-p)
Random jitter (p-p)
Jitter tolerance
Min.
0.7
0.7
0.7
0.7
9.26
40
–100
2
1.5
3
1.5
Tp/2–0.5
40
Typ.
9.41
Tp/2
0.02
0.18
Max.
4.8
4.8
2.4
2.4
3.5
3.5
400
400
9.56
60
100
Tp/2+0.5
60
0.07
0.23
0.7
Unit
ns
ns
ns
ns
ns
ns
ps
ps
ns
%
ppm
ns
ns
ns
ns
ns
%
UI
UI
UI
Conditions
0.8 V to 2.0 V
2.0 V to 0.8V
0.8 V to 2.0 V
2.0 V to 0.8 V
0.8 V to 2.0 V,
CL=10 pF
2.0 V to 0.8 V,
CL=10 pF
20 % to 80 %, CL=2 pF
20 % to 80 %, CL=2 pF
Tp is period of RBC
in frequency lock
Serial data output
(k28.5)
Serial data output
Serial data input
Page 5
—5—
CXB1586AR
PLL AC Characteristics (under the recommended operating conditions)
Symbol
Tfa
Tbs
Item
Frequency acquisition time of
TX and RX PLL
Bit synchronization time of RX
PLL
Min. Typ. Max.
500
2500
Unit
µs
bit
Conditions
Loop damping
capacitor=0.01 µF
Recommended Operating Conditions
Symbol
VCC
Ta
Item
Supply voltage
(Including VCCT5)
Ambient temperature
Min.
3.135
0
Typ.
3.3
Max.
3.465
70
Unit
V
°C
Remarks
Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP=GND)
Symbol
VCC
VI_T
VI_E
VIS_E
IOH_T
IOL_T
IO_E
Ta
Tstg
Item
Power supply voltage
(Except VCCT5)
TTL DC input voltage
ECL DC input voltage
ECL peak-to-peak differential
input voltage swing
TTL output current (High level)
TTL output current (Low level)
ECL output current
Ambient temperature
Storage temperature
Min.
–0.3
–0.5
VCC–2
–4
–20
0
–30
–55
–65
Typ. Max.
4
5.5
VCC
4
0
20
0
70
150
Unit
V
V
V
V
mA
mA
mA
°C
°C
Remarks
Under bias
Page 6
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CXB1586AR
Pin description
Symbol
VEET
TX0-9
VCCG
VEEP_TX
LPF_TX0
LPF_TX1
VCCP_TX
LBEN
VEEG
REFCLK
BYTSYNCEN
TEST
∗
LCKREF
∗
VCCT
RBC1
RBC0
RX0-9
BYTSYNC
LPF_RX0
LPF_RX1
VCCP_RX
VEEP_RX
Pin No.
1, 14, 32,
33, 46
2-4, 6-9,
11-13
5, 10, 20,
23, 28, 55,
57, 59
15
16
17
18
19
21, 25,
56, 58
22
24
26
27
29, 37, 42
30
31
34-36,
38-41,
43-45
47
48
49
50
51
Type
PS
I_TTL
PS
PS
EX
PS
I_TTL
PS
I_TTL
I_TTL
I_TTL
I_TTL
PS
O_TTL
O_TTL
O_TTL
EX
PS
PS
Equivalent
circuit
—
(a)
—
—
(e)
—
(a)
—
(a)
(a)
(a)
(a)
—
(b)
(b)
(b)
(e)
—
—
Description
Ground for TTL output : Normally 0 V.
Parallel transmit data inputs to be serialized.
TX0 is serialized first and TX9 is last.
Power supply for internal logic gates :
Normally 3.3 V.
Ground for TX PLL : Normally 0 V.
Connect to external loop filter of TX PLL. Connect a
capacitor (0.01 µF) between LPF_TX0 and LPF_TX1.
Power supply for TX PLL : Normally 3.3 V.
Loop back enable : When high, TX serializer output
internally connects to RX deserializer input,
SDOUT/SDOUT∗is held low/high, and SDIN/SDIN∗is
disabled. When low, SDOUT/SDOUT∗and
SDIN/SDIN∗are enabled.
Power supply for internal logic gates :
Normally 0 V.
Reference clock for PLL and transmit byte clock
(106.25 MHz). Supplied by the host system.
Byte synchronization enable : When high, the positive
comma character (0011111) detection circuit is
enabled to establish byte synchronization (see Timing
Chart).
Test pin : Normally 3.3 V or open.
Lock to reference clock : An active low input.
LCKREF∗forces the PLL lock to the REFCLK supplied
by the host system.
Power supply for TTL output : Normally 3.3 V.
Receive byte clocks recovered from the serial data
(53.125 MHz). These clocks are 180 degrees out of
phase, and RX0-9 are alternatively clocked on the
rising edge of these clocks (see Timing Chart)
Parallel receive data output :
RX0 is received first and RX9 is last.
Byte synchronization indicator : High when a positive
comma character is detected (see Timing Chart)
Connect to external loop filter of RX PLL. Connect a
capacitor (0.01 µF) between LPF_RX0 and LPF_RX1.
Power supply for RX PLL : Normally 3.3 V.
Ground for RX PLL : Normally 0 V.
Page 7
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CXB1586AR
Pin Type Definition
Type
PS
I_TTL
O_TTL
I_ECL
O_ECL
EX
Definition
Power supply or ground
Input TTL
Output TTL
Input ECL
Output ECL
External circuit node
Symbol
SDIN∗
SDIN
VCCE
SDOUT∗
SDOUT
VEEE
Pin No.
52
54
53, 60, 63
61
62
64
Type
I_ECL
(Diff.)
PS
O_ECL
(Diff.)
PS
Description
Serial receive data inputs :
These inputs are enabled when LBEN is low.
Power supply for ECL output : Normally 3.3 V
Serial transmit data output : These outputs are
enabled when LBEN is low. When LBEN is high,
SDOUT/SDOUT∗ is held to low/high.
Ground for ECL output :
Normally 0 V.
Equivalent
circuit
(c)
—
(d)
—
Page 8
—8—
CXB1586AR
Equivalent Circuit
VCCG
TTL-IN
VEET
(a) TTL input
VEET
VCCT3
TTL-OUT
VEET
(b) TTL output
VCCE - 1.3V
VCCE
ECL-IN
ECL-IN∗
VEEE
VCCG
VEEG
(c) ECL input
(d) ECL output
VCCE
VEEE
ECL-OUT
ECL-OUT∗
(e) LPF0/LPF1-pin
VEEP1
VCCP
LPF0
LPF1
VEEP2
Page 9
—9—
CXB1586AR
Timing Chart
TX0_a TX1_a TX2_a TX3_a TX4_a TX5_a
TX6_a
TX7_a TX8_a TX9_a TX0_b TX1_b TX2_b
TX0 - 9
REFCLK
SDOUT
(a) Transmiter Section Timing
TX_bTX_a
Tir_TX Tif_TX
Tir_REF Tif_REF
BYTSYNC
(b) Receiver Section Timing
RBC0
RBC1
RX0 - 9
2.0V
1.4V
0.8V
1.4V
0.8V
2.0V
2.0V
1.4V
0.8V
2.0V
1.4V
0.8V
2.0V
1.4V
0.8V
2.0V
1.4V
0.8V
Tor_T Tof_T
COMMA
(+)
VALID
DATA
VALID
DATA
VALID
DATA
Ts_RX
Th_RX
Ts_RX Th_RX
HOLD
HOLD
COMMA
(+)
Ts_TX Th_TX
Tskew
Page 10
—10—
CXB1586AR
Notes on Operation
1. External loop filters for PLLs
The CXB1586AR has two PLLs. One is for the transmitter and locks to the reference clock from REFCLK
input pin. Another one is for the receiver and locks to the received serial data from SDIN/SDIN∗input pins.
They need external capacitors for the their loop filters. Typical values of the external capacitors are
indicated below.
2. Example of power supply circuit
49
48
C2
17
16
C1
C1 : 0.01µF
C2 : 0.01µF
VCCT
3.3V
22µF 0.1µF
VEET
VCCG
VCCE
22µF 0.1µF
VEEG
VEEE
22µF 0.1µF
VCCP
VEEP
Page 11
—11—
CXB1586AR
3. High-speed ECL differential input
The high-speed ECL differential input pins are biased to VBB (VCC–1.3V) via a 18 kΩ resistor in the IC.
See the figures below for ECL differential input methods.
(a) ECL differential signal from 3.3V ECL output buffer
160Ω 160Ω
3.3V ECL output buffer
VCC=3.3V, VEE=GND
18kΩ18kΩ
ECL differential input buffer
VCC=3.3V, VEE=GND
VBB (VCC–1.3V)
330Ω 330Ω
ECL 100K output buffer
VCC=GND, VEE=–4.5V
18kΩ18kΩ
ECL differential input buffer
VCC=3.3V, VEE=GND
VBB (VCC–1.3V)
0.01µF
0.01µF
VEE
(b) ECL differential signal from ECL 100K output buffer
(c) differential signal from 75Ω transmission line (AC/DC termination)
(d) differential signal from 75Ω transmission line (AC termination)
75Ω 75Ω
18kΩ18kΩ
ECL differential input buffer
VCC=3.3V, VEE=GND
VBB (VCC–1.3V)
0.01µF
0.01µF
75Ω
TRANS.
LINE
18kΩ18kΩ
ECL differential input buffer
VCC=3.3V, VEE=GND
VBB (VCC–1.3V)
0.01µF
0.01µF
75Ω
TRANS.
LINE
75Ω 75Ω
0.01µF
Page 12
—12—
CXB1586AR
50Ω 50Ω
18kΩ18kΩ
ECL differential input buffer
VCC=3.3V, VEE=GND
VBB (VCC–1.3V)
0.01µF
0.01µF
VTT (VCC–2V)
50Ω
TRANS.
LINE
50Ω
18kΩ18kΩ
ECL differential input buffer
VCC=3.3V, VEE=GND
VBB (VCC–1.3V)
0.01µF
0.01µF
VTT (VCC–2V)
50Ω
TRANS.
LINE
(e) ECL differential signal from 50Ω transmission line
(f) ECL single signal from 50Ω transmission line
Page 13
—13—
CXB1586AR
Electrical Characteristics Measurement Circuit
Device under test
ECL_IN ECL_OUT
(a) TTL I/O DC characteristics measurement circuit
(b) TTL I/O AC characteristics measurement circuit
CL=10pF (including the probe capacitance)
(d) ECL I/O AC characteristics measurement circuit
CL≤2pF (input capacitance of the measurement equipment
and floating capacitance)
A
VI_T
II_T
V
IO_T VO_T
Device under test
TTL_IN TTL_OUT
Device under test
TTL_IN TTL_OUT
Pulse
generator
Probe
Oscilloscope
CL
(c) ECL I/O DC characteristics measurement circuit
A
VI_TE
II_E
VO_E
Device under test
ECL_IN ECL_OUT
V
50Ω
VCCE–2V
VCCE–2V
0.1µF
50Ω
VCCE–2V
50Ω
0.1µF
Pulse
generator
50Ω Transmission line
ECL_IN∗ ECL_OUT∗
50Ω
50Ω
VCCE–2V
VCCE–2V
Oscilloscope
Page 14
—14—
CXB1586AR
Pulse
pattern
generator
Attenuate
Error rate counter
50Ω
50Ω
VCCE–2V
VCCE–2V
0.1µF
0.1µF
531.25MHz
SDIN∗
SDIN
Device under test
SDOUT∗
SDOUT
REFCLK
RX0-9
TX0-9
parallel data
10bit
Oscilloscope
531.25MHz
50Ω
50Ω
VCCE–2V
VCCE–2V
106.25MHz
50Ω
50Ω
VCCE–2V
VCCE–2V
0.1µF
0.1µF
1.0625Gbps
SDIN∗
SDIN
Device under test
SDOUT∗
SDOUT
REFCLK
RX0-9
TX0-9
parallel data
10bit
1.0625Gbps
50Ω
VCCE–2V
CLKOUT∗
CLKOUT
CLKIN
Pulse
pattern
generator
50Ω
VCCE–2V
DATAIN
106.25MHz
50Ω
50Ω
VCCE–2V
VCCE–2V
0.1µF
0.1µF
531.25MHz
SDIN∗
SDIN
Device under test
SDOUT∗
SDOUT
REFCLK
RX0-9
TX0-9
parallel data
10bit
531.25MHz
50Ω
VCCE–2V
CLKOUT
CLKIN
50Ω
VCCE–2V
106.25MHz
modulate
Random pattern
2 ^ 7-1 or 2 ^ 23-1
DATAOUT
DATAOUT
TRIG
Pulse
pattern
generator
Jitter analyzer
DATAOUT∗
(e) TX random jitter measurement circuit
(f) Error rate measurement circuit
(g) TX jitter transfer measurement circuit
Page 15
—15—
CXB1586AR
Example of Representative Characteristics
C1 = C2 = 0.01µF
SDIN input 1.0625Gbps (Transition Density : 100%)
REFCLK input 106.25MHz
Example of TX Rj measurement (SDOUT)
Rj = 9.6psec
x : 30psec / div
y : 100mV / div
TX Eye Pattern (SDOUT 1.0625GHz operation)
C1 = C2 = 0.01µF
SDIN input 1.0625Gbps Random pattern
REFCLK input 106.25MHz
x : 200psec / div
y : 200mV / div
VOH_E
VOL_E
Page 16
—16—
CXB1586AR
Input Template (Tx jitter transfer)
Modulation amplitude (UIp-p)
REFCLK modulation frequency (Hz)
10
1
10
0
10
–1
10
–2
10 100 1k 10k 100k 1M 10M 100M
Tx Jitter Transfer
Jitter Transfer (dB)
REFCLK modulation frequency (Hz)
5.0
0.0
–5.0
–10.0
10 100 1k 10k 100k 1M 10M 100M
–15.0
–20.0
SDIN
SDOUT
REFCLK
input
output
input
C1=C2=0.01µF
Ta=27°C
(transition density : 100%)1.0625Gbps
531.25MHz
106.25MHz
Page 17
—17—
CXB1586AR
Error rate
Error rate
SDIN-Vin (mV)
10
–3
6.0 7.0 8.0 9.0 10.0 11.0
C1=C2=0.01µF
Ta=27°C
10
–4
10
–5
10
–6
10
–7
10
–8
10
–9
10
–10
10
–11
input
output
input
SDIN
SDOUT
REFCLK
1.0625Gbps
1.0625MHz
106.25MHz
2^7-1 2^23-1
Random pattern 2^7-1
Random pattern 2^23-1
Page 18
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
12.0 ± 0.2
∗ 10.0 ± 0.1
(0.22)
0.18 – 0.03
+ 0.08
1
16
17
32
33
48
49
64
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
64PIN LQFP (PLASTIC)
LQFP-64P-L01
LQFP064-P-1010
0.3g
DETAIL A
0.5 ± 0.2
(11.0)
0.127 – 0.02
+ 0.05
A
1.5 – 0.1
+ 0.2
0.1
SOLDER/PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
0.13
M
0.5
Package Outline Unit : mm
CXB1586AR
—18—
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