Page 1
CXD1172AM/AP
6-bit 20MSPS Video A/D Converter (CMOS)
Description
CXD1172AM/AP is a 6-bit CMOS A/D converter for
video use. The adoption of a 2-step parallel system
achieves low consumption at a maximum conversion
speed of 20MSPS minimum, 35MSPS typical.
Features
• Resolution: 6-bit ± 1/2LSB
• Max. sampling frequency: 20MSPS
• Low power consumption: 40mW (at 20MSPS typ.)
(Reference current excluded)
• Built-in sampling and hold circuit.
• 3-state TTL compatible output.
• Power supply: 5V single
• Low input capacitance: 4pF
• Reference impedance: 250Ω (typ.)
Applications
TV, VCR digital systems and a wide range of fields
where high speed A/D conversion is required.
Structure
Silicon gate CMOS monolithic IC
CXD1172AM
16 pin SOP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD 7V
• Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5 V
• Input voltage VIN VDD + 0.5 to VSS – 0.5 V
(Analog)
• Input voltage VCLK VDD + 0.5 to VSS – 0.5 V
(Digital)
• Output voltage VOH, VOL VDD + 0.5 to VSS – 0.5 V
(Digital)
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25 V
DVDD, DVSS 4.75 to 5.25 V
• Reference input voltage
VRB 0 to 4.1 V
VRT 0.9 to 5.0 V
VRT – VRB 0.9 to AVDD V
• Analog input voltage
VIN VRB to VRT V
• Clock pulse width
TPW1, TPW0 23ns (min.) to 1.1µs (max.)
• Operating temperature
Topr –20 to +75 °C
CXD1172AP
16 pin DIP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E89320C78-PS
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Block Diagram and Pin Configuration
1
D
0
2
CLK
DVSS
D1
3
D2
4
3
D
5
D4
6
D5
7
8
Lower data
latchs
Upper data
latchs
Clook generator
Lower encoder
(3BIT)
Lower encoder
(3BIT)
Upper encoder
(3BIT)
Lower
Sampling comparators
(3BIT)
Lower
Sampling comparators
(3BIT)
Upper
Sampling comparators
(3BIT)
Reference voltage
CXD1172AM/AP
16
AV
SS
15
DVDD
14
AVDD
13
VRB
12
IN
V
11
VRT
10
AVDD
9
DVDD
Pln Description and Equivalent Circuits
No. Symbol Equivalent Circuit
Di
1 to 6
7
8
9, 15
10, 14
11
13
D0 to D5
CLK
DVSS
DVDD
AVDD
VRT
VRB
11
DVDD
7
DV
SS
AV
DD
AVSS
AVDD
Description
D0 (LSB) to D5 (MSB) output
Clock input
Digital GND
Digital +5V
Analog +5V
Reference voltage (Top)
13
Reference voltage (Bottom)
12
16
VIN
AVSS
12
Analog input
AVSS
Analog GND
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Page 3
CXD1172AM/AP
Digital Output
Compatibility between Analog input voltage and the digital output code is indicated in the chart below.
Input signal
voltage
VRT
..............
VRB
Clock
Analog input
Data output
Step
0
......
31
32
63
TPW1 TPW0
N
N – 3 N – 2 N – 1 N N + 1
Digital output code
MSB LSB
1 1 1 1 1 1
......
1 0 0 0 0 0
0 1 1 1 1 1
0 0 0 0 0 0
N + 1
Td = 18ns
N + 2 N + 3
: Point for analog signal sampling.
N + 4
Timing Chart 1
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Page 4
CXD1172AM/AP
Electrical Characteristics (VDD = 5V, VRB = 1.0V, VRT = 2.0V, Ta = 25°C)
Item Symbol Conditions Min. Typ. Max. Unit
VDD = 4.75 to 5.25V
Conversion speed
Fc
Ta = –20 to +75°C
VIN = 1.0 to 2.0V
0.5
20
MSPS
fIN = 1kHz ramp
Supply current
Reference pin current
Analog input band width
(–1dB)
Analog input capacitance
Reference resistance
(VRT to VRB)
Offset voltage
∗1
Digital input voltage
Digital input current
Digital output current
Output data delay
IDD
IREF
BW
CIN
RREF
EOT
EOB
VIH
VIL
IIH
IIL
IOH
IOL
TDL
Fc = 20MSPS
NTSC ramp wave input
Envelope
VIN = 1.5V + 0.07Vrms
Potential difference to VRT
Potential difference to VRB
VDD = 4.75 to 5.25V
Ta = –20 to +75°C
VIH = VDD
VDD = max.
VIL = 0V
VOH = VDD + 0.5V
VDD = min.
VOL = 0.4V
With TTL 1 gate and 10pF load
Ta = –20 to +75°C
VDD = 4.75 to 5.25V
3
175
0
15
4.0
–1.1
3.7
7
4
18
4
250
–20
35
18
12
5.7
325
–40
55
1.0
5
5
30
mA
MHz
pF
Ω
mV
V
µA
mA
ns
Integral non-linearity error
EL
±0.3
±0.5
End point
Differential non-linearity
error
Differential gain error
Differential phase error
Aperture jitter
Sampling delay
∗1
The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
ED
DG
DP
Taj
Tsd
NTSC 40 IRE mod ramp
Fc = 14.3MSPS
±0.3
1.0
1.0
40
4
±0.5
drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001".
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2 LSB of the voltage when the output data changes from "11111111" to "11111110".
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LSB
%
deg
ps
ns
Page 5
Electrical Characteristics Test Circuit
Integral non-linearity error
Differential non-linearity
Offset voltage
DVM
V
IN
CXD1172A
CLK (20MHz)
6 6
“0” “1”
+V
–V
A < B A > B
COMPARATOR
A6
to
A1
A0
CONTROLLER
Test Circuit
}
S
2
S
S2 : ON IF B > A
S1
1 : ON IF A < B
B6
to
B1
B0
BUFFER
000 … 00
6
CXD1172AM/AP
to
111 … 0
Maximum operational speed
Differential gain error
1
2
SYNC
}
AMP
Differential phase error
FC – 1kHz
S. G.
100
IAE
–40
0
FC
40 IRE
MODULATION
NTSC
SIGNAL
SOURCE
S. G.
(CW)
BURST
Digital output current test circuit
Test Circuit
2.0V
1.0V
V
IN
2.0V
1.0V
CXD
1172A
TTL
ECL
TTL
ECL
66
620
–5.2V
CX20202A-1
10bit
D/A
CLK
–5.2V
620
1
2
H. P. F
VECTOR
SCOPE
D. G
D. P
ERROR RATE
COUNTER
2.0V
1.0V
VRT
VIN
VRB
CLK
VCC
GND
VOL
IOL
2.0V
1.0V
+
–
VRT
VIN
VRB
CLK
VCC
GND
VOH
IOH
+
–
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Page 6
Timing Chart 2
Analog input
External clock
Vi (1)
CXD1172AM/AP
Vi (2) Vi (3) Vi (4)
Upper comparators block
Upper data
Lower reference voltage
Lower comparators A block
Lower data A
Lower comparators B block
Lower data B
S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4)
MD (0)
RV (0)
S (1) C (1)H (1) C (3)H (3)S (3)
LD (–1) LD (1)
H (0)
LD (–2) LD (0)
C (0)
MD (1) MD (2)
RV (1) RV (2) RV (3)
C (2)H (2)S (2) H (4)S (4)
MD (3)
LD (2)
Digital output
Out (–2) Out (–1) Out (0) Out (1)
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Page 7
CXD1172AM/AP
Operation (See Block Diagram and Timing Chart)
1. CXD1172AM/AP is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2
Iower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRTVRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper
data is fed through the reference supply to the lower data.
2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features
the following operating modes which are respectively indicated on the timing chart with S, H, C symbols.
That is input sampling (auto zero) mode, input hold mode and comparison mode.
3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with
the falling edge of the first clock by means of the upper comparator block and the Iower comparator A block.
The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the
upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the
second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes
1. VDD, Vss
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the
respective GND's.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be
prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and
with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.
6. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply.
This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
See "For latch up prevention" of CXD1172P/CXA1106P PCB description. (Page 6, 7)
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Page 8
CXD1172AM/AP
Latch Up Prevention
The CXD1172A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pins 10 and 14) and DVDD (Pins 9 and 15), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
DD
DV
AV
DD
9
15
C14
DIGITAL IC
8
+5V
AV
+5V
SS
10
14
AVDD DVDD
C6
AVSS DVSS
16
CXD1172A
DVSS
b. When analog and digital supplies are from a common source
(i)
DD
DV
9
15
C14
8
+5V
AV
SS
C6
10
14
AVDD DVDD
CXD1172A
AV
SS DVSS
16
DVSS
(ii)
DV
DD
9
15
C14
+5V
C6
10
14
AVDD DVDD
CXD1172A
DIGITAL IC
DIGITAL IC
AV
SS
AVSS DVSS
16
8
DVSS
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Page 9
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
DVDD
AV
DD
9
15
8
+5V
+5V
AV
SS
C6
10
14
AVDD DVDD
CXD1172A
SS DVSS
AV
16
DVSS
b. When analog and digital supplies are from common source
(i)
CXD1172AM/AP
DIGITAL IC
(ii)
+5V
AV
AVDD
+5V
C6
SS
DVDD
AVDD
10
14
AVDD DVDD
CXD1172A
AVSS DVSS
16
DVDD
10
14
AVDD DVDD
CXD1172A
DVSS
9
9
15
DIGITAL IC
8
15
DIGITAL IC
AV
SS
AVSS DVSS
16
8
DVSS
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Page 10
6-bit, 20MSPS ADC and DAC Evaluation Board
Silk Side
Analog
VR3
C2
Q4 Q5
S IN
C1
VR1
R1
R4
R5
VR2
R2
C3
Q1
R3
Q2
Analog
VR5
C9
C10
DA OUT
R10
VR4
R9
C5
AGND
C7
R7
C6
Q3
C4
R8
R6
A.GND
C11 C12
–5V
Component Side
CXD1172AM/AP
C8
A1106P
D1172P
C14
C13
DVDD
AVDD
GND
+5V
CLK
Logic
74S174
74S174
74HC04
D7D6
D5D4D3D2D1D0
SW
D.GND
OSC
R11
CLK IN
D6 D4 D2
D7 D5 D3 D1 D0
CLK
Soldering Side
1
2
3
– 10 –
Page 11
Package Outline Unit: mm
CXD1172AM
CXD1172AM/AP
16PIN SOP (PLASTIC) 300mil
CXD1172AP
+ 0.4
9.9 – 0.1
16
18
0.45 ± 0.1
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-16P-L01
∗SOP016-P-0300-A
9
+ 0.3
5.3 – 0.1
7.9 ± 0.4
1.27
M
± 0.12
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
6.9
+ 0.1
0.2 – 0.05
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.2g
+ 0.4
1.85 – 0.15
0.15
+ 0.2
0.1 – 0.05
0.5 ± 0.2
16PIN DIP (PLASTIC)
+ 0.4
19.2 – 0.1
16
18
0.5 ± 0.1
1.2 ± 0.15
SONY CODE
EIAJ CODE
JEDEC CODE
2.54
9
0.5 MIN
3.0 MIN
DIP-16P-01
DIP016-P-0300
Similar to MO-001-AE
+ 0.4
3.7 – 0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
+ 0.3
6.4 – 0.1
7.62
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
1.0 g
+ 0.1
0.25 – 0.05
0° to 15°
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