Datasheet CXA3516R Datasheet (Sony)

3-channel 8-bit 165MSPS A/D Converter Amplifier PLL

Description

The CXA3516R is a 3-channel 8-bit 165MSPS A/D converter with built-in amplifier and PLL developed for LCD projectors and LCD monitors.

The CXA3516R inputs RGB graphics signals from personal computers or others. After the input levels are controlled, the A/D conversion is performed with a clock generated by PLL.

The digital output levels are compatible with TTL.

This IC operates at a maximum conversion rate of 165MHz, and can support up to UXGA. Control register supports both I2C and 3-wire bus.

Features

• Supply voltage: 5V, 3.3V

• Power consumption: 1.8W typ. (165MSPS)

• 144-pin LQFP

• 3-ch AMP and PLL eliminate design time for mutual

connections.

Structure

Bipolar silicon monolithic IC

Applications

• LCD monitors

• LCD projectors

• Digital TVs

• PDPs

Functions and Performance

• Power save function

• Supports both I2C and 3-wire bus Amplifier block

• Clamp

• Main contrast: 8-bit

• Sub contrast: 8-bit × 3

• Main brightness: 8-bit × 3

• CbCr offset: 6-bit × 2

• Supports YCbCr input

• Two input systems

• AMP monitor output/SW monitor output

• SYNCSEP function A/D converter block

• Maximum conversion rate: 165MSPS

• Supports UXGA input

• Supports demultiplexed output

• Supports both in-phase and alternate phase during

demultiplexing

• Supports YUV4:2:2 output

• Output high impedance mode

• Built-in reference voltage PLL block

• Sync input frequency: 10kHz to 130kHz

• Clock delay: 1/32 to 64/32CLK

• VCO counter: 12-bit

• Low clock jitter

• CLK inversion

• CLK and 1/2CLK outputs

• Phase comparison hold

• Output high impedance mode

– 1 –

E99Y28A07-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA3516R

144 pin LQFP (Plastic)

For the availability of this product, please contact the sales office.

– 2 –

CXA3516R

Absolute Maximum Ratings (Ta = 25°C)

Item

DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, AVCCVCO, DVCCPLL, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB

AVCCAD3, DVCCAD3 ADDRESS, XPOWERSAVE, XSENABLE, 3WIRE/I2C,

HOLD, XTLOAD, EVEN/ODD, XCLKIN, CLKIN, SYNCIN1, SYNCIN2, CLPIN, RC1, RC2, R/CrIN1, R/CrIN2, R/CrCLP, G/YCLP, B/CbCLP, SOGIN1, G/YIN1, SOGIN2, G/YIN2, B/CbIN1, B/CbIN2, RCrOUT, G/YOUT, B/CbOUT, DACTESTOUT

SDA, SCL Tstg

PD

Supply voltage

Input voltage

Storage

temperature

Allowable power

dissipation

5.5

GND – 0.5 to 5V VCC + 0.5

or 5.5

GND – 0.5 to 5.5

–65 to +150

5

V

°C

W

Maximum ratings Unit

Recommended Operating Conditions

Item

DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, DVCCPLL, AVCCVCO, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB

AVCCAD3, DVCCAD3 XPOWERSAVE, HOLD, XTLOAD,

EVEN/ODD, SYNCIN1, SYNCIN2, CLPIN

CLKIN, XCLKIN

Straight mode DMUX mode YUV4:2:2 D2 mode YUV4:2:2 special mode

Ta

Supply voltage

TTL input pin

PECL input pin

Maximum conversion rate

Operating ambient temperature

4.75

3 2

—

DVCCPLL

–0.8

—

100 165 100 100

–10

5

3.3 — —

—

— —

— — —

—

5.25

3.6 —

0.8 —

DV

CCPLL

–1.6

— — — —

+75

V

V V V

V

MSPS MSPS MSPS MSPS

°C

Max.Typ.Min. Unit

High level Low level

High level

Low level

– 3 –

CXA3516R

Pin Configuration (Top View)

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

7374757677

78

79

80

81

828384

85

8687

88

89

90

91

92

93

949596979899

100101102103104105106107108

133 134 135 136 137 138 139 140 141

1 2 3 4

121 122 123 124 125 126 127 128 129 130 131 132

142 143 144

110

109

111 112 113 114 115 116 117 118 119 120

5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 3611 21 31

B/CbOUT

ADDRESS

R/CrOUT

NC

XPOWER SAVE

DGNDREG

DVCCREG

SDA

SCL

XSENABLE

SEROUT

3WIRE/I

2

C

DPGND

AVCCADREF

AVCCAD3

VRT

DVCCAD3

DVCCADTTL

DGNDADTTL

RA0

RA1

DGNDAD3

RA2

RA3

RA4

RA5

RA6

AGNDAD3

DGNDAD3

RA7

DVCCADTTL

DGNDADTTL

RB0

RB1

RB2

GA4 GA3 GA2 GA1 GA0 DGNDADTTL DGNDAD3 DV

CCADTTL

BB7 BB6 BB5 BB4 BB3 GNDAD3 BB2 BB1 BB0 DGNDADTTL DVCCADTTL BA7 BA6 BA5 DGNDAD3 BA4 BA3 BA2 BA1 BA0 DGNDADTTL DGNDAD3 DV

CCADTTL

RB7 RB6 RB5 RB4 RB3

EVEN/ODD

XTLOAD

HOLD

SOGOUT

UNLOCK

DSYNC/DIVOUT

DPGND

1/2CLK

1/2XCLK

CLK

XCLK

DGNDPLLTTL

DVCCPLLTTL

AGNDADREF

AVCCAD3

VRB

DVCCAD3

DVCCAD

DVCCADTTL

DGNDADTTL

GB7

GB6

DGNDAD3

GB5

GB4

GB3

GB2

GB1

AGNDAD3

DGNDAD3

GB0

DGNDADTTL

DVCCADTTL

GA7

GA6

GA5

XCLKIN

CLKIN SYNCIN1 SYNCIN2

CLPIN DV

CCPLL

DGNDPLL

AV

CCVCO

AGNDVCO

RC1 RC2

AVCCIR

IREF

DPGND

AGNDIR

G/YIN1

AV

CCAMPG

G/YIN2

AGNDAMPG

G/YCLP

B/CbCLP

R/CrCLP

DPGND SOGIN1 B/CbIN1

AV

CCAMPB

SOGIN2 B/CbIN2

AGNDAMPB

DPGND

R/CrIN1

AV

CCAMPR

R/CrIN2

AGNDAMPR

G/YOUT

DACTESTOUT

– 4 –

CXA3516R

AMP R

SW

R

AMP G

AMP B

ADC R

ADC G

ADC B

SW

G

SW

B

SYNCSEP

SW

PLL

PD

PLL

CP (3)

FINE

DELAY

(6)

Width

(2)

COARSE

DELAY (2)

VCO

DIV

1, 2, 4, 8

REGISTER

ADDRESS

SOGOUT

XPOWER SAVE

SDA

SCL

XSENABLE

SEROUT

3WIRE/I

2

C

HOLD

XTLOAD

RC1

RC2

COUNTER (12)

1/2DIV

UNLOCK

Sub Contrast (8)

Sub Brightness (8)

R/CrIN1

CLPIN

R/CrOUT

R/CrIN2

R/CrCLP

G/YCLP

G/YIN1

G/YIN2

B/CbCLP

SYNCIN1

SYNCIN2

B/CbIN1

B/CbIN2

SOGIN1

SOGIN2

SYNCTIP

CLP

Cr Offset (6)

Sub Contrast (8)

Sub Brightness (8)

Sub Contrast (8)

Main Contrast (8)

V

TH (4) VHYS (2)

Sub Brightness (8)

Cb Offset (6)

SW

G/YOUT

SW

B/CbOUT

VRT

VRT VRB

VRB

DATA MODE

RB7 to RB0

RA7 to RA0

GB7 to GB0

GA7 to GA0

BB7 to BB0

BA7 to BA0

XCLK

1/2CLK

EVEN/ODD

1/2XCLK

DSYNC/DIVOUT

CLK

SW

SOGT

SW

SOGO

SW

SOGP

SW

SYNCIN

TOP Block Diagram

– 5 –

CXA3516R

Amplifier Block Diagram

CLP

DRV

GCA

CLP

POL

1bit

R/CrOUTR/CrCLPCLPIN

Rch

R/CrIN1

R/CrIN2

Sub

Contrast

8bit

Sub Brightness

8bit

CLPOFF

SW

VRT

VRB

ADC R

SW

R

Sub Brightness

8bit

Cr Offset

6bit

CLP

DRV

GCA

CLP

G/YOUTG/YCLP

Gch

RGB/YUV 1bit

G/YIN1

G/YIN2

Sub

Contrast

8bit

SW

VRT

VRB

ADC G

SW

G

Sub Brightness

8bit

Cb Offset

6bit

CLP

DRV

GCA

CLP

Main Contrast 8bit

SYNC ON GREEN SEPARATOR

B/CbOUTB/CbCLP

Bch

B/CbIN1

B/CbIN2

SOGIN1

SOGIN2

V

TH 4bit VHYS 2bit

Sub

Contrast

8bit

SW

VRT

VRB

ADC B

SYNC ON GREEN

SYNCT1

SYNC ON GREEN

SYNCT2

SYNC ON GREEN

SYNCP

SW

B

SW

SOGP

SYNC TIP CLP

SYNC SEP

AMP POWER SAVE

1bit

SYNC SEP POWER SAVE

1bit

DACTEST DACTEST OUT

– 6 –

CXA3516R

PECLIN

RC2

PLL

1bit

PD POL

RC1

Reset Pulse

Generator

TTLIN

SW

M

Polarity TTLOUT

TTLOUT

DSYNC

HOLD

SW

M

M/S

1/2

SW

DIV

1, 2, 4, 8

VCO + 1/4

Fine

Delay

Charge

Pump

Phase

Detector

Programmable

Counter

TTLOUT

TTLIN

TTLIN Polarity

HOLD POL

1bit

SOG Enable

1bit

SOG OUT POLSYNC OUT SW

1bit

RGBIN1/2SEL

1bit

IREF Clamp

Pulse

XTLOAD

(TTL)

SYNCP/HSYNC

1bit

SYNC POL

3bit

12bit

VCO DIV

HSYNC1/2

1bit

CLP POL

1bit

TTLIN

DAC

Polarity

TTLIN

PLL

Power Save

Polarity

SW

6bit

1/256 to 1/4096

2bit

1bit

DSYNC By-pass

1bit

VCO

By-pass

2bit

RESET

1bit

DSYNC

HOLD

CLK Enable

DIV

1, 2, 4, 8

1bit

XCLK Enable

1bit

1/2CLK Enable

1bit

1/2XCLK Enable

UNLOCK Enable

TTLOUT

1bit

DSYNC Enable

EVEN/ODD

(TTL)

DSYNC/DIVOUT

(TTL)

CLKIN

(PECL)

XCLKIN

(PECL)

SOGOUT

(TTL)

SYNCIN1

(TTL)

SYNCIN2

(TTL)

HOLD

(TTL)

CLPIN

(TTL)

SYNC ON GREEN

SYNCT1

SYNC ON GREEN

SYNCT2

SYNC ON GREEN

SYNCP

CLK

(TTL)

XCLK

(TTL)

1/2CLK

(TTL)

1/2XCLK

(TTL)

UNLOCK

1/2CLK (ADC)

CLK (ADC)

DSYNC POL

UNLOCK

Detect

J

K

Q

M/S

SW

Coarse Delay

Coarse

Delay

DIVOUT

Pulse Width

2bit

DIVOUT WIDTH

1bit

DIVOUT Delay

DIVOUT

Delay

PLL Block Diagram

– 7 –

CXA3516R

R/CrIN1

R1

G1

B1

H1

G/YIN1

B/CbIN1

SOGIN1

SYNCIN1

R/CrIN2

R2

G2

B2

H2

G/YIN2

B/CbIN2

SOGIN2

SYNCIN2

SYNC TIP

CLAMP

SYNC

SEP

SW

SOGT

AMP

BLOCK

SYNCT1

SYNCT2

SYNCT

PLL

BLOCK

SW

SOGO

POL

TTL

OUT

SOGOUT

PLL

SYNC OUT SW

1bit

SOG OUT POL

1bit

PEDESTAL

CLAMP

PEDESTAL

CLAMP

SYNC TIP

CLAMP

SYNC

SEP

SW

PLL

SW

SYNCIN

POL

1bit

SYNCP/HSYNC

1bit

HSYNC1/2

4bit

V

TH

2bit

V

HYS

1bit

RGB IN 1/2 Select

1bit

SYNC POL

1bit

SOG Enable

SW

SOGP

SYNC

SEP

SYNCP2

SYNCP1

SYNC Block Diagram

– 8 –

CXA3516R

ADC Block Diagram

8

RA7 to RA08RB7 to RB08GA7 to GA08GB7 to GB08BA7 to BA0

8

DATA FORMAT

3bit

DATA INV

1bit

BB7 to BB0

CLK

1/2CLK

AMP R

AMP G

AMP B

VRB

ADC R

ADC G MODE

ADC B

CLK CONT

VRB

VRT

ADC Power Save

1bit

VRT

– 9 –

CXA3516R

Pin Description

Pin No. Symbol I/O Typical signal Description

1 2 3 4 5 6 7 8

9 10 11 12 13 15

16, 94

17

18, 92

19, 32, 42, 54,

65, 76, 90

20, 33, 44, 55,

67, 77, 89

21, 22,

24 to 28, 31

23, 30, 43, 50,

59, 66, 79, 86

29, 80

34 to 41

45 to 49,

51 to 53

56 to 58,

60 to 64 68 to 75

78, 81 to 85,

87, 88

91 93 95

B/CbOUT ADDRESS R/CrOUT NC NC XPOWER SAVE DGNDREG DVCCREG SDA SCL XSENABLE SEROUT 3WIRE/I2C AVCCADREF AVCCAD3 VRT DVCCAD3

DVCCADTTL

DGNDADTTL

RA0 to RA7

DGNDAD3 AGNDAD3

RB0 to RB7 BA0 to BA7

BB0 to BB7 GA0 to GA7 GB0 to GB7 DVCCAD

VRB AGNDADREF

O

I

O

— —

I

— —

I I I

O

I

— —

O

— —

—

O

— —

O O

O O O

—

O

—

1.83V

—

1.83V

— —

TTL

GND

5V

— —

TTL TTL

—

5V

3.3V

2.9V

3.3V 5V

GND

TTL

GND GND

TTL TTL

TTL TTL TTL

5V

1.9V

GND

Amplifier output signal monitor I2C slave address setting Amplifier output signal monitor Not used Not used Power save setting Register GND Register power supply Control register data input Control register CLK input Enable signal input for 3-wire control register 3-wire control register data readout Selection of input between I2C bus and 3-wire bus Reference power supply for A/D converter Analog power supply for A/D converter Top reference voltage output for A/D converter Digital power supply for A/D converter

TTL output power supply for A/D converter

TTL output GND for A/D converter

Data output for R-channel port A side

Digital GND for A/D converter Analog GND for A/D converter

Data output for R-channel port B side Data output for B-channel port A side

Data output for B-channel port B side Data output for G-channel port A side Data output for G-channel port B side Digital power supply for A/D converter

Bottom reference voltage output for A/D converter Reference voltage GND for A/D converter

– 10 –

CXA3516R

96 97 98

99 100 101

103 104

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 124 125 126 127 128 129 130 132 133

DVCCPLLTTL DGNDPLLTTL XCLK CLK 1/2XCLK 1/2CLK DSYNC/

DIVOUT UNLOCK SOGOUT HOLD XTLOAD EVEN/ODD XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVCCPLL DGNDPLL AVCCVCO AGNDVCO RC1 RC2 AVCCIR IREF AGNDIR G/YIN1 AVCCAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP SOGIN1 B/CbIN1

— —

O O O O

O O

O

I I I I I I I I

— — — — — — —

I

—

I

—

I

— — — —

I I

5V

GND

TTL TTL TTL TTL

TTL

Open collector

TTL TTL TTL

TTL PECL PECL

TTL

5V

GND

5V

GND

2.1V

2 to 4.5V

5V

1.2V

GND

—

5V

—

GND

— — —

2.8V

—

TTL output power supply for PLL TTL output GND for PLL Inverted CLK output CLK output Inverted 1/2CLK output 1/2CLK output

DSYNC or DIVOUT signal output Unlock signal output

Output for SYNC ON GREEN Input for phase comparison disable signal Programmable counter reset setting Inverted pulse input of ADC sampling CLK Inverted CLK input for testing CLK input for testing Sync input 1 Sync input 2 Clamp pulse input Digital power supply for PLL Digital GND for PLL Analog power supply for PLL VCO Analog GND for PLL VCO External pin for PLL loop filter External pin for PLL loop filter Analog power supply for IREF Current setup Analog GND for IREF G/Y signal input 1 Power supply for G/Y amplifier block G/Y signal input 2 GND for G/Y amplifier block Clamp capacitor for brightness Clamp capacitor for brightness Clamp capacitor for brightness SYNC ON GREEN signal input 1 B/Cb signal input 1

Pin No. Symbol I/O Typical signal Description

– 11 –

CXA3516R

134 135 136 137 139 140 141 142 143

144

14, 102, 122,

131, 138

AVCCAMPB SOGIN2 B/CbIN2 AGNDAMPB R/CrIN1 AVCCAMPR R/CrIN2 AGNDAMPR G/YOUT DAC TEST

OUT DPGND

—

I I

—

I

—

I

—

O O

—

5V

2.8V

—

GND

—

5V

—

GND

1.83V 5V

GND

Power supply for B/Cb amplifier block SYNC ON GREEN signal input 2 B/Cb signal input 2 GND for B/Cb amplifier block R/Cr signal input 1 Power supply for R/Cr amplifier block R/Cr signal input 2 GND for R/Cr amplifier block Monitor pin for amplifier output signal

DAC testing output for amplifier block control register

GND

Pin No. Symbol I/O Typical signal Description

– 12 –

CXA3516R

Pin Description and Pin Equivalent Circuit

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

Power supply for amplifier block.

GND for amplifier block.

Sync separated SYNC signal output. Separates and outputs the SYNC signal from SYNC ON GREEN input signal. (SYNC signal input from SYNCIN1 and SYNCIN2 pins can be output.) Both positive and negative polarity outputs are supported. The polarity is selected by the control register.

SYNC ON GREEN signal inputs. Input via a 0.1µF capacitor. When not used, connect to AV

CC.

The SYNC TIP clamp level is approximately 2.0V + Vf (0.8V) = approximately 2.8V. At this time, if the pin voltage is lowered, these pins go to low impedance and current flows from the IC. When these pins are at the SYNC TIP level or higher, the clamp circuit is off and only an input base current of approximately 1.2µA flows.

Amplifier output signal monitor. Each monitor can output either the entered signal immediately before A/D converter or the signal after switching between 2 types of input signals. The 2 types of input signals can be selected by the control register and output. These pins are emitter follower outputs, but the internal bias current is so small that a 820Ω resistor should be connected between these pins and GND to monitor high frequency signals. When not used, connect to AV

CCAMP.

3

R/CrOUT O

1.83V

143 G/YOUT O

1.83V

1

B/CbOUT

O

1.83V

105

SOGOUT

O

TTL

132

SOGIN1

I

2.8V

135

SOGIN2

I

2.8V

140 125 134 142 127 137

AVCCAMPR AVCCAMPG AVCCAMPB AGNDAMPR AGNDAMPG AGNDAMPB

— — — — — —

5V 5V

5V GND GND GND

100

AV

CCAMP

AGNDAMP

280µ

1

3

143

DGNDPLL

100k

DV

CCPLL

DVCCPLLTTL

DGNDPLLTTL

105

150

AV

CCAMPG

AGNDAMPG 100µ

132 135

– 13 –

CXA3516R

Amplifier block

Analog input signal. Input via a 0.1µF ceramic capacitor. The typical signal level is 0.7V. Signals from 0.5V (min.) to

1.0V (max.) can be supported. IN1 and IN2 are selected by the control register. Leave these pins open when not used. RGB input and YCbCr input can be selected by the control register.

∗1

The clamp level typical values are as follows. In case RGB is input

2.2V + Vf (0.8V) = approximately 3V

In case YCbCr is input

G/YIN:

2.2V + Vf (0.8V) = approximately 3V

R/CrIN, B/CbIN:

2.7V + Vf (0.8V) = approximately 3.5V

Clamp period: A clamp current of ±1.2mA (max.) flows. Signal period: A base current of

0.5µA flows to the IC.

139

R/CrIN1

I

∗1

141

R/CrIN2

I

∗

1

124

G/YIN1

I

∗1

126

G/YIN2

I

∗1

133

B/CbIN1

I

∗1

136

B/CbIN2

I

∗1

130

R/CrCLP

—

∗2

128

G/YCLP

—

∗2

129

B/CbCLP

—

∗2

Clamp capacitor connector for brightness. Connect 0.1µF ceramic capacitors between these pins and GND.

∗

2

Typical levels of the clamp are as follows. In case RGB is input

SUB BRIGHTNESS

00H: 2.68V 80H: 2.81V FFH: 2.94V

In case YCbCr is input

G/YCLP is the same as above. R/Cr, B/CbCLP are as follows.

CbCr Offset

00H: 3.04V 20H: 3.07V 3FH: 3.102V

Clamp period: A clamp current of ±1.2mA (max.) flows. Signal period: A base current of

0.5µA flows to the IC.

AVCCAMP

AGNDAMP 400µ 100µ

500

100

25k

250

100

124

126 133 136

139 141

AVCCAMP

AGNDAMP

100µ

100k250

500

300

100

128 129

130

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 14 –

CXA3516R

CLK output. Output the same frequency CLK as that of ADC sampling. These are complemental TTL levels. These pins can be independently controlled on and off (power save) by the control register.

1/2CLK output. Output a half frequency CLK of that of ADC sampling. These are complemental TTL levels. These pins can be independently controlled on and off (power save) by the control register.

Data output for R-channel port A side.

Data output for R-channel port B side.

Data output for G-channel port A side.

Data output for G-channel port B side.

Data output for B-channel port A side.

Data output for B-channel port B side.

21, 22,

24 to 28,

31

34 to 41

68 to 75

78,

81 to 85,

87, 88

45 to 49,

51 to 53

56 to 58,

60 to 64

RA0 to RA7

RB0 to RB7

GA0 to GA7

GB0 to GB7

BA0 to BA7

BB0 to BB7

O

TTL

15

95 16, 94 29, 80 18, 92

91

AVCCADREF AGNDADREF AVCCAD3 AGNDAD3 DVCCAD3 DVCCAD

— — — — — —

5V

GND

3.3V

GND

3.3V 5V

Reference power supply for A/D converter. Reference GND for A/D converter. Analog power supply for A/D converter. Analog GND for A/D converter. Digital power supply for A/D converter. Digital power supply for A/D converter.

Clamp pulse input for the signal of analog input clamp and brightness clamp. Both positive and negative polarity inputs are supported. The polarity is selected by the control register. The input pulse width should be 200ns or more.

1.5V

192

1.5k

DV

CCPLL

DGNDPLL

113

A/D converter block

113

CLPIN

I

99

O

TTL

CLK

TTL

98

O

XCLK

TTL

101

O

1/2CLK

TTL

100

O

1/2XCLK

TTL

DGNDPLL

100k

DV

CCPLLTTL

DGNDPLLTTL

98

99

100101

100k

DV

CCADTTL

DGNDADTTL

DGNDAD3

Pin No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 15 –

CXA3516R

Top reference voltage output for A/D converter input dynamic range. Connect to AVCCAD3 via a 1µF ceramic capacitor.

Bottom reference voltage output for A/D converter input dynamic range. Connect to AVCCAD3 via a 1µF ceramic capacitor.

Digital GND for A/D converter.

TTL output power supply for A/D converter.

TTL output GND for A/D converter.

DGNDAD3

DVCCADTTL

DGNDADTTL

—

GND

5V

GND

23, 30, 43, 50, 59, 66,

79, 86

19, 32, 42, 54, 65, 76,

90

20, 33, 44, 55, 67, 77,

89

VRT

O

2.9V

17

VRB

O

1.9V

93

AVCCADREF

AGNDADREF

2k

20µ

90

17

AVCCADREF

AGNDADREF

4k

20µ

80

93

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 16 –

CXA3516R

PLL block

Input SYNC signal at TTL level. The input polarity is switched by the control register. Leave this pin open when not used.

Input signal for phase comparison HOLD. Phase comparison is stopped, and VCO oscillation frequency is held. When not be hold, fix the pin as follows. When HOLDPOL register is "1", fix this pin to low level. When HOLDPOL register is "0", leave this pin open or fix to high level.

Input the signal used to invert the A/D converter sampling CLK.

Low: EVEN mode High: ODD mode

Normally fix it to low level. Programmable counter reset.

Normally fix it to high level or leave open. In programmable counter test mode, set it to low level to call up the register contents. When not used, leave this pin open or fix to high level.

1.5V

192

40k

DV

CCPLL

DGNDPLL

112

111

107

108

106

DGNDPLL

DVCCPLL

14k

500

14k

110 109

CLK input for ADC operation check. Input PECL level signal complementally. When using this pin, set CLK to external input by the control register. Leave this pin open when not used.

SYNCIN1

SYNCIN2

HOLD

EVEN/ODD

XTLOAD

I

TTL

111

112

106

108

107

110

109

CLKIN

XCLKIN

IIPECL

PECL

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 17 –

CXA3516R

This pin can output either DSYNC signal or DIVOUT signal. It can be selected by the control register. In addition, the output polarity can be selected by the control register.

External pin for PLL loop filter.

Connect an external resistor (3kΩ) to supply a stabilized current to the inside of the IC. (charge pump current, etc.) Connect this pin to GND via 0.1µF ceramic capacitor connected as close to the pin as possible. The band gap voltage is output.

DSYNC/ DIVOUT

O

TTL

103

DGNDPLL

100k

DV

CCPLL

DVCCPLLTTL

DGNDPLLTTL

103

UNLOCK signal output. Make a discrimination between lock and unlock in the analog manner by connecting the external circuit. Leave this pin open when not used. Do not connect this pin to neither power supply nor GND.

UNLOCK

—

104

RC1

—

2.1V

118

RC2

—

2 to

4.5V

119

IREF

I

1.2V

121

100k

DGNDPLL

DGNDPLLTTL

DV

CCPLLTTL

104

AVCCIR

AGNDIR DPGND

118

119

DPGND

AGNDIR

AV

CCIR

121

114 115

96

DVCCPLL DGNDPLL DVCCPLLTTL

Digital power supply for PLL. Digital GND for PLL. TTL output power supply for PLL.

— — —

5V

GND

5V

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 18 –

CXA3516R

Input control register data. Switching between the I2C and 3-wire bus mode is performed by the 3WIRE/I2C pin.

Control register block

9

I

SDA

—

9

DGNDREG

DVCCREG

200k

4k

Input control register CLK. Switching between the I2C and 3-wire bus mode is performed by the 3WIRE/I2C pin.

10

I

SCL

—

10

DGNDREG

DVCCREG

200k

4k

10k

Set slave address when using I2C bus mode.

Slave address: 1 0 0 1 1 S2 S1 0

Connect this pin to GND during 3-wire bus mode.

2

I

ADD

—

DGNDREG

DVCCREG

1k

15µ

2

97 120 123 116 117

DGNDPLLTTL AVCCIR AGNDIR AVCCVCO AGNDVCO

TTL output GND for PLL. Analog power supply for IREF. Analog GND for IREF. Analog power supply for PLL VCO. Analog GND for PLL VCO.

— — — — —

GND

5V

GND

5V

GND

VCC to 3/4VCC 3/4VCC to 2/4VCC 2/4VCC to 1/4VCC 1/4VCC to GND

0 1 1 0

1 1 0 0

S2 S1

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 19 –

CXA3516R

When using the read mode of 3-wire bus mode, the register information written once is output in series order from the LSB of the setting sub address data.

GND for register. Power supply for register.

7 8

——GND

5V

DGNDREG DV

CCREG

Inputs enable signal for 3-wire bus.

High level: Control disabled

Low level: Control enabled Connect this pin to GND when using I

2

C.

XSENABLE

I

TTL

11

DGNDREG

DVCCREG

200k

4k

Selection of input between I2C bus and 3-wire bus.

3WIRE/I2C

I

—

13

DGNDREG

DVCCREG

100k

15µ15µ

13

SEROUT

O

TTL

12

DGNDREG

DV

CCREG

100k

12

XPOWER SAVE

I

TTL

6

DGNDREG

DV

CCREG

10µ

1k

6

VCC to 2/3VCC 2/3VCC to 1/3VCC 1/3VCC

to GND

I

2

C 3V mode

I2C 5V mode

3-wire bus mode

Power save for all functions including the control register block.

High level: Normal operation

Low level: Power save

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 20 –

CXA3516R

14, 102,

122, 131,

138

4

5

DPGND

NC

—

GND

—

This pin is connected to the die pad. Connect to the specified GND in Application Circuit.

Not used. Leave this pin open or connect to GND.

DAC test output for control register of amplifier block. Current is output by open collector. Normally connect to AVCC.

DAC TEST OUT

O

5V

144

DGNDREG

DV

CCREG

144

No.

Symbol I/O

Typical

signal

Equivalent circuit Description

– 21 –

CXA3516R

Electrical Characteristics (Ta = 25°C, AVCC, DVCC = 5V, AVCC3, DVCC3 = 3.3V)

Supply Current

Current during operating

5V current consumption

3.3V current consumption

Register control power save current

5V power save current consumption

3.3V power save current consumption

XPOWER SAVE pin control power save current

5V power save current consumption

3.3V power save current consumption

CLK = DC CLK = DC

— —

—

180 180

26

3.0

9.0

3.0

240 226

42

7.2

22

7.2

mA mA

mA

I

CC5

ICC3

ICC5PS

ICC3PS

ICC5XPS

ICC3XPS

3-wire control bus (SDA, SCL, SENABLE)

High level input voltage Low level input voltage High level input current Low level input current Threshold voltage

High → Low Threshold voltage

Low → High Input capacitance SCL clock frequency XSENABLE setup time XSENABLE hold time XSENABLE

high level pulse width SDA setup time SDA hold time SDA delay time

in WRITE/READ mode in WRITE/READ mode in WRITE/READ mode

in WRITE/READ mode in WRITE/READ mode

in WRITE/READ mode in READ mode

2.0 0

–2.0 –5.0

—

— —

—

3 0

300

3 0

—

— — — —

1.3

1.65

— —

10 10

—

10 10 11

5.0

0.8 0 0

—

10 10

— —

V

V µA µA

V

V pF

MHz

ns ns

VIH VIL IIH IIL

VTHHL1

VTHLH1 CI

FSCL1 TENS TENH

TENPW TDS

TDH TD

Register

Item Symbol

Measurement conditions

Min. Typ. Max.

Unit

Item Symbol

Measurement conditions

Min. Typ. Max.

Unit

– 22 –

CXA3516R

I2C control bus (SDA, SCL)

High level input voltage Low level input voltage High level input current Low level input current Threshold voltage

High → Low Threshold voltage

Low → High High level input voltage Low level input voltage High level input current Low level input current Threshold voltage

High → Low Threshold voltage

Low → High SDA low level output voltage Input capacitance SCL clock frequency Bus free-time

STOP → START

Hold time (resend)

Hold time in SCL clock at Low state

Hold time in SCL clock at High state

Setup time under resend START condition

Data hold time Data setup time Rise time Fall time Setup time under STOP

condition Capacitive load of each

bus line

IOH = 3mA

START condition: After this period, first clock is generated.

2.3 0

–2.0 –5.0

—

2.0 0

–1.0 –5.0

—

0

—

0

4.7

4.0

4.7

4.0

4.7 0

250

— —

4.0

—

— — — —

1.6

1.95

— — — —

1.3

1.65

0.15

—

50

5.0

5000

— —

5.0

—

5.0

1.0 0 0

—

5.0

0.8 0 0

—

0.5

10

100

—

— —

—

1000

300

—

400

V

V µA µA

V

V µA µA

V

V pF

kHz

µs

µs µs

ns ns ns

µs

pF

VIH VIL IIH IIL

VTHHL2

VTHLH2 VIH

VIL IIH IIL

VTHHL3

VTHLH3 VOL

CI FSCL2

TBUF

THD;STA

TLOW

THIGH

TSU;STA THD;DAT

TSU;DAT TR TF

TSU;STO

Cb

Register (Cont.)

I

2

C (High) modeI

2

C (Low) mode

Item

Symbol

Measurement conditions

Min.

Typ.

Max.

Unit

– 23 –

CXA3516R

Brightness characteristics

Brightness level H (ADC OUT)

Brightness level L

Brightness level M

Brightness level H Brightness level

Low side variable range Brightness level

High side variable range

Clamp characteristics

Cb, Cr clamp level M (ADC OUT)

Cb, Cr clamp level L

Cb, Cr clamp level M

Cb, Cr clamp level H Cb, Cr clamp level

Low side variable range Cb, Cr clamp level

High side variable range Clamp pulse minimum width

Contrast characteristics

Main contrast control L

Main contrast control M

Main contrast control H

Sub contrast control L

Sub Brightness G, B, R = 255 ADC output conversion level

Sub Brightness G, B, R = 0 G, B, R OUT pin voltage

Sub Brightness G, B, R = 128 G, B, R OUT pin voltage

Sub Brightness G, B, R = 255 G, B, R OUT pin voltage

VBRL – VBRM

VBRH – VBRM

Cb, Cr offset = 32 ADC output conversion level

Cb, Cr offset = 0 B, R OUT pin voltage

Cb, Cr offset = 32 B, R OUT pin voltage

Cb, Cr offset = 63 B, R OUT pin voltage

VCLL – VCLM

VCLH – VCLM

Main Contrast = 0 Sub Contrast = 128 Vin = 1.2Vp-p RGB/YUV mode, G, B, R OUT

Main Contrast = 128 Sub Contrast = 128 Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT

Main Contrast = 255 Sub Contrast = 128 Vin = 0.45Vp-p RGB/YUV mode, G, B, R OUT

Main Contrast = 128 Sub Contrast = 0 Vin = 0.85Vp-p RGB/YUV mode, G, B, R OUT

53

1.388

1.63

1.86

—

120

1.94

1.99

2.03

—

200

0.62

1.23

1.79

0.96

61

1.588

1.83

2.06

–242

230

128

2.23

2.28

2.34

–60

60

—

0.78

1.53

2.24

1.2

69

1.788

2.03

2.26

—

136

2.46

2.51

2.58

—

— —

0.94

1.84

2.69

1.44

LSB

V

mV

LSB

V

mV

ns

times

VBRHAD

VBRL

VBRM

VBRH

VCLMAD

VCLL

VCLM

VCLH

TWCLP

VMCL

VMCM

VMCH

VSCL

AMP

Item Symbol

Measurement conditions

Min. Typ.

Max.

Unit

– 24 –

CXA3516R

Sub contrast control H

Gain difference among RGB

Frequency response

Cross talk characteristics

Cross talk between channels

Cross talk among RGB

Main Contrast = 128 Sub Contrast = 255 Vin = 0.55Vp-p RGB/YUV mode, G, B, R OUT

Main Contrast = 128 Sub Contrast = 128 Vin = 0.6Vp-p RGB/YUV mode, G, B, R OUT

Main Contrast = 128 Sub Contrast = 128 fin = 100MHz, Vin = 0.6Vp-p

1.48

–8

—

1.85

0

220

–35

–30

2.22

8

—

times

%

MHz

dB

VSCH

∆Gain

FC – 3dB

CTC

CTB

AMP (Cont.)

SYNC SEP input characteristics

SYNC TIP input minimum amplitude

SYNC TIP input minimum duty

SYNC SEP threshold voltage

SYNC SEP hysteresis voltage

SYNC SEP VTH = 1000 SYNC SEP VHYS = 10

0.2

5

116

36

—

145

45

—

174

54

Vp-p

%

mV

VSYN

DSYN

VTH

VHYS

SYNCSEP

Item Symbol Measurement conditions

Min. Typ. Max. Unit

Item Symbol

Measurement conditions

Min. Typ. Max. Unit

– 25 –

CXA3516R

Hold characteristics

RC1 pin leak current

SYNC signal input characteristics

SYNC signal input frequency range

VCO characteristics

Clock frequency Clock frequency Clock frequency Clock frequency VCO lock range VCO gain 1 VCO gain 2 VCO gain 3 VCO gain 4

Jitter characteristics

SYNC input signal – Clock output jitter (NTSC)

SYNC input signal – Clock output jitter (VGA)

SYNC input signal – Clock output jitter (SVGA)

SYNC input signal – Clock output jitter (XGA)

SYNC input signal – Clock output jitter (SXGA)

SYNC input signal – Clock output jitter (UXGA)

Delay sync – Clock output jitter

VCO frequency divider DIV = 1/1 VCO frequency divider DIV = 1/2 VCO frequency divider DIV = 1/4 VCO frequency divider DIV = 1/8

Triggered at SYNC Fsync = 15.73kHz Fclk = 12.27MHz N = 780

Triggered at SYNC Fsync = 31.47kHz Fclk = 25.18MHz N = 800

Triggered at SYNC Fsync = 48.08kHz Fclk = 50.00MHz N = 1040

Triggered at SYNC Fsync = 56.48kHz Fclk = 75.00MHz N = 1328

Triggered at SYNC Fsync = 79.98kHz Fclk = 135.01MHz N = 1688

Triggered at SYNC Fsync = 75.00kHz Fclk = 162.00MHz N = 2160

Triggered at DSYNC

—

10

80 40 14

5

2.0 300 150

75

37.5

2.4

1.6

1.3

0.9

0.8

—

— — — — — — — — —

2.7

1.8

1.4

1.0

0.9

0.85

—

1.0

130

165

80 40 14

4.5 500 250 125

62.5

3

2.0

1.5

1.1

1.0

0.1

nA

kHz

MHz MHz MHz MHz

V Mrad/sv Mrad/sv Mrad/sv Mrad/sv

ns

Ileak

FSYNC

FCLK1 FCLK2 FCLK3 FCLK4 Vlock KVCO1 KVCO2 KVCO3 KVCO4

Tj1p-p

Tj2p-p

Tj3p-p

Tj4p-p

Tj5p-p

Tj6p-p

Tj7p-p

PLL

Item Symbol

Measurement conditions

Min. Typ. Max. Unit

– 26 –

CXA3516R

Resolution

DC characteristics

Integral linearity error Differential linearity error

Reference voltage

Top reference voltage

Bottom reference voltage Input dynamic range

AC characteristics

Maximum conversion frequency of Straight Data out Mode

Maximum conversion frequency of DMUX Parallel Data out Mode

Maximum conversion frequency of DMUX Interleaved Data out Mode

Maximum conversion frequency of 4:2:2 Data out D2 Mode

Maximum conversion frequency of 4:2:2 Data out Special Mode

AVccAD3 as a reference

AVccAD3 as a reference VRT – VRB

—

— —

–0.3

–1.3

0.9

100

165

100

8

1.0

0.4

–0.4

–1.4

1.0

—

0.7

–0.6

–1.6

1.1

—

bit

LSB LSB

V

MSPS

ILE DLE

VRT

VRB VTB

Fc

ADC

Item Symbol

Measurement conditions

Min. Typ. Max. Unit

– 27 –

CXA3516R

Digital input (PECL)

Digital input voltage: H Digital input voltage: L Digital input current: H Digital input current: L

Digital input (TTL)

Digital input voltage: H Digital input voltage: L Threshold voltage Digital input current: H Digital input current: L

Digital output (TTL)

Digital output voltage: H

Digital output voltage: L

DVccPLL as a reference DVccPLL as a reference VIH1 = DVCC

PLL – 0.8V

V

IL1 = DVCC

PLL – 1.6V

V

IH = 3.5V

VIL = 0.2V

IOH = –2mA IOH = –2mA IOH = –2mA IOH = –2mA IOL = 1mA

–1.15

— –100 –200

2.0

—

–10 –20

2.4

2.3

2.05

1.85

—

— — — —

— —

1.5

— —

2.95

2.7

2.45

2.2

0.2

—

–1.5

100

0

—

0.8

— –5

0

3.3

3.0

2.75

2.5

0.5

V

V µA µA

V

V µA µA

V

VIH1 VIL1 IIH1 IIL1

VIH2 VIL2 VTH IIH2 IIL2

VOH1 VOH2 VOH3 VOH4 VOL

I/O

Item Symbol

Measurement conditions

Min. Typ. Max. Unit

– 28 –

CXA3516R

Clock output rise time Clock output fall time Delay sync output

rise time Delay sync output

fall time Data output rise time Data output fall time HOLD signal setup time HOLD signal hold time Delay sync delay time

coarse delay Delay sync delay time

fine delay Clock output delay from

SYNC input signal Delay time between clock

output and DSYNC/DIVOUT signal

DIVOUT signal output delay time

Clock – 1/2 clock 1/2 clock – Data Clock – Data

0.8 to 2.0V (CLK, 1/2CLK)

2.0 to 0.8V (CLK, 1/2CLK)

0.8 to 2.0V (DSYNC, DIVOUT, SOGOUT)

2.0 to 0.8V (DSYNC, DIVOUT, SOGOUT)

0.8 to 2.0V

2.0 to 0.8V

CL = 9pF

Difference between delay sync signal and DIVOUT signal

0.8

1.0

0.8

1.0

0.9

0.9 20 20

3

1/32

6.0

0.8

4

0.9

2.3

2.2

1.4

1.5

1.4

1.5

1.2

— —

—

7.0

1.0

—

1.2

2.6

2.8

2.3

2.8

2.3

2.8

2.0

— —

6

64/32

8.0

1.3

5

1.6

3.2

3.8

ns ns

ns

ns ns

ns ns ns

CLK

ns

CLK

ns ns ns

T

R_CLK

TF_CLK TR_DSYNC

TF_DSYNC TR_DATA

TF_DATA Ths Thh

Td_1

Td_2

Td_3

Td_4

Td_5 Td_6

Td_7 Td_8

Item Symbol

Measurement conditions

Min. Typ. Max. Unit

Timing Characteristics

– 29 –

CXA3516R

Electrical Characteristics Measurement Circuit

(3-wire Control)

0.1µ

75

820

0.1µ

75

0.1µ

75

0.1µ

75

0.1µ750.1µ

1µ

100p

0.33µ

3.3k

3k

330p

75

5k

0.1µ

4.7k

820

AVCC5V

DV

CC5V

3.3V

DGND

AGND

1µ

ANALOG

SIGNAL

ANALOG

SIGNAL

ANALOG

SIGNAL

BUS CONTROLER

37

A

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

7374757677

78 79 80 81 828384

85 8687

88 89 90 91 92 93 949596979899

100101102103104105106107108

133

134

135

136

137

138

139

140

141

1 2 3 4

121

122

123

124

125

126

127

128

129

130

131

132

142

143

144

110

109

111

112

113

114

115

116

117

118

119

120

5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 3611 21 31

B/CbOUT

ADDRESS

R/CrOUT

NC

XPOWER SAVE

DGNDREG

DVCCREG

SDA

SCL

XSENABLE

SEROUT

3WIRE/I

2

C

DPGND

AVCCADREF

AVCCAD3

VRT

DVCCAD3

DVCCADTTL

DGNDADTTL

RA0

RA1

DGNDAD3

RA2

RA3

RA4

RA5

RA6

AGNDAD3

DGNDAD3

RA7

DVCCADTTL

DGNDADTTL

RB0

RB1

RB2

GA4

GA3

GA2

GA1

GA0

DGNDADTTL

DGNDAD3

DVCCADTTL

BB7

BB6

BB5

BB4

BB3

GNDAD3

BB2

BB1

BB0

DGNDADTTL

DV

CCADTTL

BA7

BA6

BA5

DGNDAD3

BA4

BA3

BA2

BA1

BA0

DGNDADTTL

DGNDAD3

DVCCADTTL

RB7

RB6

RB5

RB4

RB3

EVEN/ODD

XTLOAD

HOLD

SOGOUT

UNLOCK

DSYNC/DIVOUT

DPGND

1/2CLK

1/2XCLK

CLK

XCLK

DGNDPLLTTL

DVCCPLLTTL

AGNDADREF

AVCCAD3

VRB

DVCCAD3

DVCCAD

DVCCADTTL

DGNDADTTL

GB7

GB6

DGNDAD3

GB5

GB4

GB3

GB2

GB1

AGNDAD3

DGNDAD3

GB0

DGNDADTTL

DVCCADTTL

GA7

GA6

GA5

XCLKIN

CLKIN

SYNCIN1

SYNCIN2

CLPIN

DVCCPLL

DGNDPLL

AVCCVCO

AGNDVCO

RC1

RC2

AVCCIR

IREF

DPGND

AGNDIR

G/YIN1

AVCCAMPG

G/YIN2

AGNDAMPG

G/YCLP

B/CbCLP

R/CrCLP

DPGND

SOGIN1

B/CbIN1

AVCCAMPB

SOGIN2

B/CbIN2

AGNDAMPB

DPGND

R/CrIN1

AVCCAMPR

R/CrIN2

AGNDAMPR

G/YOUT

DACTESTOUT

CLAMP

PULSE

HSYNC

EXT CLK

EXT XCLK

– 30 –

CXA3516R

Control Register Functions Table

Block

Function

Feedback programmable

counter control

VCO frequency divider

control

Delay control

(lower order)

Delay control

(higher order)

Charge pump current

control

DIVOUT signal pulse

width control

DIVOUT signal delay

control

Delay sync output polarity

control

Hold input polarity control

12

2

6

2

3

2

1

0

1

2

3

4

m4

O

m3

O

m2

O

m1

O

m0

m8

O

n2

m7

O

n1

m6

O

n0

m5

O

VCO DIV

DIV1, 2, 4, 8

FINE DELAY

COARSE

DELAY

Charge.Pump

DIVOUT WIDTH

DIVOUT DELAY

DSYNC POL

HOLD POL

Frequency division ratio =

(m + 1) × 8 + n

00: 1/1

01: 1/2

10: 1/4

11: 1/8

000000: 1/32CLK

111111: 64/32CLK

00: 3CLK

01: 4CLK

10: 5CLK

11: 6CLK

000: 100µA

001: 200µA

010: 300µA

011: 400µA

100: 500µA

101: 600µA

110: 700µA

111: 800µA

00: 1CLK

01: 2CLK

10: 4CLK

11: 8CLK

0: 4CLK

1: 5CLK

0: NEGATIVE

1: POSITIVE

0: NEGATIVE

1: POSITIVE

bit

Register

No.

PLL

Data

D7

D6 D5

D4

D3

D2

D1

D0

Register Name

Control Range (typ.)

– 31 –

CXA3516R

Block

Function

Phase comparison input

positive/negative control

Sync input polarity control

SOG OUT polarity control

Clamp pulse input polarity

control

External clock/internal

VCO switching

Delay sync output/DIVOUT

switching

Delay sync hold function

Output SOG/HSYNC

switching

HSYNC1, 2 input/SOGA

switching

HSYNC1 input/HSYNC2

input switching

TTL output off function

(clock)

TTL output off function

(inverse clock)

TTL output off function

(1/2 clock)

TTL output off function

(inverse 1/2 clock)

TTL output off function

(delay sync)

1

4

5

6

O

PD POL

SYNC POL

SOG OUT POL

CLP POL

VCO By-pass

DSYNC By-pass

DSYNC Hold

SYNC OUT SW

SYNCP/

HSYNC

HSYNC 1/2

CLK Enable

XCLK Enable

1/2CLK Enable

1/2XCLK

Enable

DSYNC Enable

0: NEGATIVE

1: POSITIVE

0: NEGATIVE

1: POSITIVE

0: NEGATIVE

1: POSITIVE

0: NEGATIVE

1: POSITIVE

0: EXT CLK

1: INT VCO

0: DIVOUT

1: DSYNC

0: NORMAL

1: HOLD

0: SYNCT

1: SYNCP/HSYNC

0: SYNCP

1: HSYNC1, 2

0: EXT SYNC1

1: EXT SYNC2

0: TTL out OFF

1: TTL out ON

0: TTL out OFF

1: TTL out ON

0: TTL out OFF

1: TTL out ON

0: TTL out OFF

1: TTL out ON

0: TTL out OFF

1: TTL out ON

bit

Register

No.

PLL

Data

D7

D6 D5

D4

D3

D2

D1

D0

Register Name

Control Range (typ.)

– 32 –

CXA3516R

Block

Function

TTL output off function

(UNLOCK)

TTL output off function

(SOG OUT)

TTL output off function

(SER OUT)

Main contrast

Sub contrast Gch

Sub contrast Bch

Sub contrast Rch

Sub brightness Gch

Sub brightness Bch

Sub brightness Rch

Cb input clamp level

adjustment in YUV mode

Cr input clamp level

adjustment in YUV mode

YCbCr input mode clamp

level switching

RGB OUT output signal selection

SW output and AMP output

RGB2 input selection

1

8

6

1

6

7

8

9

10

11

12

13

14

15

16

O

UNLOCK

Enable

SOG Enable

SEROUT

Enable

MAIN

CONTRAST

SUB

CONTRAST G

SUB

CONTRAST B

SUB

CONTRAST R

SUB

BRIGHTNESS G

SUB

BRIGHTNESS B

SUB

BRIGHTNESS R

Cb Offset

Cr Offset

YCbCr mode

RGB Out Select

RGB In Select

0: TTL out OFF

1: TTL out ON

0: TTL out OFF

1: TTL out ON

0: TTL out OFF

1: TTL out ON

00000000: Mgain = × 0.78

11111111: Mgain = × 2.24

00000000: Mgain = × 0.79

11111111: Mgain = 1.21

00000000: Mgain = × 0.79

11111111: Mgain = 1.21

00000000: Mgain = × 0.79

11111111: Mgain = 1.21

00000000: VRB – 61LSB

11111111: VRB + 61LSB

00000000: VRB – 61LSB

11111111: VRB + 61LSB

00000000: VRB – 61LSB

11111111: VRB + 61LSB

00000000: 128LSB – 16LSB

11111111: 128LSB + 16LSB

00000000: 128LSB – 16LSB

11111111: 128LSB + 16LSB

0: RGB IN

1: YCbCr IN

0: AMP OUT

1: SW OUT

0: IN1

1: IN2

bit

Register

No.

PLL

REGISTER

AMP

Data

D7

D6 D5

D4

D3

D2

D1

D0

Register Name

Control Range (typ.)

– 33 –

CXA3516R

Block

Function

Brightness clamp off

SYNC SEP hysteresis

level setting during SYNC

ON GREEN

SYNC SEP threshold level

setting during SYNC ON

GREEN

ADC DATA output polarity

control

DATA output mode

switching

ADC power save

AMP power save

PLL power save

SYNC SEP power save

TTLOUT CLP LEVEL

1

2

4

1

3

1

2

16

17

18

19

O

Brightness CLP

SYNC SEP

VHYS

SYNC SEP

VTH

DATA OUT POL

DATA OUT

MODE

ADC Power

Save

AMP Power

Save

PLL Power

Save

SYNC SEP

Power Save

TTLOUT CLP

0: ON

1: OFF

00: 2mV

01: 20mV

10: 45mV

11: 70mV

0000: 75mV

10mV step

1111: 215mV

0: all 1 → all 0(NEGATIVE)

1: all 0 → all 1(POSITIVE)

000: Straight

001: DMUX Parallel

010: DMUX Interleaved

011: YUV4:2:2 D2

111: YUV4:2:2 Special

0: active

1: power save

0: active

1: power save

0: active

1: power save

0: active

1: power save

00: 2.20V

01: 2.45V

10: 2.70V

11: 2.95V

bit

Register Name

Control Range (typ.)

Register

No.

AMP

SYNC

SEP

SYNC

SEP

ADC

AMP

PLL

SYNC

SEP

TTLOUT

D7

D6 D5

D4

D3

D2

D1

D0

Data

– 34 –

CXA3516R

Register

No.

Register Name

D7

Data

D6

D5

D4

D3

D2

D1

D0

Sub Address

Register 0Register 1Register 2Register 3Register 4Register 5Register 6Register

7

Register 8Register

9

Register

10

VCODIV1

Reference

VCODIV2

Reference

DELAY

ReferenceCPReference

POLARITY

Reference

SYNC

Reference

TTLOUT

ENABLE

Reference

MAIN

CONTRAST

Reference

SUB

CONTRAST G

Reference

SUB

CONTRAST B

Reference

SUB

CONTRAST R

Reference

VCODIV

Bit7

0

Coarse Delay

Bit1

0

SEROUT

Enable

1

Main Contrast

Bit7

1

Sub Contrast G

Bit7

1

Sub Contrast B

Bit7

1

Sub Contrast R

Bit7

1

VCODIV

Bit6

0

Coarse Delay

Bit0

0

SOG Enable

1

Main Contrast

Bit6

0

Sub Contrast G

Bit6

0

Sub Contrast B

Bit6

0

Sub Contrast R

Bit6

0

VCODIV

Bit5

1

DIV1, 2, 4, 8

Bit1

0

Fine Delay

Bit5

1

DIVOUT

DELAY

1

CLP POL

1

HSYNC1/2

0

UNLOCK

Enable

1

Main Contrast

Bit5

0

Sub Contrast G

Bit5

0

Sub Contrast B

Bit5

0

Sub Contrast R

Bit5

0

VCODIV

Bit4

1

DIV1, 2, 4, 8

Bit0

1

Fine Delay

Bit4

0

DIVOUT Width

Bit1

0

SOGOUT POL

1

SYNCP/

HSYNC IN

1

DSYNC

Enable

1

Main Contrast

Bit4

0

Sub Contrast G

Bit4

0

Sub Contrast B

Bit4

0

Sub Contrast R

Bit4

0

VCODIV

Bit3

1

VCODIV

Bit11

0

Fine Delay

Bit3

0

DIVOUT Width

Bit0

0

SYNC IN POL

1

SYNC OUT

SW

1

1/2XCLK

Enable

1

Main Contrast

Bit3

0

Sub Contrast G

Bit3

0

Sub Contrast B

Bit3

0

Sub Contrast R

Bit3

0

VCODIV

Bit2

0

VCODIV

Bit10

1

Fine Delay

Bit2

0

Charge Pump

Bit2

0

PD POL

1

DSYNC Hold

0

1/2CLK

Enable

1

Main Contrast

Bit2

0

Sub Contrast G

Bit2

0

Sub Contrast B

Bit2

0

Sub Contrast R

Bit2

0

VCODIV

Bit1

0

VCODIV

Bit9

0

Fine Delay

Bit1

0

Charge Pump

Bit1

1

HOLD POL

1

DSYNC

By-pass

1

XCLK Enable

1

Main Contrast

Bit1

0

Sub Contrast G

Bit1

0

Sub Contrast B

Bit1

0

Sub Contrast R

Bit1

0

VCODIV

Bit0

0

VCODIV

Bit8

1

Fine Delay

Bit0

0

Charge Pump

Bit0

1

DSYNC POL1VCO By-pass

1

CLK Enable

1

Main Contrast

Bit0

0

Sub Contrast G

Bit0

0

Sub Contrast B

Bit0

0

Sub Contrast R

Bit0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00 (H)

01 (H)

02 (H)

03 (H)

04 (H)

05 (H)

06 (H)

07 (H)

08 (H)

09 (H)

0A (H)

38 (H)

15 (H)

20 (H)

23 (H)

3F (H)

1B (H)

FF (H)

80 (H)

Register Assignment

PLLAMP

A4

A3

A2

A1

A0

HEX code

– 35 –

CXA3516R

Register

No.

Register Name

D7

D6

D5

D4

D3

D2

D1

D0

Data

A4

A3

Sub Address

A2

A1

A0

HEX code

Register 11Register 12Register 13Register 14Register 15Register 16Register 17Register 18Register

19

SUB

BRIGHTNESS G

Reference

SUB

BRIGHTNESS B

Reference

SUB

BRIGHTNESS R

Reference

CbOFFSET

Reference

CrOFFSET

Reference

AMP MODE

Reference

SYNCSEP

Reference

OUTPUT MODE

Reference

POWER SAVE

Reference

Sub

Brightness G

Bit7

1

Sub

Brightness B

Bit7

1

Sub

Brightness R

Bit7

1

Sub

Brightness G

Bit6

0

Sub

Brightness B

Bit6

0

Sub

Brightness R

Bit6

0

Sub

Brightness G

Bit5

0

Sub

Brightness B

Bit5

0

Sub

Brightness R

Bit5

0

Cb Offset

Bit5

1

Cr Offset

Bit5

1

Sync Sep V

TH

Bit3

1

TTLOUT CLP

Bit1

1

Sub

Brightness G

Bit4

0

Sub

Brightness B

Bit4

0

Sub

Brightness R

Bit4

0

Cb Offset

Bit4

0

Cr Offset

Bit4

0

Sync Sep V

TH

Bit2

0

TTLOUT CLP

Bit0

1

Sub

Brightness G

Bit3

0

Sub

Brightness B

Bit3

0

Sub

Brightness R

Bit3

0

Cb Offset

Bit3

0

Cr Offset

Bit3

0

Brightness

CLP

0

Sync Sep V

TH

Bit1

0

DATA OUT MODE

Bit2

0

Sync Sep

Power Save

0

Sub

Brightness G

Bit2

0

Sub

Brightness B

Bit2

0

Sub

Brightness R

Bit2

0

Cb Offset

Bit2

0

Cr Offset

Bit2

0

RGB In1/2

Select

0

Sync Sep V

TH

Bit0

0

DATA OUT

MODE

Bit1

0

PLL

Power Save

0

Sub

Brightness G

Bit1

0

Sub

Brightness B

Bit1

0

Sub

Brightness R

Bit1

0

Cb Offset

Bit1

0

Cr Offset

Bit1

0

RGB Out

Select

0

Sync Sep VHYS

Bit1

1

DATA OUT

MODE

Bit0

1

AMP

Power Save

0

Sub

Brightness G

Bit0

0

Sub

Brightness B

Bit0

0

Sub

Brightness R

Bit0

0

Cb Offset

Bit0

0

Cr Offset

Bit0

0

YCbCr mode

0

Sync Sep VHYS

Bit0

0

DATA OUT

POL

1

ADC

Power Save

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0B (H)

0C (H)

0D (H)

0E (H)

0F (H)

10 (H)

11 (H)

12 (H)

13 (H)

80 (H)

20 (H)

00 (H)

22 (H)

03 (H)

30 (H)

AMP

SYNC

SEP

ADC

POWER

SAVE

– 36 –

CXA3516R

Description of Operation

Control Register

Programmable control can be performed for many functions of this IC.

1) Mode selection

Both I2C bus and 3-wire bus mode can be supported, and either of these modes can be selected by the 3WIRE/I2C (Pin 13).

3WIRE/I2C pin voltage

Setting mode

0V 1/2VCC VCC (5V)

I

2

C (High) I2C (Low) 3-wire bus

I2C (High) mode

Threshold voltage (Low → High) Threshold voltage (High → Low)

1.95V

1.6V

I2C (Low) mode

Threshold voltage (Low → High) Threshold voltage (High → Low)

1.65V

1.3V

3-wire bus mode

Threshold voltage (Low → High) Threshold voltage (High → Low)

1.65V

1.3V

The pin threshold voltages are set at 1/3VCC and 2/3VCC.

2) Threshold voltage

In I2C bus mode, both SDA (Pin 9) and SCL (Pin 10) are input. These input logic signals can have two threshold voltages by the 3-wire/I2C. These threshold voltages have the following hysteresis.

SDA, SCL pin threshold voltages

SDA, SCL and XSENABLE pin threshold voltages

In 3-wire bus mode, the threshold voltages of the logic signal input to the SDA, SCL and XSENABLE pins have the following hysteresis.

– 37 –

CXA3516R

3-wire Bus Mode

Various control can be performed by setting the internal control register values via the serial interface comprised of the three pins SDA (Pin 9), SCL (Pin 10) and XSENABLE (Pin 11). Data can be accepted when XSENABLE is low level. When XSENABLE is high level, data cannot be accepted. The SDA pins of multiple IC can also be connected to the same bus line and each IC can be controlled independently by XSENABLE. XSENABLE may change the state when SCL is high level.

1) Write mode

8-bit control data consisting of a 7-bit sub address and 1-bit READ/WRITE setting is input in series from the LSB to the SDA pin. When READ/WRITE setting is "1", data can be written to register. When this IC is used in 3-wire bus mode, the sub address is 5 bits, so always set the 2 MSB bits to "0". Input the clock to the SCL pin. Data is loaded to the SDA pin at the rising edge of this clock. The data is set in the register at the rising edge of XSENABLE. The SDA and SCL pins are also used in I2C bus control mode.

XSENABLE

SCL

SDA

A0

LSB

SUB ADDRESS

MSB LSB MSB

A1 A2 A3 A4

A5 A6

00

1 D0D1D2D3D4D5D6D7

DATAREAD/WRITE

XSENABLE

SCL

SDA

TENS

TDS TDH

TENH

TENPW

READ/WRITE 0: READ Mode 1: WRITE Mode

Set the VCO post-stage frequency divider (DIV1, 2, 4, 8) and programmable counter (VCODIV) in the following order. The data is set when Register1 is sent.

Register0 (SUB ADDRESS (H): 00)

↓

Register1 (SUB ADDRESS (H): 01)

– 38 –

CXA3516R

2) Read mode

Input the 7-bit sub address and 1-bit READ/WRITE setting to the SDA pin. When READ/WRITE setting is "0", the 8-bit internally set data is output in series from the LSB by the SEROUT (Pin 12). While data is being output from the SEROUT pin, don't care what data is input to the SDA pin. Use the read function to check whether the data is set correctly inside the IC.

A5 A6

00

XSENABLE

SCL

SDA

SEROUT

A0

LSB

SUB ADDRESS

MSB

LSB MSB

A1 A2 A3 A4 0

D0 D1 D2 D3 D4 D5 D6 D7

DATA

XSENABLE

SCL

SDA

SEROUT

TENS

TDS TDH TD

TENH

READ/WRITE

TENPW

READ/WRITE 0: READ Mode 1: WRITE Mode

The SEROUT pin is TTL output. When not using the READOUT function, the TTL output circuit can be turned off by control register.

Register: SEROUT ENABLE

SEROUT output status

0

Function off

1

Function on

Power-on Reset

When the power supply rises, the power-on reset circuit operates and all the control register data is set to "1". AMP, ADC, PLL and SYNCSEP are all set to power save mode, and all the TTL output pins are set to high impedance mode. Therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes.

– 39 –

CXA3516R

I2C BUS Mode

Various control can be performed by setting the internal control register values via the serial interface comprised of the SDA (Pin 9) and SCL (Pin 10). This mode has only a write mode for setting data, and there is no read mode. Therefore, address "S0" set READ/WRITE is always "0".

ADDRESS pin voltage

SLAVE ADDRESS

0V

1001 1000

1/3VCC

1001 1100

2/3VCC

1001 1110

VCC (5V)

1001 1010

SLAVE ADDRESS

S7

1

S6

0

S5

0

S4

1

S3

1

S2

x

S1

x

S0

0

The pin threshold voltages are set to 1/4VCC, 1/2VCC and 3/4VCC.

An 8-bit slave address (IC address), 8-bit sub address, and a number of 8-bit data strings are input in series from the MSB to the SDA pin. When this IC is used in I2C bus mode, sub address is 5 bits, and 3 bits of MSB side are set to always "0". ACK signal is returned from the IC to confirm that the data has been received for each 8-bit data. The sub address can be designated optionally. The sub address is auto-incremented in order from the designated sub address, and the data strings are loaded in succession. To set the data at a specific separated sub address, either send the stop condition and then reset the sub address, or also send the data of unchanged portions so that the data is continuous. Only auto-increment mode is supported, and the sub address + data + sub address + data mode where only specific sub addresses are designated is not supported.

S7

SDA

S6 S5 S4 S3 S2 S1 S0

MSB LSB

A6A7 A5

000

A4

SUB ADDRESS

A3 A2 A1 A0

ACKACK

SLAVE ADDRESS

D6D7 D5 D4

DATA

D3 D2 D1 D0

ACK

D6D7 D5 D4

DATA

D3 D2 D1 D0 ACK

SCL

STOP CONDITIONSTART CONDITION

• START CONDITION When SCL pin is high level, the signal input to SDA pin has a falling edge, there is START CONDITION.

• STOP CONDITION When SCL pin is high level, the signal input to SDA pin has a rising edge, there is STOP CONDITION.

Four different kinds of slave address (IC address) can be set by externally setting the ADDRESS (Pin 2) to a specific voltage.

– 40 –

CXA3516R

I2C BUS Control Signals

SDA

SCL

P S Sr P

TBUF

TLOW

TR_REG

TF_REG

THD;STA

THD;STA THD;DAT TSU;DAT TSU;STA TSU;STOTHIGH

Power-on Reset

When the power supply rises, the power-on reset circuit operates and all the control register data are set to "1". AMP, ADC, PLL and SYNCSEP are all set to power save mode, and all the TTL output pins are set to high impedance mode. Therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes.

– 41 –

CXA3516R

Amplifier

This is a 3-channel AMP that optimizes the AC coupled RGB analog input signals and YCbCr analog input signals for ADC input. Switch input mode between RGB input or YCbCr input with the control register. The AC coupled analog input signals are synchronously clamped by the externally input clamp pulse at a pedestal level. An input capacitor of 0.1µF is recommended.

Allowing two lines of input to be selected for the analog input signal, the AMP includes a high frequency, low cross talk video switch circuit for input switching. Switching is performed using a control register. When using only one line, leave the unused line open. The input band of the analog input signal is 220MHz in the –3dB bandwidth range.

There are main contrast and sub-contrast of the gain used to adjust the analog input signal to full scale (1V typ.) of the ADC. Each can be adjusted to one of 256 levels using control registers. Main contrast is controlled by moving the gain of the 3 RGB channels. The each gain of the 3 RGB channels can be controlled independently. In RGB input mode, the clamp level used for the black level adjustment can be adjusted independently for the 3 channels to any of 256 levels by using sub-brightness.

The ∗CLP pin∗1is connected to the hold capacitor of the clamp circuit for the sub-brightness. A hold capacitor of 0.1µF is recommended. The ∗OUT pins∗2can output signal immediately before input to the ADC or the signal after switching between the two lines of input select switch. Either of them can be selected by control register. As for emitter follower output, since the internal bias current is small, be sure to connect an 820Ω resistor between the ∗OUT pins

∗2

and AGND in order to view the signal with a high frequency. A 75Ω driver cannot be supported. In addition, load capacitance should be 5pF or less. When the SYNC ON GREEN signal is monitored at the ∗OUT pins∗2after the two lines of select switch, the sync amplitude is a maximum of 0.3V, for a limiter is applied at the amplifier input stage.

In YCbCr signal input mode, Y can be adjusted to any of 256 levels using the sub-brightness while Cb and Cr can be adjusted to any of 64 levels using the Cb or Cr offset. A detailed description of the above registers is given below.

∗1

∗CLP pins: Overall naming for R/Cr CLP (Pin 130), G/Y CLP (Pin 128), B/Cb CLP (Pin 129)

∗2

∗OUT pins: Overall naming for R/Cr OUT (Pin 3), G/Y OUT (Pin 143), and B/Cb OUT (Pin 1)

• Analog input signal mode switching

Analog input signal supports both RGB analog input signal and YCbCr analog input signal. This register switches the clamp level of the input clamp block and the amplifier output block in each mode. However, the G/Ych perform the same processing in both RGB input mode and YCbCr input mode.

Register: YCbCr mode

Analog input signal mode

0

RGB input

1

YCbCr input

Register: RGB In Select

Analog input signal channel switching

0

IN1

1

IN2

• Input channel switching

Input supports 2-channel input, and the input can be selected by an internal switch.

Register: CLP POL

Clamp pulse polarity

0

NEGATIVE

1

POSITIVE

• Clamp pulse input polarity

The clamp pulse input polarity can be selected by an internal switch.

– 42 –

CXA3516R

Register: Brightness CLP

Clamp operation

0

Clamp operation

1

Clamp off

• Brightness clamp off function

Clamp operation can be set to a mode where only the post-stage brightness clamp does not operate even if a clamp pulse is input to the CLPIN (Pin 113). At this time, all three channels of the ∗CLP pins∗1are set to high impedance simultaneously, and the signal black level can be varied in an analog manner by setting the voltages externally. However, the voltage value set here is not related to the VRT (Pin 17) and VRB (Pin

93) voltages or the ∗OUT∗2monitor signal output DC levels. Therefore the value should be set while monitoring the ADC data output or the data after that.

Register: RGB Out select

Monitor output switching

0

Amplifier output

1

Switch output

• Monitor signal output selection

The two monitor signal outputs (∗OUT pins

∗

2

) of the amplifier can be selected by an internal switch. One is amplifier output signal immediately before input to the ADC, and other is after switching between the two lines of select switch.

Register: MAIN CONTRAST

Amplifier gain (typ.)

SUB CONTRAST = 128

0

0.78

· · ·

128

1.53

· · ·

255

2.24

• Main contrast

The RGB channel gains can be set collectively by an 8-bit DAC setting.

Register: SUB CONTRAST R

Rch gain adjustment (typ.)

0

–21%

· · ·

128

0%

· · ·

255

+21%

• Rch sub contrast

The Rch contrast (R amplifier gain) can be adjusted independently within the range of ±21% relative to the main contrast by an 8-bit DAC setting.

Register: SUB CONTRAST G

Gch gain adjustment (typ.)

0

–21%

· · ·

128

0%

· · ·

255

+21%

• Gch sub contrast

The Gch contrast (G amplifier gain) can be adjusted independently within the range of ±21% relative to the main contrast by an 8-bit DAC setting.

Register: SUB CONTRAST B

Bch gain adjustment (typ.)

0

–21%

· · ·

128

0%

· · ·

255

+21%

• Bch sub contrast

The Bch contrast (B amplifier gain) can be adjusted independently within the range of ±21% relative to the main contrast by an 8-bit DAC setting.

– 43 –

CXA3516R

Register: YCbCr mode

Input signal mode

0

RGB

Register: SUB BRIGHTNESS R

Level shift amount (typ.)

0

–61LSB

· · ·

128

0LSB

· · ·

255

+61LSB

• Rch sub brightness in RGB mode

The Rch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Rch sub brightness can be varied within the range of ±25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V).

Register: YCbCr mode

Input signal mode

0

RGB

Register: SUB BRIGHTNESS G

Level shift amount (typ.)

0

–61LSB

· · ·

128

0LSB

· · ·

255

+61LSB

• Gch sub brightness in RGB mode

The Gch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Gch sub brightness can be varied within the range of ±25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V).

Register: YCbCr mode

Input signal mode

0

RGB

Register: SUB BRIGHTNESS B

Level shift amount (typ.)

0

–61LSB

· · ·

128

0LSB

· · ·

255

+61LSB

• Bch sub brightness in RGB mode

The Bch sub brightness (black level voltage) can be set by an 8-bit DAC during RGB signal input. The Bch sub brightness can be varied within the range of ±25% of the ADC input dynamic range (approximately 1V) centering on VRB (Pin 93) (approximately 1.9V).

Register: YCbCr mode

Input signal mode

1

YCbCr

Register: Cb Offset

Level shift amount (typ.)

0

112LSB

· · ·

32

128LSB

· · ·

63

144LSB

• Cbch black level shift in YCbCr mode

The Cbch black level voltage can be set by a 6-bit DAC during YCbCr signal input. The Cbch black level voltage can be varied within the range of ±16LSB centering on the ADC input dynamic range center ((VRT + VRB)/2).

Register: YCbCr mode

Input signal mode

1

YCbCr

Register: Cr Offset

Level shift amount (typ.)

0

112LSB

· · ·

32

128LSB

· · ·

63

144LSB

• Crch black level shift in YCbCr mode

The Crch black level voltage can be set by a 6-bit DAC during YCbCr signal input. The Crch black level voltage can be varied within the range of ±16LSB centering on the ADC input dynamic range center ((VRT + VRB)/2).

– 44 –

CXA3516R

• Input signal connection method

Input

Pin No.

Pin 124 Pin 126

Pin 133 Pin 136

Pin 139 Pin 141

G/YIN1 G/YIN2

B/CbIN1 B/CbIN2

R/CrIN1 R/CrIN2

68 to 75 78, 81 to 85, 87, 88

45 to 49, 51 to 53 56 to 58, 60 to 64

21, 22, 24 to 28, 31 34 to 41

GA0 to GA7 GB0 to GB7

BA0 to BA7 BB0 to BB7

RA0 to RA7 RB0 to RB7

Symbol

Output

Pin No. Symbol

1. When inputting both RGB and YCbCr, input according to the table above.

2. SYNCSEP is connected to G/YIN.

3. When inputting RGB and not using SYNCSEP, there is no difference between the three channels so the input order may be optional.

4. When inputting Y, Cb and Cr, be sure to input according to the table above. It is possible for only the R/Cr IN and B/Cb IN pins to be clamped to the center of the ADC input dynamic range.

– 45 –

CXA3516R

SYNCSEP

The SYNCSEP function can be used to separate and output the SYNC signal that is superimposed on the SYNC ON GREEN signal (including the SYNC ON Y signal). There are two major SYNCSEP circuits. One is the circuit for creating a SYNC signal to be input to the PLL, and the other is a circuit for outputting a SYNC signal from the SOGOUT (Pin 105) so that a clamp pulse can be created externally. These SYNCSEP circuits perform processing on entirely different channels. (See the block diagram for the SYNCSEP operational description.)

• SYNCSEP circuit for the PLL SYNC signal

In the case of the SYNC ON GREEN signal, the SYNC ON GREEN signal is AC coupled to the G/YIN1 (Pin

124) or the G/YIN2 (Pin 126) and the sync component is separated and used as a reference. An input capacitor of 0.1µF is recommended. When a signal is input to this pin, the pedestal level is clamped by a clamp pulse input to the CLPIN (Pin

113). After this, the signal is split into a signal to the amplifier circuit and the signal to the SYNCSEP circuits, and the SYNC signal is sent through a two lines of input select switch (SW SOGP) and the SYNC signal is separated by the SYNCSEP circuits. At this time, it is possible to minimize the jitter of the SYNC signal sent to the PLL by using a control register to select the threshold level (VTH) and hysteresis level (VHYS) of the SYNCSEP circuit according to the type of noise on the superimposed SYNC signal.

SOG SYNC SEP threshold (Versus pedestal level)

The SYNC signal separated by the SYNCSEP circuits can be switched at the SW PLL circuit with an externally input SYNC signal (the SYNC signal input from the SYNCIN1 or SYNCIN2 pin) by using control registers (SYNCP/HSYNC). The selected signal is input to the PLL block.

Selecting between the sync separated SYNC signal and the externally input SYNC signal

SOG SYNC SEP hysteresis

Register: SYNC SEP VTH

Threshold

0000

75mV

· · ·

9.3mV step

1111

215mV

Register: SYNC SEP VHYS

Hysteresis

00

2mV

01

20mV

10

45mV

11

70mV

Register: SYNCP/HSYNC IN

SYNC signal type SYNC signal input pin

01 Sync separated signal G/YIN1 pin

G/YIN2 pin

Externally input SYNC signal SYNCIN1 pin

SYNCIN2 pin

VTH

VHYS

Pedestal level

SYNC signal

– 46 –

CXA3516R

• SYNCSEP circuits for the SYNC signal for the clamp pulse

A SYNC ON GREEN signal is input to the SOGIN1 (Pin 132) or SOGIN2 (Pin 135). The AC coupled signal is internally sync tip clamped and the minimum level (bottom of sync) is turned into the internally-set DC level (approximately 2.8V). The sync tip clamped input signal is separated from the threshold of 165mV (at SYNC DUTY 5%) above from the bottom of the sync by the SYNCSEP circuit. After this, the signal is output at TTL level from the SOGOUT pin and used as a reference signal for generating a clamp pulse. Since no clamp pulse is required for the sync tip clamp, it is possible to output a SYNC signal from the SOGOUT pin even when there is no external clamp pulse present such as when power supply is turned on. An input capacitor of 0.1µF is recommended. A control register can be used to select output either the SYNC signal separated out from the signal input from the SOGIN1 pin or the SOGIN2 pin by SW SOG O or the previously described PLL SYNC signal output from the SW PLL circuit.

Output from the SOGOUT pin

SYNCT1, SYNCT2/SYNCP1, SYNCP2/SYNCIN1, SYNCIN2 output selection

SYNCT1, SYNCT2: The SYNC signal sync tip clamped and separated from the SOGIN1 and SOGIN2 pins SYNCP1, SYNCP2: The SYNC signal pedestal clamped and separated from the G/YIN1 and G/YIN2 pins SYNCIN1, SYNCIN2: The SYNC signal input from the SYNCIN1 and SYNCIN2 pins

Register: SYNC OUT SW

Output from the SOGOUT pin

0

SYNCT1, SYNCT2

1

SYNCP1, SYNCP2 or SYNCIN1, SYNCIN2

The SOGIN1, SOGIN2 and the previously described G/YIN1, G/YIN2 are interlocked as for the 2-ch selection (Register: RGB In Select).

Input channel selection

Register: RGB In Select

G/YIN pin selection

SOGIN pin selection

0 IN1 IN1

1 IN2 IN2

Register: SOGOUT POL SOGOUT output polarity

0

Negative

1

Positive

Register: SOG Enable

SOGOUT output status

0

Off

1

On

The polarity of signals output from the SOGOUT pin can be set by using registers.

• SYNC ON GREEN output enable

When the SOGOUT pin is not used, it is possible to turn off the TTL output using a control register. But it cannot be set to high impedance.

– 47 –

CXA3516R

Register: HSYNC1/2

SYNC signal input pin

0

SYNCIN1

1

SYNCIN2

Register: SYNC POL

SYNC signal input polarity

0

Negative

1

Positive

PLL

• SYNC signal input

The SYNC (HSYNC) used by the PLL is input from the SYNC signal input pins. There are two sets of input pins, SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112), which are switched by the control register.

SYNCIN1 input, SYNCIN2 input switching

SYNC signals within the range from 10kHz to 130kHz can be input. The input supports both positive and negative polarity.

SYNC signal input polarity

Set the register in accordance with the polarity of the externally input SYNC. When SYNC is positive polarity, set SYNC POL to "1". (Clock is generated in sync with the rising edge of SYNC.) When SYNC is negative polarity, set SYNC POL to "0". (Clock is generated in sync with the falling edge of SYNC.) When there is no SYNC input, the VCO oscillates at random and a random pulse is output from the CLK output.

DIV 1, 2, 4 ,8

Programmable counter

VCOCP

LPF

PD

AB

SYNC signal

Point A: VCO oscillation frequency Point B: Clock frequency

• Phase detector (PD)

The phase detector compares the phase of the SYNC signal with that of the programmable counter output signal. The phase comparison is performed at the edge, and a phase difference between the compared signals is output as a pulse. There is no hysteresis function for the input pins of the SYNC signal (SYNCIN1 and SYNCIN2) input to the phase detector. If necessary external waveform shaping should be done as jitter results when a noisy signal is input. Set the control register, PD POL, to "1" as for the input polarity of the phase detector.

• Hold function

The hold function holds the VCO input voltage and generates oscillation itself without performing phase comparison. The VCO oscillation frequency is held during this period without performing phase comparison, by inputting the HOLD signal from the HOLD (Pin 106). HOLD signal polarity can be set by using the control register: HOLD POL.

Register: HOLD POL

HOLD signal input polarity

0

Held while HOLD signal is Low Held while HOLD signal is High

1

For details, see the hold timing diagram.

– 48 –

CXA3516R

• Charge pump (CP)

The charge pump sets charge pump current to flow for the amount of time corresponding to the pulse width output from the phase detector. The phase detector gain is determined by the charge pump current. The amount of current can be varied by using a control register. This IC is used to set the charge pump current value according to the VCO oscillation frequency as given below.

[CP Setting Matrix]

VCO oscillation frequency: CP setting values

40MHz to 85MHz: 200µA

85MHz to 110MHz: 300µA 110MHz to 140MHz: 400µA 140MHz to 155MHz: 500µA 155MHz to 165MHz: 600µA

The VCO oscillation frequency is that at the Point A in the diagram.

Register: Charge Pump Bit2 Register: Charge Pump Bit1 Register: Charge Pump Bit0

Charge pump current

0 0 0

100µA

0 0 1

200µA

0 1 0

300µA

0 1 1

400µA

1 0 0

500µA

1 0 1

600µA

1 1 0

700µA

1 1 1

800µA

• Loop filter (LPF)

The control voltage input to the VCO is the pulse current output from the charge pump circuit that is smoothed by an integrating circuit (loop filter). The resistor and capacitor values of the integrating circuit are as follows. (For the circuit configuration, see the application circuit.)

C1 = 0.33µF C2 = 330pF R1 = 3.3kΩ

For the resistor and capacitors, use a metal film chip resistor with little temperature variation and ceramic chip capacitors. In particular, the 0.33µF capacitor should be equivalent to high dielectric constant series capacitor type B or better. (Electrostatic capacitance change ratio ±10%: T = –25 to +85°C) In case of using any resistors or capacitors except those given above, it is not guaranteed.

• VCO

The VCO oscillation frequency range covers from 40MHz to 165MHz.

– 49 –

CXA3516R

Register: CLK Enable, XCLK Enable

Clock output status

0

Off

1

On

• VCO frequency dividers (DIV 1, 2, 4, 8)

The oscillation frequency of the VCO can be divided to 1/1, 1/2, 1/4, or 1/8 according to a control register setting. Depending on the combination of the VCO oscillation frequency and VCO frequency divider, the Point B clock frequency covers an operating range of 5MHz to 165MHz. The matrix of the VCO frequency divider setting is as follows.

[VCO Frequency Divider Setting Matrix]

Clock frequency: DIV setting value

5MHz to 14MHz: 1/8 14MHz to 40MHz: 1/4 40MHz to 80MHz: 1/2 80MHz to 120MHz: 1/1

Register: DIV 1, 2, 4, 8 Bit1 Register: DIV 1, 2, 4, 8 Bit0

Counter frequency

0 0

1/1

0 1

1/2

1 0

1/4

1 1

1/8

• Programmable counter

The clock frequency at Point B is divided and a programmable counter output signal is generated. The frequency division ratio can be set optionally by using a 12-bit control register. This is determined by using lower order 3 bits and upper order 9 bits in the following formula.

Frequency division ratio = (m + 1) × 8 + n

m: 9 bits (VCO DIV Bit 3 to 11) n: 3 bits (VCO DIV Bit 0 to 2)

Register

No. Register 0 Register 1

Data7

MSB

m4

Register

Name VCODIV1 VCODIV2

Data6m3Data5m2Data4m1Data3

m0 m8

Data2

n2

m7

Data1

n1

m6

Data0

LSB

n0

m5

After the set value for the frequency division ratio is changed, that set value is loaded into the programmable counter when the output value of the programmable counter becomes "all 0".

• Clock output

When the input polarity of the SYNC signal is positive, the clock output is synchronized to the rising edge of the SYNC signal and is available as complementary signals CLK (Pin 99) and XCLK (Pin 98). The delay time of the clock output can be varied in the range of 1/32CLK to 64/32CLK by using a control register (see PLL timing diagram). Although the clock output can be turned off independently by using a control register, it cannot be set to high impedance. The operational frequency of the clock is up to 100MHz.

– 50 –

CXA3516R

Register: DSYNC By-pass

Signal output from the DSYNC/DIVOUT pin

1

DSYNC signal

0

DIVOUT signal

Register: 1/2CLK Enable, 1/2XCLK Enable

1/2 Clock Output Status

0

Off

1

On

• 1/2 clock output

1/2 clock signal is a signal that resets the clock by using a reset pulse created from an internal delay sync signal and divides the clock in half. The complementary signal is output from the 1/2CLK (Pin 101) and 1/2XCLK (Pin 100). (See the PLL timing diagram). Although the 1/2 clock output can also be independently turned off by the control register, it cannot be set to high impedance.

• Delay sync output

Two types of delay sync signal (DSYNC and DIVOUT) can be output from the DSYNC/DIVOUT (Pin 103). This is selected by switching a control register. The DSYNC signal is output as the input SYNC signal undergone timing control. The DIVOUT signal is output as the programmable counter output undergone timing control. Both can be used as reset signals for any connected IC such as a scaling IC.

Delay sync output signal (DSYNC/DIVOUT (Pin 103))

• DSYNC signal

A SYNC signal input that has been timing controlled by a clock generated by a PLL is output. Although only the forward edge is completely managed at this time with delay settings, etc., the back edge has an undefined width for one clock cycle because it latches and outputs the input SYNC signal.

• DIVOUT signal

A timing controlled programmable counter output signal is output. In addition to the COARSE DELAY that has been set by using the DSYNC signal, the delay time setting is output with a delay of 4 or 5 clocks. The pulse width is also managed by a clock.

[Function Correspondence Table for the DSYNC Signal/DIVOUT Signal]

Function DSYNC signal DIVOUT signal Register

COARSE DELAY

FINE DELAY

Pulse width

DIVOUT DELAY

Output polarity

Output enable

Output during HOLD

3CLK to 6CLK

1/32CLK to 64/32CLK

Fixed (depends on input SYNC signal width)

—

On/Off On/Off On/Off

3CLK to 6CLK

1/32CLK to 64/32CLK

1, 2, 4, 8CLK

4, 5CLK

On/Off On/Off On/Off

COARSE DELAY

FINE DELAY DIVOUT WIDTH DIVOUT DELAY

DSYNC POL

DSYNC Enable

DSYNC Hold

– 51 –

CXA3516R

Register: FINE DELAY

Delay time

000000

1/32CLK

000001

2/32CLK

· · · · · · · · · ·

111111

64/32CLK

Register: COARSE DELAY

Delay time

00

3CLK

01

4CLK

10

5CLK

11

6CLK

• Delay time setting (Fine Delay/Coarse Delay)

The delay sync output, clock output, and 1/2 clock output can make delay time setting (Fine Delay/Coarse Delay) for the input signal. The amount of delay time is from 3CLK Delay to 6CLK Delay for Coarse Delay and from 1/32CLK to 64/32CLK for Fine Delay. The delay time (Fine Delay/Coarse Delay) can be set by using the control registers shown below.

• DIVOUT signal output pulse width

The pulse width of the DIVOUT signal output can be set to 1, 2, 4, 8 clock pulse widths by using a control register.

Register: DIVOUT WIDTH

DSYNC signal width

00

1CLK

01

2CLK

10

4CLK

11

8CLK

Register: DIVOUT DELAY

Delay time

0

4CLK

1

5CLK

Register: DSYNC POL

Delay sync output polarity

0

Negative

1

Positive

• DIVOUT signal output delay time setting

The DIVOUT signal is output with 4 or 5 clock delay based on the delay time (Fine Delay/ Coarse Delay) set as described above. The clock delay time can be set by using a control register.

• Delay sync output polarity

The polarity of the delay sync signal output from the DSYNC/DIVOUT pin can be selected either negative or positive by using a control register.

Register: DSYNC Enable

Delay sync output status

0

Off

1

On

• Delay sync output status

Although it is possible to turn off the signal output from the DSYNC/DIVOUT pin by using a control register, it cannot be set to high impedance.

– 52 –

CXA3516R

Register:

DSYNC Hold

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

H

L

H

L

H

L

H

L

DIVOUT signal

L

DSYNC signal DIVOUT signal DIVOUT signal

DSYNC signal

Register:

DSYNC By-pass

HOLD signal logic (When HOLD POL register = 1)

Delay sync output

• Delay sync output status during hold

Register: The delay sync output during the hold period can be controlled with the DSYNC Hold register and the HOLD signal.

Register: DSYNC Hold

Delay sync output status

0

Using HOLD signal logic

1

DSYNC signal/DIVOUT signal

• XTLOAD signal (reset signal)

This input pin forces to reset the divider function of the programmable counter. Since this signal is not normally used, leave it open or fix to high level. When it is used, this signal is in conjunction with the HOLD signal. See the note given later regarding the combined use of these signals.

The values given in the above table are for when the DSYNC POL register is set to "1". The delay sync output status is reversed when DSYNC POL is set to "0".

XTLOAD pin

Programmable counter status

L

Forcible reset

H

Count

The output status resulting from this setting differs based on status of the DSYNC By-pass register.

– 53 –

CXA3516R

Register: The DSYNC Hold register and HOLD signal can be used to control the delay sync output during the hold period. The relationship between the delay sync output and the SYNC signal is shown below. (For each of CASE 1 to 3, the DSYNC POL register is "1". In addition, the DSYNC signal output and DIVOUT signal output can be switched by using the DSYNC By-pass register.)

CASE 1

SYNC signal (SYNC POL = 1)

HOLD signal

(1) DSYNC Hold = 1

(2) DSYNC Hold = 0

DSYNC signal

DIVOUT signal

– 54 –

CXA3516R

CASE 2

SYNC signal (SYNC POL = 1)

HOLD signal

(1) DSYNC Hold = 1

(2) DSYNC Hold = 0

DSYNC signal

DIVOUT signal

– 55 –

CXA3516R

CASE 3

SYNC signal (SYNC POL = 1)

HOLD signal

(1) DSYNC Hold = 1

(2) DSYNC Hold = 0

DSYNC signal

DIVOUT signal

– 56 –

CXA3516R

Notes on Using the HOLD Signal and XTLOAD Signal (Reset Signal)

If the cycle of the SYNC signal is lost, the phase difference between the SYNC signal and the programmable counter output in the phase detector will increase, and it will cause PLL unlock. At this time, the HOLD signal is input to the HOLD (Pin 106), phase comparison is stopped while the signal is high level (when the HOLD POL register is set to "1"), and the clock can be stably oscillated by holding the VCO oscillation frequency. Note, however, the correspondence differs depending on whether the number of locations where the SYNC signal period changes (the 0.5H region in the diagram) is odd or even.

Programmable counter

VCO

DIV 1, 2, 4, 8

CP

LPF

PD

SYNC signal

Clock output

SYNC signal

(SYNC POL = 0)

H 0.5H 0.5H 0.5H 0.5H

1234

HHH

HOLD signal

Programmable counter output signal

0.5H 0.5H 0.5H

8CLK

H

1

23

HHHH

XTLOAD signal

(reset signal)

Programmable counter output signal

∗

"HSYNC" and "XTLOAD" are synchronized

Tw (min) = 100ns

SYNC signal

(SYNC POL = 0)

HOLD signal

Case 1: When the 0.5H region is even (correspondence with HOLD signal only)

When the number of the 0.5H period is even, it is possible to hold the period of the programmable counter output stable by applying the HOLD signal before the frequency changes. This corresponds to the vertical blanking period of the composite sync (computer signal).

Case 2: When the 0.5H region is odd (correspondence with HOLD signal + XTLOAD signal (reset signal))

When the number of the 0.5H period is odd, if only the HOLD signal is used, the phase difference between the SYNC signal and the programmable counter output signal will increase in the extra 0.5H region and the lock will be lost momentarily. In this case, the 0.5H region is held by the HOLD signal, and it is possible to use the XTLOAD signal (reset signal) at 1H backward to the official counter period by resetting/setting the counter value. Although there are no particular restrictions on the setup time and hold time of the XTLOAD signal (reset signal), the pulse width of the XTLOAD signal (reset signal) is restricted while the HOLD signal is high. (When the HOLD POL register is set to "1".) If the rising edge of the XTLOAD signal (reset signal) is delayed by 8CLK from the falling edge of the SYNC signal, counter output will be obtained by synchronizing with the falling edge of the next SYNC signal. See the diagram for details on timing.

– 57 –

CXA3516R

• HOLD signal timing

SYNC signal (when SYNC POL = 1)

SYNC signal (when SYNC POL = 0)

HOLD signal (when HOLD POL = 1)

DIVOUT signal (when DSYNC POL = 0)

Clock output

Thold

ThsThh ThsThh

VCO oscillation frequency is held without performing phase comparison.

The HOLD signal setup time (Ths) is the time from the rising edge of the HOLD signal to the falling edge of the DIVOUT signal. The HOLD signal hold time (Thh) is the time from the falling edge of the DIVOUT signal to the rising edge of the HOLD signal. See the above timing diagram for details on the relationship with SYNC POL.

The frequency variation of CLK while held can be calculated as given below.

VCO

I

leak

C

–Q+Q

∆V

∆f

I

SW

I

SW

C · ∆V = Q = Ileak · Thold

C: Loop filter capacitance ∆V: Varying voltage due to leak current Ileak: Leak current of the internal amplifier Thold: Hold time

∆V = Ileak · Thold/C ∆f = ∆V · KVCO = Ileak · Thold/C · KVCO

For example,

Assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33µF, KVCO = 2π · 55 [MHz/V],

∆V = 1 · 10–9· 1 · 10–3/(0.1 · 10–6) = 3 · 10–6[V] ∆f = 1 · 10–9· 1 · 10–3/(0.1 · 10–6) · 2π · 70 · 106= 1050 [Hz]

– 58 –

CXA3516R

UNLOCK detect

UNLOCK signal

Vcc

R2

R3 50kΩ

Q1

R1 = 100Ω R2 = 100kΩ C1 = 0.01µF

IC externalIC internal

R1

I1

I2

S2 signal

S1 signal

C1

Signal from the phase detector

104

The UNLOCK output is an open collector. By connecting the external circuit shown above to this output pin, it is possible to adjust the sensitivity of the S2 signal by varying the constants R1, R2 and C1. (The constants R1, R2 and C1 above are reference values. The resistor R3 should be 50kΩ and Q1 should be 2SC series. The operations of the three cases are described below.

Case 1: When there is no phase difference (PLL locked status)

The S1 signal is low and the S2 signal is high. The UNLOCK signal is low.

• UNLOCK timing

If the phase difference between the SYNC signal input and the programmable counter output signal to the phase detector (PD) increases, it becomes impossible for the VCO to maintain stable oscillation. This status is converted into the UNLOCK signal and output. It is possible to perform analog lock/unlock by connecting an external circuit to this pin.

S1 signal

S2 signal

UNLOCK signal

H

L

H

L

Threshold level of the inverter

S1 signal

S2 signal

UNLOCK signal

H

L

H L

L

Threshold level of the inverter

Case 2: When there is a phase difference, the S1 signal will goes low and high as shown in the figure below.

At this time, the falling edge slew rate of the S2 signal is determined by the current I1 flowing into this open collector. The falling edge slew rate of the S2 signal will therefore be delayed as resistor R1 increases. In addition, since the rising edge slew rate of the S2 signal is determined by the current I2, the rising edge slew rate of the S2 signal will become faster as the resistor R2 decreases. If the integrated S2 signal does not fall below the threshold level of the next inverter, the UNLOCK signal will remain low. This will therefore be judged as locked even if there is a phase difference.

S1 signal

S2 signal

UNLOCK signal

H

L

H L

L

Threshold level of the inverter

Case 3: However, even if the same phase difference as described above is assumed, the decreasing resistor

R1 will increase the current I1 flowing into the open collector. The falling edge slew rate of the S2 signal will therefore become faster. In addition, if resistor R2 is increased, the rising edge slew rate of the S2 signal will become slower. If the integrated S2 signal is under the threshold level of the next inverter, the UNLOCK signal will go from low to high and the PLL will be judged as unlocked.

– 59 –

CXA3516R

The CXA3516R's charge pump is a constant-current output type as shown below.

S1

VCC

To LPF

S2

When a constant-current output charge pump circuit is used inside the PLL, the phase detector (PD) output acts as a current source, and the dimension of its transmittance KPD is A/rad. Also, when considering the VCO input as a voltage, the LPF transmittance dimension must be expressed in ohms (Ω = V/A). Therefore, the PLL transmittance when a constant-current output charge pump circuit is used is as follows.

1/S

KPD

(A/rad)

PD

KVCO

(rad/S/V)

VCOLPF

counter

F (S)

(Ω)

1/S 1/N

+

–

θo

N

ω

0

ω

/N

θ

r

ω

r

The PLL closed loop transmittance is obtained by the following formula.

Here, KPD, F(S) and KVCO are:

KPD: Phase comparator gain (A/rad) F(S): Loop filter transmittance (Ω) KVCO: VCO gain (rad/s/V)

∗1

The reason for the 1/S inside the phase detector is as follows.

θo (t)/N = ∫ω0 (t)/Ndt + θo (t = 0)/N: (a) θo (t = 0) = 0 θo (t)/N = ∫ω0 (t)/Ndt: (b)

Performing Laplace conversion:

θo (S)/N = W0 (S)/N: (c)

1 s

θo/N

θr

KPD · F (S) · KVCO · 1/N · 1/S

1 + KPD · F (S) · KVCO · 1/N · 1/S

=

...

(1)

t

o

t

o

– 60 –

CXA3516R

The loop filter F(S) is described below. The loop filter smoothes the output pulse from the phase detector (PD) and inputs it as the DC component to the VCO. In addition to this, however, the loop filter also functions as an important element in determining the PLL response characteristics. Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3516R's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants.

Current input type active filter

ii

CR

Vo

–Vo

–A –1

The filter transmittance is as follows.

+ Vo = (R + ) · ii

F (S) = ·

= ·

∴τ = RC

Here, assuming A > 1, then:

F (S) =

........................

(2)

Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL:

=

...

(3)

=

.................................................

(4)

ωn =

√

.................................................

(5)

ζ = ωnτ

.....................................................................

(6)

The Bode diagram for formula (2) is as follows.

0

–90

–45deg

log ω

1

τ

log ω

log scale

Gain [dB]Phase [deg]

2ζωnS + ωn

2

S2+ 2ζωnS + ωn

2

1 + SRC

SC

A

1 + A

1 + Sτ

SC

θo/N

θr

· S +

1 + Sτ

SC

A

1 + A

KPD · KVCO · τ

NC

KPD · KVCO

NC

· S +S2+

KPD · KVCO · τ

NC

KPD · KVCO

NC

KPD · KVCO

NC

Vo

A

1

SC

1 2

– 61 –

CXA3516R

Here, ωn and ζ are as follows.

ωn characteristic angular frequency:

The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency: ωn.

ζ damping factor:

This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is determined by the loop gain and the loop filter.

A capacitor C2 is added to the actual loop filter. This added capacitor C2 is used to reduce the R noise, and a value of around 1/10 to 1/1000 of C1 should be selected as necessary.

Current input type active filter with added capacitor C2

ii

C1 R

Vo

–Vo

C2

–A –1

The filter transmittance is as follows.

F (S) =

=

...................

(3)

τ1 = C1 · R

τ2 =

Here, assuming C2 = C1/100, then:

τ2 =

= C1 · R

= τ1

The Bode diagram for formula (3) is as follows.

0

–90

–45deg

log ω

1

τ1

1

τ2

log ω

log scale

Gain [dB]Phase [deg]

1 + C1 · R · S

S ((C1 + C2) + C1 · C2 · R · S)

1 + τ1 · S

S (C1 + C2) (1 + τ2 · S)

C1 · C2 · R

C1 + C2

C1 · C1/100 · R

C1 + C1/100

1

101

1

101

– 62 –

CXA3516R

Next, the various parameters inside an actual CXA3516R are obtained.

The CXA3516R's charge pump output block and the LPF circuit are as follows.

VCC

100µA

to

800µA

100µA step

S1

R1 C1

C2

S2

20k

100

333

CXA3516R

To VCO

100µA

800µA

100µA step

118

119

First, KPD is as follows.

KPD = 100µ/2π or 200µ/2π or 300µ/2π or 400µ/2π or

500µ/2π or 600µ/2π or 700µ/2π or 800µ/2π (A/rad)

Typical KVCO characteristics curves for the CXA3516R's internal VCO are as follows.

200

150

100

50

2

3

VCO DIV = 1/1

VCO input voltage [V]

VCO frequency [MHz]

4

VCO DIV = 1/2

VCO DIV = 1/4

VCO DIV = 1/8

Therefore, KVCO is as follows.

KVCO = 2π · 55 or 2π · 27.5 or 2π · 13.75 or 2π · 6.875 (rad/s/V)

– 63 –

CXA3516R

kHz

MHz

µA

bit2

bit1

bit0

M/(S∗V)

bit1

bit0

µF

kΩ

kHzrad

kHz

MHz

MODE

Resolution

FSYNC

FCLK

KPD × 2π

C.Pump

setting

KVCO

/2π

DIV

1, 2, 4, 8

setting

N

setting

C1 R1

ωn

fn

ζ

VCO oscillation frequency

NTSC NTSC NTSC NTSC

PAL PAL PAL PAL

480p

1080i

720p

PC-98

VGA MAC

VESA SVGA SVGA SVGA SVGA SVGA

MAC XGA XGA XGA MAC

XGA SXGA SXGA SXGA SXGA UXGA

640 × 400 640 × 480 640 × 480 640 × 480 800 × 600 800 × 600 800 × 600 800 × 600 800 × 600

832 × 624 1024 × 768 1024 × 768 1024 × 768 1024 × 768 1024 × 768

1280 × 1024

1600 × 1200

15.73

15.63

31.47

33.75

45.00

24.82

31.47

35.00

37.86

35.16

37.88

46.88

48.08

53.67

49.72

48.36

56.48

60.02

60.24

68.68

46.43

63.98

79.98

91.15

75.00

12.27

18.41

24.55

27.00

14.69

22.03

29.38

27.00

72.00

74.25

21.05

25.18

30.24

31.50

36.00

40.00

49.51

50.00

56.25

57.28

65.00

75.01

78.75

80.00

94.50

78.75

108.00

135.01

156.96

162.00

300 200 300 300 200 300 400 300 500 500 500 200 300 400 400 500 600 300 300 400 400 400 500 600 600 300 600 300 400 600 600

0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1

1 0 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 0 0

0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1

55/8 55/4 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/1 55/2 55/1 55/1 55/1 55/1

1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0

780 1170 1560 1716

940 1410 1880 1728 2288 2200 1650

848

800

864

832 1024 1056 1056 1040 1048 1152 1344 1328 1312 1328 1376 1696 1688 1688 1722 2160

0.33

3.3

2.83

2.67

2.83

2.70

2.98

2.69

4.27

4.35

5.03

3.13

3.95

4.39

4.48

4.51

4.87

4.90

5.64

5.38

4.98

5.60

6.17

6.14

6.03

5.43

5.44

6.28

7.62

6.80

0.45

0.42

0.45

0.43

0.47

0.43

0.68

0.69

0.80

0.50

0.63

0.70

0.71

0.72

0.77

0.78

0.90

0.86

0.79

0.89

0.98

0.96

0.86

0.87

1.00

1.21

1.08

1.54

1.45

1.54

1.47

1.62

1.46

2.32

2.37

2.74

1.71

2.15

2.39

2.44

2.46

2.65

2.67

3.07

2.93

2.71

3.05

3.36

3.34

3.28

2.96

3.42

4.15

3.70

98.18

73.64

98.18

108.00

58.75

88.13

117.50

108.00

144.01

148.50

84.19

100.70

120.96

126.00

144.02

160.01

99.01

100.01

112.49

114.55

129.99

150.01

157.49

160.00

94.50

157.49

108.00

135.01

156.96

162.00

ωn and ζ calculated for various types of computer signals are shown below.

Here, the various parameters are as follows. FSYNC: Input sync frequency, FCLK: Output clock frequency KPD × 2π: Phase comparator gain × 2π (KPD × 2π = 100 or 200 or 300 or 400 or 500 or 600 or 700 or 800) KVCO/2π: VCO gain (when VCO DIV = 1/1, KVCO/2π = 55)

(when VCO DIV = 1/2, KVCO/2π = 55/2) (when VCO DIV = 1/4, KVCO/2π = 55/4) (when VCO DIV = 1/8, KVCO/2π = 55/8)

N: Counter value, C1: Loop filter capacitance value, R1: Loop filter resistance value

• CP setting matrix

Internal VCO oscillation frequency: CP setting value

40MHz to 85MHz: 200µA

85MHz to 110MHz: 300µA 110MHz to 140MHz: 400µA 140MHz to 155MHz: 500µA 155MHz to 165MHz: 600µA

• DIV setting matrix

Output oscillation frequency: DIV setting value

5MHz to 14MHz: 1/8 14MHz to 40MHz: 1/4 40MHz to 80MHz: 1/2 80MHz to 165MHz: 1/1

– 64 –

CXA3516R

CLK Jitter Evaluation Method

The generated CLK is obtained by inputting Hsync to the CXA3516R. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger.

Pulse generator

CXA3516R

ClockHsync signal

ch1

trigger

Digital oscilloscope

Trigger

Enlarge Enlarge

Clock

Tj p-p

Active video

Front porch

Back porch

H sync

Clock

Hsync signal

Tsync = 1/fsync

15 to 25% of Tsync

Computer signal

The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync. Therefore, when the observation point is changed, the CLK jitter at that point is observed.

The figure below shows a typical example of the CLK jitter for the CXA3516R. The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has passed from the rising edge of Hsync.

Jitter amount Tj p-p

Observation points

2/4 · Tsync1/4 · Tsync0 3/4 · Tsync Tsync

– 65 –

CXA3516R

A/D Converter

• Analog input signal

The RGB analog input signal and YCbCr analog input signal are converted to digital signals and output. Be sure to adjust the input dynamic range of the ADC in the pre-stage amplifier block by performing contrast and brightness settings for the analog signal input to the ADC. (See the item on the amplifier for details on the setting procedure.)

• Sampling clock

Although the sampling clock is created by a PLL (internal CLK), it is also possible to externally input a clock to the ADC (external CLK) directly for checking ADC operations. In this case, be sure to make the register settings below in order to input a PECL level clock from the CLKIN (Pin 110) and the XCLKIN (Pin 109).

Register: VCO By-pass

ADC clock

0

External CLK

1

Internal CLK

Note, however, that even if an external CLK is input under the above settings, it is impossible to run the ADC at the input clock frequency unless the PLL's VCO frequency divider is set to 1/1. Running the ADC on an external CLK is done in order to check the operations of the ADC. Normally, it should be run on the internal CLK generated by the PLL.

• Reference voltage

The input dynamic range of the ADC is determined based on the reference voltage from the VRT (Pin 17) and the VRB (Pin 93). Since this reference voltage is created using an internal band gap voltage, there is no need for an external reference voltage circuit. The voltage at the VRT pin is set to a voltage approximately

0.4V lower than the voltage coming from the AVCC

AD3 power pin. Also, the VRB pin is set to a voltage approximately 1.0V lower than that at the VRT pin. Capacitors of 1µF or more should be connected between the AV

CCAD3 power supply pins for these

reference voltage pins (VRT pin and VRB pin). If the value of the capacitor is too low or no capacitor is attached, the reference voltage circuit will cause an oscillation that results in noise or malfunction because the ADC faithfully samples this oscillation. It is impossible to apply an external voltage to a reference voltage pin. Note that it is also impossible to use the voltage generated by a reference voltage pin as an external voltage source.

• Operational mode

The ADC output data of this IC supports five types of operational mode. Each operational mode is set by using a control register.

Straight Data out Mode DMUX Parallel Data out Mode DMUX Interleaved Data out Mode 4:2:2 Data out D2 Mode 4:2:2 Data out special Mode

Register: DATA OUT MODE

D3 D2 D1

0 0 0 0 1

0 0 1 1 1

0 1 0 1 1

For a description of each operational mode, see the next page.

– 66 –

CXA3516R

• Description of the operational modes

(Straight Data out Mode)

An RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog input signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). The sampled analog input signal is output from the port A side of the data output with a 3-clock pipeline delay. Note that output for port B side is turned off at this time and cannot be set to high impedance. The ADC data output is output with a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operational frequency in Straight Data out Mode is 100MHz at the sampling clock frequency. Also, note, when operating in Straight Data out Mode, that the output on the port B side (RB0 to RB7, GB0 to GB7, and BB0 to BB7) is turned off and cannot be set to high impedance. All TTL output are set to high impedance only when this IC is put into power save mode. The following type of interface is possible when this IC is operated in Straight Data out Mode.

The hold time of the post-stage scaling IC using the interface shown above is,

th (min.) = 2.2ns

CXA3516R Scaling IC

CLK

XCLK

1/2CLK

1/2XCLK

99 98 101

100

RA0 to RA7 GA0 to GA7 BA0 to BA7

max.

min.

Td_8

2.2ns (min.) to 3.8ns (max.)

th (min.)

– 67 –

CXA3516R

(DMUX Parallel Data out Mode)

The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each clock cycle, sampled data is divided into pins in port A side and port B side. The data output on the port A side possesses a 3-clock pipeline delay versus the sampling clock, while the data output on the port B side possesses a 2-clock pipeline delay. The output timing is the same for data output from both ports. Data is maintained for two cycles (2T) of the sampling clock. ADC data is output with a propagation delay (Td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2XCLK (Pin 100). An interface of the following type is possible when this IC is run in DMUX Parallel Data out Mode.

CXA3516R Scaling IC

CLK

XCLK

1/2CLK

1/2XCLK

99 98 101

100

RA0 to RA7 GA0 to GA7 BA0 to BA7

RB0 to RB7 GB0 to GB7 BB0 to BB7

ts

max.

min.

th

ts th

T

Td_7

1.3ns (min.) to 2.2ns (max.)

With the interface shown above, the post-stage scaling IC acquire data by using the clock signal output from the 1/2CLK pin of the ADC. In case of this interface, the setup time of the post-stage scaling IC is,

ts (min.) = T – 2.2ns

While the hold time is,

th (min.) = T + 1.3ns

– 68 –

CXA3516R

(DMUX Interleaved Data out Mode)

The RGB analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). At each clock cycle, sampled data is divided into pins in port A and port B. The data output on the port A side possesses a 2-clock pipeline delay versus the sampling clock, while the data output on the port B side also possesses a 2-clock pipeline delay. Although the data output from both ports is maintained for two cycles (2T) of the sampling clock, there is one cycle (T) difference between the output timing for port A side and port B side. Data output on port A side possesses a propagation delay (Td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2XCLK (Pin 100), while data output on port B side possesses a propagation delay (Td_1/2clk to data) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2CLK (Pin 101). An interface of the following type is possible when this IC is run in DMUX Interleaved Data out Mode.

CXA3516R Scaling IC

CLK

XCLK

1/2CLK

1/2XCLK

99 98 101

100

RA0 to RA7 GA0 to GA7 BA0 to BA7

RB0 to RB7 GB0 to GB7 BB0 to BB7

ts

max.

min.

th

ts th

T

max.

min.

∗Td

Td_7

1.3ns (min.) to 2.2ns (max.)

With the interface shown above, port A data is acquired into the post-stage scaling IC by using the clock signal output from the 1/2CLK pin of the ADC, while port B data is acquired by using the clock signal output from the 1/2XCLK pin. In case of this interface, the setup time of the post-stage scaling IC is,

ts (min.) = T – 2.2ns

While the hold time is,

th (min.) = T + 1.3ns

– 69 –

CXA3516R

(4:2:2 Data out D2 Mode)

The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog signal input to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). In 4:2:2 Data out D2 Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to the data output ports GA0 to GA7. The Cb and Cr signals are all simultaneously A/D converted at a half sampling rate compared with the Y signal, then multiplexed within the IC, and output to the data output ports BA0 to BA7 in the order U (Cb) and V (Cr). When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the signal. See the operational description of SYNCSEP for details. Data output of ADC possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operating frequency in 4:2:2 Data out D2 Mode is 100MHz as the sampling clock frequency. Although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the IC operates in 4:2:2 Data out D2 Mode, they cannot be set to high impedance. All TTL output is set to high impedance when this IC is put into power save mode. An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode.

The hold time of the post-stage scaling IC using the interface shown above is,

th (min.) = 2.2ns

CXA3516R Scaling IC

CLK

XCLK

1/2CLK

1/2XCLK

99 98 101

100

GA0 to GA7 BA0 to BA7

max.

min.

Td_8

2.2ns (min.) to 3.8ns (max.)

– 70 –

CXA3516R

(4:2:2 Data out special Mode)

The YCbCr analog input signal AC coupled is optimized by using a 3-ch AMP and the signal is input to the ADC. The analog input signal to the ADC is sampled by using a clock generated by the PLL. The identical signal with the sampling clock for analog input signal is output from the CLK (Pin 99). In 4:2:2 Data out special Mode, the only Y signal is A/D converted just as in Straight Data out Mode and output to the data output ports GA0 to GA7. The Cb and Cr signals are A/D converted at every other sampling at a half sampling rate of the Y signal, then multiplexed within the IC, and output to the data output ports BA0 to BA7 in the order U (Cb) and V (Cr). When the SYNC ON Y signal is input, it is necessary to separate out the SYNC signal superimposed on the signal. See the operational description of SYNCSEP for details. ADC data output possesses a propagation delay (Td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the CLK pin. The operating frequency in 4:2:2 Data out special Mode is 100MHz as the sampling clock frequency. In addition, although RA0 to RA7, RB0 to RB7, GB0 to GB7, and BB0 to BB7 are all put into output off mode when the IC operates in 4:2:2 Data out Special Mode, they cannot be set to high impedance. All TTL output is set to high impedance when this IC is put into power save mode. An interface of the following type is possible when this IC is run in 4:2:2 Data out D2 Mode.

The hold time of the post-stage scaling IC using the interface shown above is,

th (min.) = 2.2ns

CXA3516R Scaling IC

CLK

XCLK

1/2CLK

1/2XCLK

99 98 101

100

GA0 to GA7 BA0 to BA7

max.

min.

Td_8

2.2ns (min.) to 3.8ns (max.)

– 71 –

CXA3516R

• EVEN/ODD function

When a toggle signal created by dividing the Vsync signal in half is input to the EVEN/ODD (Pin 108), the ADC sampling clock is inverted every Vsync signal. This function can be used to configure a single frame screen from two fields by AD converting an RGB analog input signal that requires high speed and high resolution, such as a UXGA 60Hz (162MHz) or more signal, at half the frequency of the original ADC sampling rate. There are no particular control register settings when using the EVEN/ODD function. The sampling clock is inverted based on the polarity of the signal input to the EVEN/ODD pin. Be sure to input signal to the EVEN/ODD pin at TTL level.

EVEN/ODD pin

Operational mode

L

EVEN

H

ODD

Example of Using the EVEN/ODD Function

2 4 61 3 5

a b c d e

f g h

i

j k

l

1 3

EVEN field ODD field

EVEN/ODD frame

5

a b

c d e

f g h

i

j

k

l

2 4 6

a b c d e f g h

i j

k

l

1

3

5

2

4

6

Analog input signal

Hsync

Sampling CLK

Vsync

Toggle signal (EVEN/ODD pin)

– 72 –

CXA3516R

TTL Output High Level Setting

All the TTL output pins can be set to high level by the control register. All the TTL output pins are set simultaneously. The TTL output pins are as follows.

RA7 to RA0, RB7 to RB0, GA7 to GA0, GB7 to GB0, BA7 to BA0, BB7 to BB0, SEROUT, SOGOUT, Delay Sync Output, 1/2CLK, 1/2XCLK, CLK and XCLK

Register: TTLOUT CLP

High level (typ.)

00

2.2V

01

2.45V

10

2.7V

11

2.95V

The TTL output can be input directly to a 3V power supply IC without level conversion. Set high level in accordance with the supply voltage.

Power Save

1) Power save for all functions

All functions of the chip can be stopped to save power by the XPOWER SAVE (Pin 6). The control register is also set to power save mode at this time.

XPOWER SAVE pin

Operating status

L

Power save

H

Power on

Register ADC Power Save AMP Power Save PLL Power Save SYNC SEP Power Save

0 Power on Power on Power on Power on

1 Power save Power save Power save Power save

The pin input level is TTL level.

2) Power save every block by using the control register

The blocks except the registers can also be set to power save mode by the control register. Selects according to using state.

– 73 –

CXA3516R

TTL Output Mode during Power Save Mode

All TTL output pins are set to high impedance when the IC is put into power save mode. Since this IC supports power on reset, AMP, ADC, PLL, and SYNCSEP are set to power save mode when power is turned on and all TTL output pins are set to high impedance. However, note that the TTL output pins don't change into high impedance, when control register are used to set each TTL output disable mode separately. Even though there are also modes in which data output ports are set to output off mode based on the ADC operational mode, it cannot be set to high impedance.

ADC Data Output Modes

Other TTL Output Pin Modes

RA7 to 0 RB7 to 0 GA7 to 0 GB7 to 0 BA7 to 0 BB7 to 0

XPOWER SAVE mode

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

ADC Power Save mode

Straight mode

DMUX Parallel mode

DMUX Interleaved mode

YUV 4:2:2 D2 mode

YUV 4:2:2 Special

mode Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DATA

—

∗

DATA

—

∗

DATA

—

∗

DATA DATA DATA DATA DATA DATA

—

∗

—

∗

DATA

—

∗

DATA

—

∗

—

∗

—

∗

DATA

—

∗

DATA

—

∗

CLK XCLK 1/2CLK 1/2XCLK DSYNC/

DIVOUT SOGOUT SEROUT UNLOCK

XPOWER SAVE mode

Hi-Z Hi-Z Hi-Z Hi-Z

Hi-Z Hi-Z

PLL Power Save mode

CLK Disable

XCLK Disable

1/2CLK Disable

1/2XCLK Disable

SOGOUT Disable

Hi-Z Hi-Z Hi-Z Hi-Z

Hi-Z Hi-Z

—

∗

Signal Signal Signal

Signal Signal

Signal

—

∗

Signal Signal

—

∗

Signal Signal Signal

Signal Signal

Signal Signal Signal

—

∗

Signal Signal

Signal Signal Signal Signal

—

∗

Signal Signal Signal

DSYNC Disable

Signal Signal Signal Signal

Signal

—

∗

Signal Signal

Signal Signal Signal Signal

Signal Signal

—

∗

Signal

SEROUT Disable

Signal Signal Signal Signal

Signal Signal

Signal

—

∗

UNLOCK Disable

∗

A dash (–) indicates output off status that cannot be set to high impedance.

– 74 –

CXA3516R

Supply Current

The default value for the current consumption and the control register-based power save current (ICC5PS, ICC3PS), and power save current (ICC5XPS, ICC3XPS) when the XPOWER SAVE function is used, are indicated to each block as follows. (The current consumption values given here are the typical values for when the IC is run at a clock frequency of 80MSPS.)

Block

Register AMP (SYNCSEP)

PLL

ADC

DVCCREG AVCCAMP

∗

AVCCVCO + AVCCIR DVCCPLL + DVCCPLLTTL AVCCADREF DVCCAD + DVCCADTTL AVCCAD3 + DVCCAD3

5V (D) 5V (A) 5V (A) 5V (D) 5V (A) 5V (D)

3.3V (A)

17.2mA

80.0mA

16.0mA

41.4mA

6.8mA

73.2mA 180mA

17.2mA

0.7mA 0mA

2.0mA

0.4mA

6.0mA

3.0mA

1.2mA

0.7mA 0mA

1.0mA

0.4mA

6.0mA

3.0mA

Supply pin names

Supply

voltage

Current

consumption (typ.)

Register PS current

consumption

XPS current

consumption

AVCCAMP∗= AVCCAMPR + AVCCAMPG + AVCCAMPB

– 75 –

CXA3516R

PLL Timing Chart (Td1 = 3CLK)

Analog input

SYNCIN1 (Pin 111)

SYNCIN2 (Pin 112)

DSYNC signal (Pin 103)

(DSYNC By-pass = 1)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 0)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 1)

1/2CLK (Pin 101)

(N = ODD)

ADC Data Output

(Straight Mode)

1/2CLK (Pin 101)

(N = EVEN)

RESET

(Internal Signal)

N – 2

0 1 2 3 4 5 6CLK

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N – 5

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

Td_2 = 1/32 to 64/32CLK

Td_1 = 3CLK

Td_5 = 5CLK

1, 2, 4, 8CLK

Td_5 = 4CLK

Td_4

(typ. 1.0ns)

Td_3

(typ. 7ns)

Td_6

(typ. 1.2ns)

Td_6

(typ. 1.2ns)

CLK (Pin 99)

1CLK

– 76 –

CXA3516R

PLL Timing Chart (Td1 = 4CLK)

Analog input

SYNCIN1 (Pin 111)

SYNCIN2 (Pin 112)

DSYNC signal (Pin 103)

(DSYNC By-pass = 1)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 0)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 1)

1/2CLK (Pin 101)

(N = ODD)

ADC Data Output

(Straight Mode)

1/2CLK (Pin 101)

(N = EVEN)

RESET

(Internal Signal)

CLK (Pin 99)

N – 2

0 1 2 3 4 5 6CLK

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N – 5

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

Td_2 = 1/32 to 64/32CLK

Td_1 = 4CLK

Td_5 = 5CLK

1, 2, 4, 8CLK

Td_5 = 4CLK

Td_4

(typ. 1.0ns)

Td_3

(typ. 7ns)

Td_6

(typ. 1.2ns)

Td_6

(typ. 1.2ns)

1CLK

– 77 –

CXA3516R

PLL Timing Chart (Td1 = 5CLK)

Analog input

SYNCIN1 (Pin 111)

SYNCIN2 (Pin 112)

DSYNC signal (Pin 103)

(DSYNC By-pass = 1)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 0)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 1)

1/2CLK (Pin 101)

(N = ODD)

ADC Data Output

(Straight Mode)

1/2CLK (Pin 101)

(N = EVEN)

RESET

(Internal Signal)

CLK (Pin 99)

N – 2

0 1 2 3 4 5 6CLK

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N – 5

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

Td_2 = 1/32 to 64/32CLK

Td_1 = 5CLK

Td_5 = 5CLK

1, 2, 4, 8CLK

Td_5 = 4CLK

Td_4

(typ. 1.0ns)

Td_3

(typ. 7ns)

Td_6

(typ. 1.2ns)

Td_6

(typ. 1.2ns)

1CLK

– 78 –

CXA3516R

PLL Timing Chart (Td1 = 6CLK)

Analog input

SYNCIN1 (Pin 111)

SYNCIN2 (Pin 112)

DSYNC signal (Pin 103)

(DSYNC By-pass = 1)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 0)

DIVOUT signal (Pin 103)

(DSYNC By-pass = 0,

DIVOUT Delay = 1)

1/2CLK (Pin 101)

(N = ODD)

ADC Data Output

(Straight Mode)

1/2CLK (Pin 101)

(N = EVEN)

RESET

(Internal Signal)

CLK (Pin 99)

N – 2

0 1 2 3 4 5 6CLK

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N – 5

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

Td_2 = 1/32 to 64/32CLK

Td_1 = 6CLK

Td_5 = 5CLK

1, 2, 4, 8CLK

Td_5 = 4CLK

Td_4

(typ. 1.0ns)

Td_3

(typ. 7ns)

Td_6

(typ. 1.2ns)

Td_6

(typ. 1.2ns)

1CLK

– 79 –

CXA3516R

ADC Timing Diagram

0.9ns to 1.2ns to 1.6ns

Td_6

min. typ. max.

2.2ns to 2.8ns to 3.8ns

Td_8

min. typ. max.

T

R_CLK 0.8ns 1.4ns 2.3ns

T

F_CLK 1.0ns 1.5ns 2.8ns

min. typ. max. TR_CLK 0.8ns 1.4ns 2.3ns TF_CLK 1.0ns 1.5ns 2.8ns

min. typ. max. TR_DATA 0.9ns 1.2ns 2.0ns TF_DATA 0.9ns 1.2ns 2.0ns

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

Clock

CLK

XCLK

1/2CLK

1/2XCLK

1/2 clock

Data

The timing diagram above supposes that one data cycle represents the same amount of time as one clock cycle concerning the three modes as follows: Straight Data out Mode, 4:2:2 Data out D2 Mode, and 4:2:2 Data out special Mode.

– 80 –

CXA3516R

ADC Timing Diagram

0.9ns to 1.2ns to 1.6ns

Td_6

min. typ. max.

2.3ns to 2.6ns to 3.2ns

Td_7

min. typ. max.

T

R_CLK 0.8ns 1.4ns 2.3ns

TF_CLK 1.0ns 1.5ns 2.8ns

min. typ. max. TR_CLK 0.8ns 1.4ns 2.3ns TF_CLK 1.0ns 1.5ns 2.8ns

min. typ. max. TR_DATA 0.9ns 1.2ns 2.0ns TF_DATA 0.9ns 1.2ns 2.0ns

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

Clock

CLK

XCLK

1/2CLK

1/2XCLK

1/2 clock

Data

T

T – 2.2ns

min.

T + 1.3ns

min.

The timing diagram above supposes DMUX Parallel Data out Mode. It is possible for the post-stage scaling IC to acquire data by using a 1/2 clock. The output delay time in this mode is the same as that in DMUX Interleaved Data out Mode.

– 81 –

CXA3516R

ADC Timing Diagram (Straight Data out Mode)

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N1

N0

N2

N3

N4

N5

N6

N7

N8

N9

N10

N7N6N5N4N3N2

– 82 –

CXA3516R

ADC Timing Diagram (DMUX Parallel Data out Mode)

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N1

N0

N2

N3

N4

N5

N6

N7

N8

N9

N10

N6N4N2

N7N5N3

– 83 –

CXA3516R

ADC Timing Diagram (DMUX Interleaved Data out Mode)

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N1

N0

N2

N3

N4

N5

N6

N7

N8

N9

N10

N7N5N3

N6N4N2

– 84 –

CXA3516R

ADC Timing Diagram (4:2:2 Data out D2 Mode)

Analog input

RIN1 (139 pin) RIN2 (141 pin)

GIN1 (124 pin) GIN2 (126 pin)

BIN1 (133 pin) BIN2 (136 pin)

Data out

GA7 to GA0

BA7 to BA0

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

Y1

Y0

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Cb1

Cb3

Cb5

Cb7

Cb9

Cr1

Cr3

Cr5

Cr7

Cr9

Y8Y6Y4Y2 Y3 Y5 Y7

Cb3 (U3) Cr3 (V3) Cb5 (U5) Cr5 (V5) Cb7 (U7) Cr7 (V7)

– 85 –

CXA3516R

ADC Timing Diagram (4:2:2 Data out special Mode)

Analog input

RIN1 (139 pin) RIN2 (141 pin)

GIN1 (124 pin) GIN2 (126 pin)

BIN1 (133 pin) BIN2 (136 pin)

Data out

GA7 to GA0

BA7 to BA0

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

Y1

Y0

Y2

Cr2

Y3

Y4

Y5

Y6

Y7

Y8

Cr4

Cr6

Cr8

Y9

Y10

Cr10

Cb1

Cb3

Cb5

Cb7

Cb9

Y8Y6Y4Y2 Y3 Y5 Y7

Cb3 (U3)Cr2 (V3) Cr4 (V4) Cb5 (U5) Cr6 (V6) Cb7 (U7) Cr8 (V8)

– 86 –

CXA3516R

ADC Timing Diagram (Straight Data out Mode, EVEN/ODD)

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N0

N4

N5

N3

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N2

N1

N14N10N6N4 N8 N12

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N0

N4

N5

N3

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N2

N1

N11N7N5 N9 N13

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

EVEN

ODD

– 87 –

CXA3516R

ADC Timing Diagram (DMUX Parallel Data out Mode, EVEN/ODD)

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N0

N4

N5

N3

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N2

N1

N8N4 N12

N10N6 N14

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N0

N4

N5

N3

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N2

N1

N5 N9 N13

N7 N11 N15

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

EVEN

ODD

– 88 –

CXA3516R

ADC Timing Diagram (DMUX Interleaved Data out Mode, EVEN/ODD)

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N0

N4

N5

N3

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N2

N1

N10N6 N14

N8N4 N12

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

Analog input

RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin)

SYNCIN1 (111 pin) SYNCIN2 (112 pin)

DSYNC (103 pin)

CLK (99 pin)

XCLK (98 pin)

1/2CLK (101 pin)

1/2XCLK (100 pin)

N0

N4

N5

N3

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N2

N1

N7 N11 N15

N5 N9 N13

Data out

RA7 to RA0 GA7 to GA0 BA7 to BA0

RB7 to RB0 GB7 to GB0 BB7 to BB0

EVEN

ODD

– 89 –

CXA3516R

0

0.5

1.0

1.5

Gain [dB]

2.0

2.5

50 100 150

Main Contrast register

Main Contrast Control Characteristics

200 250

Sub contrast = 128 R, G, B OUT

0

–30

–20

–10

0

Gain adjustment ratio [%]

10

20

30

50 100 150

Sub Contrast register

Sub Contrast Control Characteristics

200 250

Main contrast = 128

R, G, B OUT

0

–80

–60

–40

–20

0

20

AD output conversion level (LSB)

40

60

80

50 100 150

Brightness register

Brightness Level Control Characteristics

200 250 0

100

105

110

115

125 120

AD output conversion level (LSB)

135 130

145 140

150

10 20

30 40

CbCr offset register

CbCr Clamp Level Control Characteristics

50 60

0

50

100

150

VTH [mV]

200

250

2

46810

V

TH register

SYNC SEP VTH Control Characteristics

12 14 0

0

10

20

40

30

VHYS [mV]

50

70

60

80

12

V

HYS register

SYNC SEP VHYS Control Characteristics

3

– 90 –

CXA3516R

0.1

–5

–3

–1

1

3

5

Gain [dB]

7

9

110

Frequency [MHz]

Frequency Response

100 300

Main contrast = 128 Sub contrast = 128 R, G, B OUT

–10

–8

–6

–4

–2

0

2

Gain fluctuation ratio [%]

4

6

8

10

0 10 20 30 40 50

Ta – Ambient temperature [°C]

Gain Temperature Characteristics

60 70

–10 0 10 20 30 40 50 60 70

4.75

–2.0

–1.5

–1.0

–0.5

0

0.5

Gain fluctuation ratio [%]

1.0

1.5

2.0

5

Supply voltage [V]

Gain Supply Voltage Characteristics

5.25

4.75 5 5.25

–0.3

–0.2

–0.1

0.1 0

AD output fluctuation (LSB)

0.3

0.2

0.5

0.4

0.6

–0.6

–0.4

0

–0.2

0.2

0.4

0.6

Ta – Ambient temperature [°C]

Brightness Level Temperature Characteristics

–1.5

–1.0

–0.5

0

0.5

AD output level fluctuation (LSB)

1.0

1.5

Supply voltage [V]

Brightness Supply Voltage Characteristics

AD output level fluctuation (LSB)

CbCr Clamp Level Temperature Characteristics

Main contrast = 128 Sub contrast = 128 R, G, B OUT

Brightness = 128

–10 0 10 20 30 40 50 60 70

Ta – Ambient temperature [°C]

Main contrast = 128 Sub contrast = 128 R, G, B OUT

Brightness = 128

CbCr offset register = 32

– 91 –

CXA3516R

1.5

0

50

100

150

Output frequency [MHz]

200

250

2.0 2.5 3.0 3.5 4.0 4.5 VCO control voltage [V]

KVCO Characteristics

5.0

0

8

16

24

32

40

48

Fine delay [1/32CLK]

56

72 64

80

32

40 48 568 16 24

Fine delay register control [1/32CLK]

Fine Delay vs. Control

64

DIV = 1/1 DIV = 1/2 DIV = 1/4 DIV = 1/8

–0.6

–0.4

0

–0.2

0.2

0.4

0.6

AD output level fluctuation (LSB)

CbCr Clamp Level Supply Voltage Characteristics

4.75 5 5.25 Supply voltage [V]

CbCr offset register = 32

NTSC, DIV = 1/8, CP = 010, 100 VGA, DIV = 1/4, CP = 010, 011 SVGA, DIV = 1/4, 1/2, CP = 010, 100, 101 XGA, DIV = 1/2, CP = 011, 100 SXGA, DIV = 1/1, CP = 010, 011, 100 UXGA, DIV = 1/1, CP = 101

02040 60 80 100 120 140 160 180

0

0.4

0.2

0.6

1.0

0.8

Jitter peak-peak [ns]

1.4

1.2

1.8

1.6

2.0

Output frequency [MHz]

Jitter Peak-Peak vs. Output Frequency

– 92 –

CXA3516R

3.0

160

180

Current consumption [mA]

200

3.3

5.0 5.254.75

Supply voltage [V]

Ta – Ambient temperature [°C]

Current Consumption vs. Supply Voltage Fluctuation

3.6

V

CC3

VCC5

–10

160

180

Current consumption [mA]

200

0 25 50

Current Consumption vs. Temperature Characteristics

75

ICC5 ICC3

CLK = DC

ICC5 ICC3

CLK = DC

160

180

200

220

240

260

Current consumption [mA]

FCLK – Clock frequency [MHz]

Current Consumption vs. Frequency Response

100 120 16020 14040 60 80

ICC5 ICC3

Operational mode: DMUX parallel Data out Load capacitance: CL = 10pF

– 93 –

CXA3516R

Application Circuit (I

2

C (High) mode)

0.1µ

75

0.1µ

75

0.1µ

75

0.1µ

75

0.1µ

75

0.1µ

G1

G2

B1

R1

R2

B2

1µ

100p

C1

0.33µ

R1

3.3k

3k

C2

330p

75

0.1µ

4.7k

AVCC5V

DV

CC5V

3.3V

DGND

AGND

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

7374757677

78 79 80 81 828384858687

88 89 90 91 92 93 949596979899

100101102103104105106107108

133

134

135

136

137

138

139

140

141

1 2 3 4

121

122

123

124

125

126

127

128

129

130

131

132

142

143

144

110

109

111

112

113

114

115

116

117

118

119

120

5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 3611 21 31

B/CbOUT

ADDRESS

R/CrOUT

NC

XPOWER SAVE

DGNDREG

DVCCREG

SDA

SCL

XSENABLE

SEROUT

3WIRE/I

2

C

DPGND

AVCCADREF

AVCCAD3

VRT

DVCCAD3

DVCCADTTL

DGNDADTTL

RA0

RA1

DGNDAD3

RA2

RA3

RA4

RA5

RA6

AGNDAD3

DGNDAD3

RA7

DV

CCADTTL

DGNDADTTL

RB0

RB1

RB2

GA4

GA3

GA2

GA1

GA0

DGNDADTTL

DGNDAD3

DVCCADTTL

BB7

BB6

BB5

BB4

BB3

GNDAD3

BB2

BB1

BB0

DGNDADTTL

DVCCADTTL

BA7

BA6

BA5

DGNDAD3

BA4

BA3

BA2

BA1

BA0

DGNDADTTL

DGNDAD3

DVCCADTTL

RB7

RB6

RB5

RB4

RB3

EVEN/ODD

XTLOAD

HOLD

SOGOUT

UNLOCK

DSYNC/DIVOUT

DPGND

1/2CLK

1/2XCLK

CLK

XCLK

DGNDPLLTTL

DV

CCPLLTTL

AGNDADREF

AVCCAD3

VRB

DVCCAD3

DV

CCAD

DV

CCADTTL

DGNDADTTL

GB7

GB6

DGNDAD3

GB5

GB4

GB3

GB2

GB1

AGNDAD3

DGNDAD3

GB0

DGNDADTTL

DV

CCADTTL

GA7

GA6

GA5

XCLKIN

CLKIN

SYNCIN1

SYNCIN2

CLPIN

DVCCPLL

DGNDPLL

AVCCVCO

AGNDVCO

RC1

RC2

AVCCIR

IREF

DPGND

AGNDIR

G/YIN1

AVCCAMPG

G/YIN2

AGNDAMPG

G/YCLP

B/CbCLP

R/CrCLP

DPGND

SOGIN1

B/CbIN1

AVCCAMPB

SOGIN2

B/CbIN2

AGNDAMPB

DPGND

R/CrIN1

AVCCAMPR

R/CrIN2

AGNDAMPR

G/YOUT

DACTESTOUT

This is an application circuit which

controls this IC with I

2

C (High)

mode and supports RGB2 channel

input.

ADC operational mode supports

DMUX Parallel mode or DMUX

Interleaved mode.

(I

2

C bus slave address is

10011000.)

Application circuits shown are

typical examples illustrating the

operation of the devices. Sony

cannot assume responsibility for

any problems arising out of the use

of these circuits or for any

infringement of third party patent

and other right due to same.

– 94 –

CXA3516R

Application Circuit (3-wire bus mode)

This is an application circuit which

controls this IC with 3-wire bus

mode and operates ADC with

4:2:2 Data out D2 mode with

respect to YcbCr analog input

signal.

820

0.1µ

75

0.1µ

75

0.1µ

Y

Cb

Cr

1µ

100p

C1

0.33µ

R1

3.3k

3k

C2

330p

75

0.1µ

4.7k

820

TP-RTP-B

TP-G

820

4.7k

AVCC5V

DV

CC5V

3.3V

DGND

AGND

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

7374757677

78 79 80 81 828384

85 8687

88 89 90 91 92 93 949596979899

100101102103104105106107108

133

134

135

136

137

138

139

140

141

1 2 3 4

121

122

123

124

125

126

127

128

129

130

131

132

142

143

144

110

109

111

112

113

114

115

116

117

118

119

120

5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 3611 21 31

B/CbOUT

ADDRESS

R/CrOUT

NC

XPOWER SAVE

DGNDREG

DVCCREG

SDA

SCL

XSENABLE

SEROUT

3WIRE/I

2

C

DPGND

AVCCADREF

AVCCAD3

VRT

DVCCAD3

DVCCADTTL

DGNDADTTL

RA0

RA1

DGNDAD3

RA2

RA3

RA4

RA5

RA6

AGNDAD3

DGNDAD3

RA7

DVCCADTTL

DGNDADTTL

RB0

RB1

RB2

GA4

GA3

GA2

GA1

GA0

DGNDADTTL

DGNDAD3

DVCCADTTL

BB7

BB6

BB5

BB4

BB3

GNDAD3

BB2

BB1

BB0

DGNDADTTL

DVCCADTTL

BA7

BA6

BA5

DGNDAD3

BA4

BA3

BA2

BA1

BA0

DGNDADTTL

DGNDAD3

DVCCADTTL

RB7

RB6

RB5

RB4

RB3

EVEN/ODD

XTLOAD

HOLD

SOGOUT

UNLOCK

DSYNC/DIVOUT

DPGND

1/2CLK

1/2XCLK

CLK

XCLK

DGNDPLLTTL

DVCCPLLTTL

AGNDADREF

AVCCAD3

VRB

DVCCAD3

DVCCAD

DVCCADTTL

DGNDADTTL

GB7

GB6

DGNDAD3

GB5

GB4

GB3

GB2

GB1

AGNDAD3

DGNDAD3

GB0

DGNDADTTL

DVCCADTTL

GA7

GA6

GA5

XCLKIN

CLKIN

SYNCIN1

SYNCIN2

CLPIN

DVCCPLL

DGNDPLL

AVCCVCO

AGNDVCO

RC1

RC2

AVCCIR

IREF

DPGND

AGNDIR

G/YIN1

AVCCAMPG

G/YIN2

AGNDAMPG

G/YCLP

B/CbCLP

R/CrCLP

DPGND

SOGIN1

B/CbIN1

AVCCAMPB

SOGIN2

B/CbIN2

AGNDAMPB

DPGND

R/CrIN1

AVCCAMPR

R/CrIN2

AGNDAMPR

G/YOUT

DACTESTOUT

Application circuits shown are

typical examples illustrating the

operation of the devices. Sony

cannot assume responsibility for

any problems arising out of the use

of these circuits or for any

infringement of third party patent

and other right due to same.

– 95 –

CXA3516R

Notes on Operation

• On the PC board, prepare a solid ground pattern having as large an area as possible, and placing the IC in the center, divide this area into an analog region and digital region.

• The loop filter area of the PLL block plays an important role in terms of performance. It is therefore located as close as possible to the IC pins and the periphery is guarded with AGND. Also, be sure to use capacitors and resistors for the loop filter that should be temperature compensated and do not change the values.

• Be sure to use a metal film resistor for the resistor connected to IREF (Pin 121).

• The wiring for SYNCIN1 (Pin 111) and SYNCIN2 (Pin 112) should be as short as possible and each needs to

be shielded by ground.

• Use a 0.1µF ceramic chip capacitor for the bypass capacitor attached between the power supply and ground. The capacitor should be attached to the pin as close as possible.

• Use a 1µF ceramic chip capacitor for the capacitor attached to the VRT (Pin 17) and the VRB (Pin 93) and connect to the AVCCAD3 (Pin 16 and Pin 94) as close as possible.

• Equalize and shorten the lines of RGB analog input signals, if possible. Each line needs to be shielded by ground. (This is the same for the R/CrCLP, G/YCLP, and B/CbCLP pins.)

• A 0.1µF capacitor is recommended for attachment to the RGB analog input pins. The less the capacitance becomes, the more the sag by leak current becomes. The more the capacitance becomes, the more start up time takes in case of putting power souce into the IC. (This is the same for the R/CrCLP, G/YCLP, and B/CbCLP pins.)

• Design boards so that the wiring for the R/CrIN, G/YIN, and B/CbIN and R/CrOUT, G/YOUT, B/CbOUT pins is as separated as possible.

• Use a pattern width that takes characteristic impedance into account for signal wires terminated at 75Ω.

• There are no particular restrictions on the power-on sequence.

• Although there are AV

CCAD3 and DVCCAD3 as 3.3V power supply, use the same 3.3V analog power supply

to each on the board.

• AGNDAD3 and DGNDAD3 are the ground for AV

CCAD3 and DVCCAD3, respectively. Use the same ground

for AGNDAD3 and DGNDAD3. Although AGND is the ground recommended for AGNDAD3 and DGNDAD3, there are no problems in terms of operation even if connected to DGND. (The special evaluation board in the Application Circuit is connected to DGND.)

• Although 5V power supply is divided into both analog and digital power supply lines, be sure to wire boards so that no potential difference arises between these power supplies.

• Load capacitance of the data output wires causes the change for the worse of slew rate and noise. Be sure to use short layouts with the finest wires possible.

• Put this IC into power save mode when making a connection between data output and another IC. (High impedance cannot be set when pins are disabled separately.)

– 96 –

CXA3516R

CXA3516R Evaluation Board

Overview

The CXA3516R Evaluation Board is a special board designed for the easy evaluation of the CXA3516R developed for the LCD projector and monitor so that performance can be maximized. The DSUB 15-pin connector is used as the input connector that allows the direct input of a video signal from a PC. The input video signal is A/D converted by the CXA3516R and a pin for monitoring is designed onto the board so that output data can be checked directly.

The 10-bit high speed D/A converters are built onto the board so that the performance of the IC can be easily checked. Picture quality can be easily evaluated by using a CRT monitor since the D/A-converted video signal is output from the DSUB 15-pin connector for output in addition to the DSYNC output of the CXA3516R.

Features

• Single +5V power supply (with built-in 3.3V regulator)

• Allows two-line video signal input

• Data output port is also used as output data monitoring pin

• CXA3516R output is D/A converted and is easily monitored by a CRT

• Supports 2 types of control registers (3-wire and I2C)

Operating Conditions

• Supply voltage: +5V (typ.)

• Current consumption: 830mA (typ.)

• Input signal: Separated sync video signal

– 97 –

CXA3516R

CXA3516R EVB Block Diagram

10µF

0.1µF

Vsync signal

select

Video signal

output

Hsync output

Vsync output

Video signal 2

Hsync signal 2

Vsync signal 2

Video signal 1

Hsync signal 1

Vsync signal 1

R, G, B

analog input signal

R, G, B

analog input signal

R, G, B

analog output signal

R, G, B

digital output data

Control signal

×3

CXA3197R

Control register pins

CON5

3Wire I

2

C

CON4

Power supply pins

Output data monitoring pins

data output ports

Video In1

CON1

Video In2

Video signal

input pins

CON2

Video OUT

CON3

Video signal

output pins

SOGOUTCLPIN

SW1

Power save

SW2

3WIRE/I

2

C

SW3

I/O logic

CXA3516R

CXA2016P

Clamp pulse generation

5V 0V

DAC

– 98 –

CXA3516R

Using the CXA3516R Evaluation Board

The CXA3516R Evaluation Board can be used to easily evaluate just by connecting a power supply, video signals, and control register signals. The procedure is described below.

1. Connect the power supply to the power connection pin. (GND/+5V) Do not apply power supply in this state.

2. Check the direction of SW1. SW1 is the power save control switch. The CXA3516R is put into power save mode when SW1 is set to the rear position (↑). Set SW1 to the forward (↓) position when using the CXA3516R. SW1 is connected to the XPOWER SAVE pin.

3. Connect the special control register signal cable. Connect the cable to CON4 when using I2C control. Set SW2 and SW3 to the forward (↓) position. While, connect the cable to CON5 when using 3-wire control. Set SW2 and SW3 to the rear (↑) position. In addition, check that the short pin (I2C) is in the "00" position in case of using I2C control.

4. Input the RGB analog signals from the CON1 pin (Video In 1). XGA60 is recommended as the initial signal because the control program default value is set for the XGA60.

XGA60: Vsync 60Hz

Hsync: Video signal for 48kHz N = 1344

5. The RGB analog signal for simple picture quality evaluations is output from the CON3 pin (Video Out). Be sure to connect the CON3 pin to a CRT monitor that can process a signal of XGA60 or more.

6. Turn on the power. Check a current to be about 360mA flows through the 5V power supply. If there is much more current than this, immediately turn off the power and check that there are no misconnections.

7. Run the control program. Click on "re-load" at the bottom right of the control program screen, and check a current to be about 830mA flows through the 5V power supply. If everything works normally, an processed image for picture quality evaluation appears on the CRT monitor. Reconfirm the above items from the beginning if the processed image does not appear.

– 99 –

CXA3516R

3-wire Control Program Installation and Startup Method

[Operating Environment]

Windows95 or Windows98

[Program Installation and Startup]

The installation program is configured from the following four files and stored in two floppy disks.

setup.exe, A3506_1.cab, A3506_2.cab, and Setup.lst

1. Copy the four files from the floppy disk onto the PC.

2. Click setup.exe. The installer will start. Follow all on-screen instructions.

3. Once installation complete, a folder titled "Project1" will be created in the Program files folder.

4. The following control window will open when the A3506.exe file starts.

Use this window to make board settings in response to the printer port address of the PC. Be sure to set the address for the PC from the pull-down menu port at the top-left of the control screen. There are two types of addresses: 378 and 3BC.

– 100 –

CXA3516R

I2C Control Program Installation and Startup Method

[Operating Environment]

Windows95 or Windows98

[Program Installation and Startup]

The installation program consists of the following four files and is stored in two floppy disks.

setup.exe, A3506_1.cab, A3506_2.cab, Setup.lst

1. Copy these four files from the floppy disk onto the PC.

2. Click setup.exe. The installer will start. Follow all on-screen instructions.

3. Once installation complete, a folder titled "Project1" will be created in the Program files folder.

4. The following control window will open when the A3506.exe file starts.

Use this window to make board settings in response to the printer port address of the PC. Be sure to set the address for the PC from the pull-down menu port at the top-left of the control screen. There are two types of addresses: 378 and 3BC.