Page 1
CCD Camera Timing Generator
Description
The CXD1257AR generates the timing pulses
required by the CCD image sensors as well as signal
processing circuits.
Features
• NTSC and PAL compatible
• Electronic shutter function
• H-driver
• Compatible with digital and analog camera systems
• Standby function
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX026CKA, ICX027CKA
ICX054AK, ICX055AK
ICX056AK
CXD1257AR
64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD Vss – 0.5 to +7.0 V
• Input voltage VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDD 5.0 ± 0.25 V
• Operating temperature Topr –20 to +75 °C
Block Diagram
SYNC
GEN
62
60
59
57
63
64
1
2
41
42
43
44
45
46
22
37
VD INITIALIZE
HD INITIALIZE
1/2
HIGH-SPEED
PULSE
GENERATION
CIRCUIT
38
39
8
21
VSS
40
28
ADR . COUNT
H – ROM
LATCH
GATE
DRIVER
26
3
27
24
VDD
25
GATE
10
56
ADR . COUNT
DECODER
49
48
47
V – ROM
LATCH
GATE
COUNTER
51
50
19
18
17
15
16
MODE
SET
ADR . COUNT
ROG – ROM
LATCH
CONTROLLER
SHUT
53
54
52
29
ROM
30
31
DECODER
32
33
34
GATE
35
20
11
12
13
14
23
36
HTSG
61
4
MICROCOMPUTER
5
6
7
9
55
58
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E91817B4X-PK
Page 2
Pin Description
CXD1257AR
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol I/O Description
OSCO
OSCI
EF
ED0
ED1
ED2
SMD1
Vss
SMD2
XVCT
D1
D2
D3
D4
A5
O
Inverter output for oscillation.
I
Inverter input for oscillation.
I
Not used. (With pull-up resistor)
I
Shutter speed setting. Strobe input for serial mode. (With pull-up resister)
I
Shutter speed setting. Clock input for serial mode. (With pull-up resister)
I
Shutter speed setting. Data input for serial mode. (With pull-up resister)
I
Shutter mode setting. (With pull-up resister)
—
GND
I
Shutter mode setting. (With pull-up resister)
O
Not used. (Open)
I
Fix at Low in normal operation. (With pull-down resister)
I
Fix at Low in normal operation. (With pull-down resister)
I
Fix at Low in normal operation. (With pull-down resister)
I
Low: NTSC, High: PAL. (With pull-down resister)
O
Not used. (Open)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A4
A3
A0
A1
A2
Vss
RG
NC
VDD
VDD
H1
H2
Vss
XSUB
XV2
XV1
XSG1
O
Not used. (Open)
O
Not used. (Open)
O
Not used. (Open)
O
Not used. (Open)
O
Not used. (Open)
—
GND
O
Reset gate pulse output.
—
—
Power supply.
—
Power supply for H1 and H2.
O
Clock output for CCD horizontal register drive.
O
Clock output for CCD horizontal register drive.
—
GND for H1 and H2.
O
CCD discharge pulse output.
O
Clock output for CCD vertical register drive.
O
Clock output for CCD vertical register drive.
O
CCD sensor charge readout pulse output.
33
34
35
XV3
XSG2
XV4
O
Clock output for CCD vertical register drive.
O
CCD sensor charge readout pulse output.
O
Clock output for CCD vertical register drive.
– 2 –
Page 3
CXD1257AR
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol I/O Description
TEST2
MCK
XSHP
XSHD
Vss
XSP1
XSP2
XSH1
XSH2
XDL1
XDL2
BFG
CLP1
CLP2
CLP3
I
Test input. Set at Low in normal operation.
O
NTSC: 1820fH/3, PAL: 1816fH/3. Output.
O
Precharge level sample-and-hold pulse.
O
Data sample-and-hold pulse.
—
GND
O
Color separation sample-and-hold pulse.
O
Color separation sample-and-hold pulse.
O
Switching sample-and-hold pulse.
O
Switching sample-and-hold pulse.
O
Delay line clock output.
O
Delay line clock output.
O
Pulse output for chroma modulator in encoder.
O
Clamp pulse output.
I/O
Clamp pulse output. When GM is set at High, standby mode switching input.
I/O
Clamp pulse output. When GM is set at High, standby mode switching input.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CLP4
PBLK
ID
WEN
GM
VDD
CL
PS
HD
VD
HTSG
TEST
XCK
CK
O
Clamp pulse output.
O
Blanking cleaning pulse output.
O
Line identification output.
O
Write enable output for low-speed shutter operation.
I
Low: Analog signal processing, High: Digital signal processing. (With pull-down resister)
—
Power supply.
O
NTSC: 910fH, PAL: 908fH. Clock output.
Switching for electronic shutter speed input method. (With pull-up resister)
I
Low: Serial input, High: Parallel input.
I
Horizontal synchronizing signal input.
I
Vertical synchronizing signal input. (During Low, 9H for NTSC and 7.5H for PAL)
Control input for XSG1 and XSG2. (With pull-up resistor)
I
Low: XSG1, XSG2 halted, High: XSG1, XSG2 generated.
I
Test input. Set at Low in normal operation. (With pull-down resister)
O
NTSC: 1820fH, PAL: 1816fH. Clock output.
I
NTSC: 1820fH, PAL: 1816fH. Clock input.
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Page 4
CXD1257AR
Electrical Characteristics
DC Characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Item
Symbol Conditions Min. Typ. Max. Unit
Supply voltage VDD
Input voltage 1
(Input pins other than those below)
Input voltage 2
(Pins 59 and 60)
Output voltage 1
(Output pins other than those below)
Output voltage 2
(Pins 22, 37, 38, 39, 57, and 63)
Output voltage 3
(Pins 26 and 27)
Output voltage 4
(Pin 1)
Feedback resister
Pull-up resister
Pull-down resister
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
RFB
RPU
RPD
IOH = –2mA
IOL = 4mA
IOH = –4mA
IOL = 8mA
IOH = –8mA
IOL = 8mA
IOH = –1mA
IOL = 1mA
VIN = Vss or VDD
VIL = 0V
VIH = VDD
4.75
0.7VDD
2.2
VDD – 0.5
VDD – 0.5
VDD – 0.5
VDD/2
500k
40k
40k
5.0
2M
100k
100k
5.25
0.3VDD
0.8
0.4
0.4
0.4
VDD/2
5M
250k
250k
V
V
V
V
V
V
V
V
V
V
V
V
V
Ω
Ω
Ω
I/O Pin Capacitances
Item
Input pin capacitance
Output pin capacitance
I/O pin capacitance
(VDD = VI = 0V, fM = 1MHz)
Symbol Min. Typ. Max. Unit
CIN
COUT
CI/O
9
11
11
pF
pF
pF
– 4 –
Page 5
Description of Operation
1. Mode Control
CXD1257AR
Symbol
GM
PS
EF
HTSG
D1
D2
D3
D4
Pin No. L H
55
58
3
61
11
12
13
14
Analog signal processing Digital signal processing
Serial shutter Parallel shutter
speed setting speed setting
Fix at High in normal operation
XSG1, 2 XSG1, 2
OFF ON
Fix at Low in normal operation
Fix at Low in normal operation
Fix at Low in normal operation
NTSC PAL
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Page 6
2. Changes in I/O Signals in Each Mode
CXD1257AR
Symbol
GM
D2
TEST2
XSP1
XSP2
XSH1
XSH2
XDL1
XDL2
BFG
Pin No. Analog color Digital color 1 Digital color 2
55
12
36
41
42
43
44
45
46
47
Color separation
sample-and-hold
pulse output
Color separation
sample-and-hold
pulse output
Switching sampleand-hold pulse
output
Switching sampleand-hold pulse
output
Delay line clock
Delay line clock
Burst flag gate
pulse output
L
L
L
H
L
L
H
L
H
Color separation
Halted at High
sample-and-hold
pulse output
Color separation
Halted at High
sample-and-hold
pulse output
Switching sample-
Halted at Low
and-hold pulse
output
Switching sample-
Halted at Low
and-hold pulse
output
Halted at High
Halted at Low
Burst flag gate
pulse output
(normally not used)
Halted at High
Halted at Low
Burst flag gate
pulse output
(normally not used)
Standby control input
CLP2
49
Clamp pulse output
Low: Standby
High: Normal
operation
Standby control
Low: All circuits
halted for
CLP3
50
Clamp pulse output
standby mode
High: Only CL
output for
standby mode
ID
∗
When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low.
53
Line identification
output
Line identification
output
Standby control input
Low: Standby
High: Normal
operation
∗
Standby control
Low: All circuits
halted for
standby mode
High: Only CL
output for
standby mode
Line identification
output
∗
(Mode combinations other than those shown above cannot be used.)
Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG,
XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4,
PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before
standby.
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Page 7
CXD1257AR
3. Electronic Shutter
The operation of the electronic shutter is controlled by the output of XSUB pulse during particular intervals.
<Shutter Modes>
SMD1 SMD2
L L Flickerless: Eliminates fluorescent frequency-induced flicker.
L H High-speed shutter: Shutter speed faster than 1/60 (NTSC), 1/50 (PAL)
H L Low-speed shutter: Shutter speed slower than 1/60 (NTSC), 1/50 (PAL)
H H No shutter operation.
<Shutter Mode and Speed Setting Method>
PS = High: Parallel input; set by ED0 to ED2, SMD1, and SMD2.
PS = Low: Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin.
3-1. Parallel input (PS = H)
Shutter Speed Compatibility Chart
Mode
OFF
NTSC/PAL
X
NTSC
Flickerless
PAL
NTSC
PAL
X
X
High-speed
shutter
X
X
X
X
X
X
X
SMD1 SMD2 ED0 ED1 ED2 Shutter speed
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
L
L
X
X
X
H
H
L
H
L
H
L
H
L
H
L
X
X
X
H
H
H
L
L
H
H
L
L
H
H
X
X
X
H
H
H
H
H
L
L
L
L
H
H
Shutter off
1/100 (s)
1/120 (s)
1/60 (s)
1/50 (s)
1/125 (s)
1/250 (s)
1/500 (s)
1/1000 (s)
1/2000 (s)
1/4000 (s)
1/10000 (s)
2FLD
4FLD
Low-speed
shutter
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
H
L
H
L
H
L
L
L
H
H
L
L
H
6FLD
H
8FLD
L
10FLD
L
12FLD
L
14FLD
L
16FLD
– 7 –
Page 8
CXD1257AR
3-2. serial input (PS = L)
For serial input (PS = L), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2
(Pin 9) pins as SMD1 and SMD2 (shutter mode control).
In this case, control by SMD1 and SMD2 pins is invalid.
ED1 (CLK)
ED2 (DATA)
ED0 (STB)
ED2 data is latched to the register at the rise of ED1, and transferred to the within during the Low period of ED0.
D0 D1
D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy
– 8 –
Page 9
AC Characteristics
CXD1257AR
ED2
ts2 th2
ED1
tW1 tW1
ts1 ts0
ED0
tw0
Symbol
tS2
th2
tS1
tW0
tS0
tW1
ED2 set-up time, activated by the rising edge of ED1
ED2 hold time, activated by the rising edge of ED1
ED1 rising set-up time, activated by the rising edge of ED0
ED0 pulse width
ED0 rising set-up time, activated by the rising edge of ED1
ED1 pulse width (serial input)
3-4. Low-speed shutter timing chart
OEOEOEOEOEOEOE
VD
XSG1, 2
WEN
Min. Max.
20ns
20ns
20ns
20ns
20ns
20ns
(ED2 : ED1 : ED0 = H : H : H)
—
—
—
50µs
—
—
XSG1, 2
WEN
(ED2 : ED1 : ED0 = H : H : L)
– 9 –
Page 10
3-5. Shutter speed calculation formula
High-speed shutter
• NTSC
T = [26210 – (1FF16 – L16)] × 63.56 + 32.37µs (L16 = Load value)
• PAL
T = [31210 – (1FF16 – L16)] × 64 + 32.14µs
CXD1257AR
NTSC
Load value
0FA16
0FC16
10016
10816
11816
13716
17616
19616
Shutter speed Calculated value Load value Shutter speed Calculated value
1/10000
1/4000
1/2000
1/1000
1/500
1/250
1/125
1/100
1/10424
1/4483
1/2095
1/1014
1/499
1/252
1/125
1/100
Low-speed shutter
Shutter speed calculation formula
N = 2 × (1FF16 – L16) FLD
However, "1FF" cannot be used as the load value.
Load value
Shutter speed (FLD)
0C816
0CA16
0CE16
0D616
0E616
10516
14316
14916
1/10000
1/4000
1/2000
1/1000
1/500
1/250
1/125
1/120
PAL
1/10401
1/4461
1/2083
1/1008
1/496
1/250
1/125
1/120
1FE16
1FD16
:
:
10116
10016
2
4
:
:
508
510
– 10 –
Page 11
492
490
2468
CXD1257AR
357
1
491
Timing Chart (1)
NTSC vertical direction
FLD
HD
BLK/VD
XSG1
XSG2
357
246
1
492
491
ID
XV1
XV2
XV3
XV4
CCD
PBLK
CLP1
CLP2
CLP3
CLP4
BFG
– 11 –
Page 12
46810
2
CXD1257AR
9
1357
582
2468
3579
1
Timing Chart (2)
PAL vertical direction
FLD
BLK/VD
HD
XSG1
XSG2
581
582
ID
XV1
XV2
XV3
XV4
CCD
PBLK
CLP1
CLP2
CLP3
CLP4
BFG
– 12 –
Page 13
102
CXD1257AR
BLK
(63)
HD
45
57
39
51
63
67
50
94
45
89
75
94
94
64
56
CL
BLK/HD
Timing Chart (3)
NTSC horizontal direction
MCK
H1
RG
XSHP
XSHD
XSP1
XSP2
XSH1
– 13 –
XSH2
XDL1
XDL2
27
XV1
XV2
21
XV3
33
XV4
18
XSUB
2
CLP1
24
8
CLP2
29
CLP3
CLP4
18
PBLK
ID
BFG
Black painted portions of H1 clock indicate the optical black.
Page 14
112
CXD1257AR
BLK
(64)
HD
50
62
56
68
72
55
103
94
80
103
103
69
61
CL
BLK/HD
Timing Chart (4)
PAL horizontal direction
MCK
H1
RG
XSHP
XSHD
XSP1
XSP2
XSH1
XSH2
– 14 –
XDL1
XDL2
32
XV1
44
XV2
26
XV3
38
XV4
18
XSUB
2
CLP1
24
8
CLP2
34
CLP3
CLP4
23
PBLK
ID
BFG
Black painted portions of H1 clock indicate the optical black.
Page 15
1clock:104.76ns (NTSC)
105.73ns (PAL)
CXD1257AR
Unit: Number of clocks (Common to NTSC and PAL)
Numerals in brackets are for PAL.
290
[286]
289
[285]
1234
24 24 19
3
10 14
H1
Timing Chart of Readout (NTSC/PAL)
HD
XV2
XV1
FIELD ODD
XV3
XV4
– 15 –
XV1
XV2
XV3
EVEN
XV4
XSG1
XSG2
Page 16
H1/2 start
CXD1257AR
112
Resetting phase
93
3
12
CL
H1
HD
XCK
MCK
H2
RG
XSHP
XSHD
XSP1
XSP2
XDL1
XDL2
XSH1
Timing Specifications of Resetting Phase and H1/2 Start — High-speed Waveform (NTSC)
– 16 –
XSH2
Page 17
H1/2 start
CXD1257AR
118
Resetting phase
100
3
12
CL
H1
HD
XCK
MCK
H2
RG
XSHP
XSHD
XSP1
XSP2
XDL1
XDL2
Timing Specifications of Resetting Phase and H1/2 Start — High-speed Waveform (PAL)
– 17 –
XSH1
XSH2
Page 18
Package Outline Unit: mm
12.0 ± 0.2
∗ 10.0 ± 0.1
CXD1257AR
64PIN LQFP (PLASTIC)
49
64
0.5 ± 0.08
48
1
0.18 – 0.03
0.1 ± 0.1
+ 0.08
33
16
32
17
(0.22)
A
+ 0.2
1.5 – 0.1
(11.0)
0.5 ± 0.2
+ 0.05
0.127 – 0.02
0.1
SONY CODE
EIAJ CODE
JEDEC CODE
0° to 10°
DETAIL A
0.5 ± 0.2
LQFP-64P-L01
LQFP064-P-1010
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
– 18 –
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
0.3g
PLATING
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