Datasheet CXA3621GE Datasheet (Sony)

CXA3621GE

Fingerprint Sensor

Description

The CXA3621GE is an electrostatic capacitance

method fingerprint sensor.

This monolithic IC integrates the sensor block, sense amplifier (3-bit gain adjustment), sample-andhold, output amplifier and output buffer needed to acquire fingerprint images, as well as the timing generator for determining the operation of these functions onto a single chip.

Features

• Electrostatic capacitance type sensor (charge transfer method)

• Number of pixels: 192 × 128

• 317 DPI

• Low power consumption (50mW or less) ∗ When P/S: 18µW or less

• Single 3.0V power supply

• Sensor gain control: 3 bits

• S/N ratio improved by on-chip sensor block parasitic capacitance cancel function

30 pin LLGA (Plastic)

Applications

Fingerprint verification units

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage AVDD, DVDD VSS – 0.5 to +7.0 V

• Input voltage VI VSS – 0.5 to VDD + 0.5 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –25 to +125 °C

• Allowable power dissipation PD 1100 mW

Recommended Operating Conditions

• Supply voltage AVDD, DVDD 2.7 to 3.6 V

• Ambient operating temperature Ta 0 to +50 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E02127-PS

Block Diagram

CXA3621GE

C_SP

UC

XSP (D/I)

CLK (D/I)

ADCLK (D/O)

Timing

Generator

S_CNT

Load

R_SP

UC UC

SENSOR

UC UC UC UC

...........

192

Sense AMP (×192)

192

S/H & SW (×192)

192

Row Shift Register

...........

UC UC

.........

128

........

C_CLK

Column Shift Register

3bit

DAC

Output

Buffer

3

DI (D/I)

AOUT (A/O)

R_CLK

VOS (Bias)

– 2 –

Detailed Block Diagram

CXA3621GE

C_SP

...........

192 (Dummy)

...........

UC UC UC UC UCUC

SVss[1:128]

128

DUMMY SENSOR

SVss[1:128]

........

UC

C_CLK

C_LOG

SR[1:128]

.........

128

SENSOR (UC)

128

C_COUT

UC

SVss

UC

SR

................

192

................

UC

C[1:192]

UC UC UC UC UC

IN_N[1:192]

192

VCS_O

BIAS_O

DUMMY

SAMP

SAMP (192)

S[4:5]

S[3:5]N

DD

SV

VM

PAMP_D

OUT

VCSN

OAMP

SD1

OUT

SC[1:192] SC[1:192]N

192 192

VOS

PAMP_S

S[6:7]

S[6:7]N

R_LOG

CLK

DCLK

C_CO

XSP

DC_VOS

BUF

LAND No.

7C 7D

7E

7F 6B

6C

6D

6E

6F

5B

5C 5D

5E

5F

4F

4E

4D 4C

4B

3F

28 27

26

25 24

23

22

21

20

19

18 17

16

15

14

13

12 11

10

9

Pin Symbol SGND (P/S) AV

DD (P/S)

AVss (P/S)

AOUT (A/O) VOS (Bias)

VCS_O (Bias)

NC

DD (P/S)

DV

SS (P/S)

CSRO (D/O)

RSRO (D/O) C_CK (D/O)

ADCLK (D/O)

SVDS (D/O)

PS (D/I)

CLK (D/I)

XSP (D/I) DI2 (D/I)

DI1 (D/I)

DI0 (D/I)

DSR DSVss

C_SP

TG

S[4:5]

C_CLK

S[3:5]N

DCLK

SR

SD1

SD

DI[0:1]

SVDS

DC_VM

– 3 –

BIAS_SA

8

TEST3 (D/I)

TEST2 (D/I)

7

TEST1 (D/I)

6

5

VCS_S (Bias)

4

VM (Bias)

3

AV

2

SGND (P/S)

1

SS (P/S)

DD (P/S)

3E

3D

3C

3B

2F

2E

2D

2C

Pin Description

CXA3621GE

Serial

No.

—

1 2

3 4 5

6 7 8

9 10 11

12

Land No.

2B 2C 2D

2E

2F

3B 3C 3D

3E

3F

4B 4C

4D

Symbol SUB SGND AVDD

AVSS VM VCS_S

TEST1 TEST2 TEST3 DI0 DI1 DI2

XSP

I/O Power Power Power

Power

A/O A/O

D/I

Description

Substrate electrode (chip rear surface electrode) 3.0V (VDD). Sensor lightning conductor electrode. (Connect to the GND which

is the other system of operating power supply.) Analog power supply 3.0V. Analog GND. Sense amplifier reference voltage monitor 1.5V (1/2 VDD).

(Do not connect.) Sense amplifier current source bias monitor. (Do not connect.) Test mode selection. (Connect to GND.) Test mode selection. (Connect to GND.) Test mode selection. (Connect to GND.) Gain setting input (LSB). Gain setting input. Gain setting input (MSB). Sense start pulse (negative pulse).

The column and row shift registers and the timing generator are

cleared by this signal. 13 14 15 16 17 18 19 20 21 22 23

24 25

26 27

28

4E 4F 5F

5E 5D 5C

5B

6F

6E 6D 6C

6B

7F

7E 7D

7C

CLK PS SVDS ADCLK C_CK RSRO CSRO DVSS DVDD NC VCS_O

VOS AOUT

AVSS AVDD

SGND

D/I

D/I D/O D/O D/O D/O D/O

Power Power

—

A/O A/O A/O

Power Power

Power

Main clock 2MHz. Power saving mode setting. (Low: Operation; High: Standby) Integrating pulse monitor. (Do not connect.) Delay clock. (Do not connect.) Column shift register clock. (Do not connect.) Column shift register final output. (Do not connect.) Row shift register final output. (Do not connect.) Digital GND. Digital power supply 3.0V. No connection. (Do not connect.) Output amplifier current source bias monitor. (Do not connect.) Output amplifier reference voltage monitor 1.09V (4/11VDD).

(Do not connect.) Sensor output. Analog GND. Analog power supply 3.0V. Sensor lightning conductor electrode. (Connect to the GND which

is the other system of operating power supply.)

– 4 –

CXA3621GE

Electrical Characteristics

DC Characteristics (Vss = 0V, Ta = 25°C)

Item Analog supply voltage Digital supply voltage Current consumption

(for operation) Current consumption

(for standby) Input voltage (High) Input voltage (Low) Output voltage (High) Output voltage (Low)

Input leak current Output voltage

Output voltage

Symbol

AVDD DVDD

IDD1

IDD2 VIH

VIL VOH VOL

IL VM

VOS

VDD = 3V, P/S = L

VDD = 3V, P/S = H, CLK = L Digital (CMOS) input cell

Digital (CMOS) input cell VDD = 3V, IOH = –800µA VDD = 3V, IOL = 2.4mA VDD = 3V,

digital (CMOS) input cell [3V/0V] VDD = 3V VDD = 3V

Conditions

Min.

2.7

5.0

0.7VDD Vss

2.6 0

–1

1.4

1.00

Typ.

3.0

8.5

1.5

1.09

Max.

3.6

13.0

5

VDD

0.3VDD

3.0

0.4 1

1.6

1.20

Unit

V V

mA

µA

V V V V

µA

V V

AC Characteristics (VDD = 3.0V, VSS = 0V, Ta = 25°C)

Item

Clock input period

Symbol

CLK

Conditions

Min.

400

Typ. Max.

Unit

ns

Number of sensor defects

1

Output voltage (Air_Level) Output voltage (Water_Level)

∗1

Output voltage Air Level means the output level in the condition where nothing is placed against the sensor

AOUT AOUT

∗

2

∗

0 850 950

1090 1200

3 1350 1450

surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the sensor output and then taking the average. The gain setting for this measurement is (011).

∗2

Output voltage Water Level specifies the degree to which the output level changes from the Air Level when a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level when a drop of water is placed on the surface) are built into the sensor chip, and the average of these output values is calculated. The difference from the Air Level noted above becomes the Water Level. The gain setting for this measurement is (011).

Defects

mV mV

– 5 –

Electrical Characteristics Measurement Circuit

CXA3621GE

Digital input pin Digital output pin Analog output pin

1.0µF AOUT/O

VCS_O/O

0.1µF

CSRO/O

C_CK/O

SVDS/O

TEST2/I

VCS_S/O

AVDD

DV

DD

CLK/I

DI2/I

DI0/I

27

25

23

21

19

17

15

13

11

28

26

24

22

20

18

SGND

AV

SS

VOS/O

NC

DVSS

RSRO/O

0.1µF

ADCLK/O

16

PS/I

14

12

XSP/I

DI1/I

9

7

10

TEST3/I

8

TEST1/I

5

6

Vcc

3.0V

AV

SS

SGND

3

1

VM/O

4

DD

AV

2

1.0µF

0.1µF

The load of 30pF or more is added to each pin.

– 6 –

Application Circuit

CXA3621GE

Fingerprint sensor chip

Microcomputer

DRAM

8-bit A/D

Flash

Registered data

During registration

During verification

ASIC

Binary value, verification

Verification results

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third par ty patent and other right due to same.

– 7 –

CXA3621GE

Description of Operation

• Fingerprint sensor principle

The principle of this newly developed fingerprint sensor is described below (Fig. 1). The sensor block contains an array of metal electrodes which are covered on top by an insulating film (overcoat). When a finger (which is conductive matter) is placed directly against this surface, the three elements of the metal electrode, the insulating film and the finger form a capacitor. The difference between the fingerprint ridges and valleys is the diff erence in distance to the metal electrodes, and becomes the difference in the capacitance values of the individually formed capacitors. (The ridge capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air in addition to this, making the difference between the ridge and valley capacitance values even greater than the difference in distance.) Using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by transferring and converting these charges to voltages.

Ridge Valley

Si

Fig. 1

Fingerprint unevenness

Overcoat Metal electrode Inter-layer film

– 8 –

CXA3621GE

Sensor Array

Dummy Block

Sensor block

(192 × 128: Sensor cell)

(128: Dummy block)

Vcel

SVss

Vceld Vsld

SVss

Cs

Sr

Cp

Cp'

Upper: Sensor cell Lower: Dummy block

Sr

Cp

Cp'

Vsl

S3

S4

Cf1

Vsns

S5 Sc

S_Amp

SV

DD

V

DD

VM

S4

Cf1

Vsnsd

S_Amp

SV

DD

V

DD

VM

Sense amplifier block

(192: Sensor cell) (1: Dummy block)

Ch1

S5 Sd1

Ch1

VM

SS

Cf2

P_Amp

SD

Cf2

P_Amp

Ssig

Sdmy

S6

Cf3

Voi Voo

Cs1

O_Amp

VOS

Output block

(1)

S7

Ch2

Buffer

Aout

Fig. 2

• Fingerprint sensor operation (Fig. 2)

Description of characters

Cs: Capacitance formed between the finger and the metal electrode Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate Cp': Capacitance for canceling Cp (Cp ≈ Cp') Ch∗: Hold capacitance Cf∗: Feedback capacitance for determining the gain S∗: Switch V∗: Node voltage VM = VDD, VOS = VDD

1 2

4

11

– 9 –

Appearance and Readout Order

Cell (1, 1)

15.36mm

Cell (1, 192)

CXA3621GE

Scan Formation

Cell (1, 1) to Cell (1, 192)

10.24mm

G

F

E

D

C

Sensor Area

192 × 128

Cell (128, 1)

19.8mm

4 9 14 15 20 25

3 8 13 16 21 26

2 7 12 17 22 27

1 6 11 18 23 28

Cell (128, 192)

16.8mm Cell (128, 1) to

Cell (128, 192)

Flip

B

A

1234 7658

5101924

– 10 –

CXA3621GE

Notes on Operation

Sensor surface electrostatic strength

Aerial discharge (150pF, 330Ω): ±12kV or more

Sony conducts tests using the 50% flash-ov er method∗ from the viewpoint of reproducibility and comparison of performance. This method allows more stable measurement than the general method of approaching a discharge gun (approach method). However the discharge distance tends to be longer than for the approach method, so the above performances may not be satisfied if testing is performed by the approach method.

∗The discharge distance (distance between the probe tip and the test piece) is determined, and a trigger is applied at fixed time intervals to raise the applied voltage and start discharge. The applied voltage when discharge occurs at just 1/2 of the number of trigger times is the 50% flash-over voltage. The flash-over voltage changes when the distance is changed, but it has been confirmed that there are no problems in terms of sensor performance up to ±12kV.

Sensor surface strength

The sensor surface may be broken by the contact of the metal and others. Therefore, be sure to pay the sufficient attention to handling this IC.

∗Never handle sensors with metal tweezers or similar tools on mounting lines, etc.

– 11 –

Timing Chart

CXA3621GE

500ns

XSP (3F)

CLK (4C)

Strobe Point

Input level

Output level

250ns

480ns

V

IH

= 0.7V

VIL = 0.3V

0.65V

0.35V

250ns

DD

High

DD

X

DD

Low

– 12 –

Input/Output Signal

CXA3621GE

CLK (Pin 13 • 4E) Input

XSP (Pin 12 • 4D) Input

AOUT (Pin 25 • 7F) Output

500ns (1CLK)

250ns

750ns

((192 + 1 + 63) × 2 + 1)

16512.5µs (33025CLK) {(192 + 1 + 63) × (2 + 126) + (192 + 1 + 63) + 1}

256.5µs

(513CLK)

(Repeat 128 Times)

96µs

(192CLK)

1st line

output

32µs

(64CLK)

Sensor

read

96µs

(192CLK)

2nd line

output

F = 2MHz

750ns

1 to 1.2V

32µs

(64CLK)

Sensor

read

AOUT (Pin 25 • 7F) Detail

2.3V

1.1V

500ns (1CLK)

– 13 –

Package Outline Unit: mm

SA

0.2

20.0

0.5 ± 0.3

2.42 ± 0.3

19.0 ± 0.25

15.16 ± 0.25

PIN 1 INDEX

R1.0MAX

CXA3621GE

30PIN LLGA

∗

2.6 ± 0.3

0.5 ± 0.3

∗

X

1.2 ± 0.1

0.08MAX

S

0.1

B S

17.0

0.2

4-R1.0

SENSOR AREA

3 – φ2.2

2.3

G

2.07

F E D

7.1

C B

2.07

A

2.2

2.3

SONY CODE JEITA CODE

JEDEC CODE

10.16

A

2

1

345678

x4

0.15

0.8

2.54

LLGA-30P-02

10.04 ± 0.25

Y

52 – φ1.2 ± 0.08

φ0.1

M

3.42

3.65

16.0 ± 0.25

SAB

2.54

B

(0.4)

0.25MAX

DETAIL Y

NOTE : ∗ Not include flash burr.

PACKAGE STRUCTURE

PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL

PACKAGE MASS

ORGANIC SUBSTRATE

NICKEL & GOLD PLATING

DETAIL X

0.25MAX

COPPER

0.7g

– 14 –

Sony Corporation