Datasheet CXA3235N, CXA3236N Datasheet (Sony)

—1—

E97943A81-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta = 25 °C)

• Supply voltage VCC1,VCC2 –0.3 to +5.5 V

VCC3 –0.3 to +10.0 V

• Storage temperature
Tstg –55 to +150 °C

• Allowable power dissipation

PD 880 mW

(when mounted on a substrate)

Operating Conditions

• Supply voltage VCC1, VCC2 4.75 to 5.30 V

VCC3 4.75 to 9.45 V

• Operating temperature
Topr –25 to +75 °C

Description

The CXA3235/3236N is a monolithic TV tuner IC
which integrates local oscillator and mixer circuits for
VHF band, local oscillator and mixer circuits for UHF
band, an IF amplifier and a tuning PLL onto a single
chip, enabling further miniaturization of the tuner.
The PLL on this IC supports the I2C bus format.

Features

• Low noise figure

• Low power consumption (5 V, 54 mA typ.)

• On-chip tuning PLL (I2C bus format)

• Selection of frequency steps 31.25 kHz, 50 kHz

and 62.5 kHz

• On-chip 4-output band switch

Applications

• TV tuners

• VCR tuners

• CATV tuners

Structure

Bipolar silicon monolithic IC

All Band TV Tuner IC with On-chip PLL

30 pin SSOP (Plastic)

CXA3235/3236N

Note) Electrostatic discharge strength is weak, and care should be taken in handling this IC.

—2—

CXA3235/3236N

Block Diagram and Pin Configuration

Bias

USW

IF AMP

SCL
SDA

ADSW

FMT

BVL

BVH

BU

V

CC1

MIXout1
MIXout2

GND1

MS

VHFin

UHFin1

UHFin2

Shift
Register

Band
SW
Driver

V.REG

VHF

MIX

UHF

MIX

Buffer

VHF

OSC

UHF
OSC

Buffer

Buffer

Phase
Detector

Charge
Pump

LOCK
Det

Divider
14/15bit

Prescaler
1/8

REF

OSC

Divider
1/512,640,1024

I2C BUS

Receiver

1
2
3

4

5

6

7

8

9

10

11

12

13

14

15

VOSC1

GND

VOSC2

UOSCB1

UOSCE2

UOSCB2

V

CC2

GND

IF OUT

LOCK

CPO

CPE

REFOSC

VCC3

UOSCE1

16

17

18

20

21

22

23

24

25

27

28

29

19

26

30

—3—

CXA3235/3236N

Pin Description

Pin

Symbol Equivalent circuit

Pin voltage

Description

No. (V)

1

2

3

4

5

6

7
8

9

10

11

SCL

SDA

ADSW

FMT

BVL

BVH

BU

VCC1

MIXout1

MIXout2

GND1

—

—

1.25

(when open)

ON : VCC3

OFF : 0

—

Clock input.

Data I/O.

Address selection.
This pin controls bits 2 and 1 of
the address byte.

4 : Output for FM TRAP.
5 : Power supply output for

VL band.

6 : Power supply pin for VH

band.

7 : Power supply output for

UHF band.

The pin corresponding to the
selected band goes High.

Analog circuit power supply.

Mixer outputs.

Analog circuit GND.

1

22

VCC2

100k

5k

2

22

VCC2

100k

5k

3

22

150k

50k

VCC2

4
5

6
7

30

20k

VCC3

9

10

—

—4—

CXA3235/3236N

Pin

Symbol Equivalent circuit

Pin voltage

Description

No. (V)

12

13

14

15

16

18

17

19

20

21

22

MS

VHFin

UHFin1

UHFin2

VOSC1

VOSC2

GND

UOSCB1

UOSCE1

UOSCE2

UOSCB2

1.5

(when open)

2.3

(VHF)

0

(UHF)

0

(VHF)

2.3

(UHF)

0

(VHF)

2.3

(UHF)

3

(VHF)

3.1

(UHF)

3.5

(VHF)

5.0

(UHF)

—

3.2

(VHF)

2.9

(UHF)

—

(VHF)

2.4

(UHF)

—

(VHF)

2.4

(UHF)

3.2

(VHF)

2.9

(UHF)

Pin used for selecting a
frequency step mode.
Any of the five modes can be
selected by applying an input
voltage.

VHF input.
The input format is unbalanced
input.

UHF inputs.
The input method can be
selected from balanced input
or unbalanced input.

External resonance circuit
connection for VHF oscillator.

GND

External resonance circuit
connection for UHF oscillator.

50k

VCC2

120k

1213

14

15

3k 3k

18 16

8

8p

3k

3k

15p

600

50

V

CC1

19 2220 21

3k

3k

V

CC1

—5—

CXA3235/3236N

Pin

Symbol Equivalent circuit

Pin voltage

Description

No. (V)

23
24

25

26

27

28

29

30

VCC2

GND2

IFOUT

LOCK

CPE

CPO

REFOSC

VCC3

—
—

2.3

5.0

(Lock)

0.2

(UNLock)

0.6

2.0

4.3

—

PLL circuit power supply.
PLL circuit GND.

IF output.

LOCK detection.
High when locked, Low when
unlocked.

NPN transistor connection for
varicap diode drive.

Charge pump output.
Connect a loop filter.

Crystal connection for
reference oscillator.

Power supply for external
supply.

25

8

40

V

CC1

26

22

VCC2

40k

28

27

22

VCC2

200

500

20k

29

60k

30p 30p

—
—

—6—

CXA3235/3236N

Electrical Characteristics See the Electrical Characteristics Measurement Circuit.
Circuit Current (VCC=5 V, Ta=25 °C)

Item

Circuit current A

Circuit current D

Symbol

AICCV

AICCU
DICC

Measurement conditions
VCC1 current, Band switch output
open during VHF operation
VCC1 current, Band switch output
open during UHF operation
VCC2 current

Min. Typ. Max. Unit

30 41 55 mA

31 42 56 mA

7 11 15 mA

Item

Conversion gain

∗1

Noise figure ∗1,

∗2

1 % cross
modulation ∗1,

∗3

Maximum output power

Switch ON drift

∗4

Supply voltage drift

∗4

Symbol
CG1
CG2
CG3
CG4
NF1
NF2
NF3
NF4

CM1

CM2

CM3

CM4
Pomax

∆fsw1

∆fsw2

∆fsw3

∆fsw4

∆fst1

∆fst2

∆fst3

∆fst4

Measurement conditions
VHF operation fRF = 55 MHz
VHF operation fRF = 360 MHz
UHF operation fRF = 360 MHz
UHF operation fRF = 800 MHz
VHF operation fRF = 55 MHz
VHF operation fRF = 360 MHz
UHF operation fRF = 360 MHz
UHF operation fRF = 800 MHz
VHF operation
fD = 55 MHz, fUD = ±12 MHz
VHF operation
fD = 360 MHz, fUD = ±12 MHz
UHF operation
fD = 360 MHz, fUD = ±12 MHz
UHF operation
fD = 800 MHz, fUD = ±12 MHz
50 Ω load saturation output
VHF operation fOSC = 100 MHz
∆f from 3 s to 3 min after switch ON
VHF operation fOSC = 405 MHz
∆f from 3 s to 3 min after switch ON
UHF operation fOSC = 405 MHz
∆f from 3 s to 3 min after switch ON
UHF operation fOSC = 845 MHz
∆f from 3 s to 3 min after switch ON
VHF operation fOSC = 100 MHz
∆f when VCC 5 V changes ±5 %
VHF operation fOSC = 405 MHz
∆f when VCC 5 V changes ±5 %
UHF operation fOSC = 405 MHz
∆f when VCC 5 V changes ±5 %
UHF operation fOSC = 845 MHz
∆f when VCC 5 V changes ±5 %

Min. Typ. Max. Unit

21 24 27 dB
22 25 28 dB
26 29 32 dB
27 30 33 dB

12 15 dB
11 14 dB

8.5 12.5 dB

9.5 13.5 dB

97 101 dBµ

96 100 dBµ

92 96 dBµ

88 92 dBµ
+5 +10 dBm

±300 kHz

±400 kHz

±400 kHz

±500 kHz

±150 kHz

±250 kHz

±200 kHz

±250 kHz

OSC/MIX/IF Amplifier Block

—7—

CXA3235/3236N

Item
SDA, SCL
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
SDA “L” output voltage
Clock input hysteresis
Clock rate
CPO (charge pump)
Output current 1
Output current 2
Leak current 1
Leak current 2
REFOSC
Oscillator
frequency range
Input capacitance
Drive level
BVL, BVH, BU (Band SW)
Output current
Saturation voltage
Leak current
FMT (Band SW)
Output current
Saturation voltage
Leak current
Bus timing
SCL clock frequency
Start waiting time
Start hold time
Low hold time
High hold time
Start setup time
Data hold time
Data setup time
Rise time
Fall time
Start setup time

Symbol

VIH
VIL
IIH
IIL
LSDA
CIHYS
CIRATE

ICPO1
ICPO2
LeakCP1
LeakCP2

FXTOSC
CXTOSC

VXTOSC

IBS1
VSAT1
LeakBS1

IBS2
VSAT2
LeakBS2

fSCL
tWSTA
tHSTA
tLOW
tHIGH
tSSTA
tHDAT
tSDAT
tR
tF
tSSTO

Measurement conditions

VIH = VCC
VIL = GND
Sink current = 3 mA

Byte4/Bit6 = 0
Byte4/Bit6 = 1
Byte4/Bit6 = 0
Byte4/Bit6 = 1

When ON
When ON Sink current = 20 mA
When OFF

When ON
When ON Sink current = 5 mA
When OFF

See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.
See Timing Chart on Page 15.

Min. Typ. Max. Unit

3 VCC V

GND 1.5 V

0 –0.1 µA

–1 –2 µA

0.4 V

0.25 0.4 0.65 V

0.5 MHz

±35 ±50 ±75 µA

±140 ±200 ±300 µA

30 nA

100 nA

3 12 MHz

17.5 19 20.5 pF
200 400 mVp-p

–25 mA

100 200 mV

0.5 3 µA

–7 mA

75 150 mV

0.03 0.1 µA

0 400 kHz

1300 ns

600 ns

1300 ns

600 ns
600 ns

1300 ns

600 ns

300 ns
300 ns

600 ns

PLL Block

∗1

Measured value for untuned inputs.

∗2

Noise figure is the direct-reading value of NF meter in DSB.

∗3

Desired signal (fD) input level is –30 dBm. Undesired signal (fUD) is 100 kHz, 30 % AM at ±12 MHz.
The measurement value is undesired signal level, it measured with a spectrum analyzer at S/I=46 dB.

∗4

Value when the PLL is not operating.

—8—

CXA3235/3236N

Electrical Characteristics Measurement Circuit

CXA3235/3236N

CL

DA

CE

FMT

BVL

BVH

BU

V

CC

1

MIX out1

MIX out2

GND1

MS

VHF in

UHFin1

UHFin2

V

CC

3

REFOSC

CPO

CPE

LOCK

IFOUT

GND2

V

CC

2

UOSCB2

UOSCE2

UOSCE1

UOSCB1

VOSC2

GND

VOSC1

100p

XTAL

1n

LOCK IF OUT

47k 0.047µ

8200p

2SC2785

33p

22k

+30V

3.3µ 1n

+5V

56p

47k

7p

47k

1T363 1T363

0.5p

0.5p

47k

47k

16p

1n

SCL SDA ADSW

FMT BVL BVH BU

2k

56p 56p

100

1n

1n

+5V

3.3µ

1n 1n 1n

VHF IN

1n

UHF IN

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15

4.5t 4.5t

1T363

1T362

47k

150p

47k

3.0ø

2.5t

1n

47k

51

BVH

3.2ø

5.5t

1n

47k

51

0.5p

4MHz

1.2k

1p

8p 4p 8p

56p

2.5ø2.5t

1617182021222324252627282930 19

BVL

—9—

CXA3235/3236N

Description of Functions

The CXA3235/3236N is a terrestrial wave broadcast tuner IC which converts frequencies to IF in order to
tune and detect only the desired reception frequency of VHF, CATV and UHF band signals.
In addition to the mixer, local oscillator and IF amplifier circuits required for frequency conversion to IF, this
IC also integrates a PLL circuit for local oscillator frequency control onto a single chip.
The functions of the various circuits are described below.

1. Mixer circuit
This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local
oscillation signal.

2. Local oscillator circuit
A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and
inductance.

3. IF amplifier circuit
This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output
stage.

4. PLL circuit
This PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of a prescaler, main
divider, reference divider, phase comparator, charge pump and reference oscillator. The control format
supports the I2C bus format. The following five modes can be selected according to the combination of the
frequency division values of the main and reference dividers.

Mode Main divider Reference divider

B-0 15 bit 1024 fixed
B-1 14 bit 512 fixed
B-2 15 bit 640 fixed
B-3 15 bit 512 fixed
B-4 15 bit 512/1024 switching

—10—

CXA3235/3236N

Description of Analog Block Operation

(See the Electrical Characteristics Measurement Circuit.)

VHF oscillator circuit

• This circuit is a differential amplifier type oscillator circuit.

Pin 18 is the output and Pin 16 is the input.
Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 18 via coupled
capacitance, inputting to Pin 16 with feedback capacitance, and applying positive feedback.

• The amplifier between Pins 16 and 18 has an extremely high gain. Therefore, care should be taken to
avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal
oscillation.

VHF mixer circuit

• The mixer circuit employs a double balance mixer with little local oscillation signal leakage.

The input format is base input type, with Pin 12 grounded and the RF signal input to Pin 13.

• The RF signal is inserted from the oscillator, converted to IF frequency and output from Pins 9 and 10.

• Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9

and 10 at this time must be DC 4.0 V or more.

UHF oscillator circuit

• This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential

oscillation operation via an LC resonance circuit including a varicap. Connect resonator capacitance
composing colpitts oscillators between Pins 19 and 20, Pins 20 and 21, and Pins 21 and 22.

• Then, LC resonance circuit comprising a varicap diode is connected across Pins 19 and 22.

UHF mixer circuit

• This circuit employs a double balance mixer like the VHF mixer circuit.

The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be
selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input
consisting of grounding Pin 14 via a capacitor and input to Pin 15.

• Pins 9 and 10 are the mixer outputs.

• Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9

and 10 at this time must be DC 4.0 V or more.

IF amplifier circuit

• The signals frequency converted by the mixer are output from Pins 9 and 10, and at the same time are

AC coupled inside the IC and input to the IF amplifier.

• Single-tuned filters are connected to Pins 9 and 10 in order to improve the interference characteristics of
the IF amplifier.

• The signal amplified by the IF amplifier is output from Pin 25.
The output impedance is approximately 75 Ω.

—11—

CXA3235/3236N

Description of PLL Block

The PLL on this IC supports the I2C bus control format. The control pins are as shown in the table below.

1) Mode Setting Method

The modes for each frequency step are set according to the MS pin voltage.

Symbol

ADSW

SCL

SDA

Description

Address selection

SCL input

SDA I/O

Mode

B-0
B-1
B-2
B-3

B-4

MS pin voltage

0 to 0.15 VCC

OPEN

0.45 VCC to 0.55 VCC

0.65 VCC to 0.75 VCC

0.85 VCC to VCC

Main

divider

15 bit
14 bit
15 bit
15 bit

15 bit

Reference

divider

1024

512
640

512
512/
640/

1024

Reference frequency

3.90625 kHz

7.8125 kHz

6.25 kHz

7.8125 kHz

7.8125 kHz/

6.25 kHz/

3.90625 kHz

Frequency

step

∗

31.25 kHz

62.5 kHz
50 kHz

62.5 kHz

62.5 kHz/
50 kHz/

31.25 kHz

∗ Frequency step is for when X’tal OSC = 4 MHz.

2) Address Setting

The responding address can be changed according to the ADSW pin voltage, so that multiple PLL can
exist within one system.

Address

ADSW pin voltage

0 to 0.1 VCC

OPEN or 0.2 VCC to 0.3 VCC

0.4 VCC to 0.6 VCC

0.9 VCC to VCC

MA1

0
0
1
1

MA0

0
1
0
1

—12—

CXA3235/3236N

3) Programming

The VCO lock frequency is obtained according to the following formula.

fosc = fref × 8 × (32 M + S)

fosc: local oscillator frequency
fref : reference frequency
8 : prescaler fixed frequency division ratio
M : main divider frequency division ratio
S : swallow counter frequency division ratio

The variable frequency division ranges of M and S are as follows, and are set as binary.

32 ≤ M ≤ 1023 (32 ≤ M ≤ 511 for B-1 mode)
0 ≤ S ≤ 31

3-1) The CXA3235N control format is as follows.

3-1-1 : B-0/B-1/B-2/B-3 Modes

Write-mode : Slave Receiver

MODE

Address byte
Divider byte 1
Divider byte 2

Control byte

Band SW byte

MSB LSB

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 1 0 0 0 MA1 MA0 0 A
0 M9

∗

M8 M7 M6 M5 M4 M3 A

M2 M1 M0 S4 S3 S2 S1 S0 A

1 CP T1 CD X X X OS A

X X X X BU FMT BVH BVL A
X : Don’t care
∗ M9 is “0” for B-1 mode.

3-1-2 : B-4 Mode

Write-mode : Slave Receiver

MODE

Address byte
Divider byte 1
Divider byte 2

Control byte

Band SW byte

MSB LSB

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 1 0 0 0 MA1 MA0 0 A
0 M9 M8 M7 M6 M5 M4 M3 A

M2 M1 M0 S4 S3 S2 S1 S0 A

1 CP T1 CD X R1 R0 OS A

X X X X BU FMT BVH BVL A

X : Don’t care

—13—

CXA3235/3236N

3-2) The CXA3236N control format is as follows.

The BU and FMT data order is switched for the CXA3235N.

3-2-1 : B-0/B-1/B-2/B-3 Modes

Write-mode : Slave Receiver

MODE

Address byte

Divider byte 1
Divider byte 2

Control byte

Band SW byte

MSB LSB

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 1 0 0 0 MA1 MA0 0 A
0 M9

∗

M8 M7 M6 M5 M4 M3 A

M2 M1 M0 S4 S3 S2 S1 S0 A

1 CP T1 CD X X X OS A

X X X X FMT BU BVH BVL A
X : Don’t care
∗ M9 is “0” for B-1 mode.

3-2-2 : B-4 Mode

Write-mode : Slave Receiver

MODE

Address byte
Divider byte 1
Divider byte 2

Control byte

Band SW byte

MSB LSB

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 1 0 0 0 MA1 MA0 0 A
0 M9 M8 M7 M6 M5 M4 M3 A

M2 M1 M0 S4 S3 S2 S1 S0 A

1 CP T1 CD X R1 R0 OS A
X X X X FMT BU BVH BVL A

X : Don’t care

A : Acknowledge bit
MA0, MA1 : address setting
M0 to : main divider frequency division ratio setting
S0 to : swallow counter frequency division ratio setting
T1 : test mode selection (when “1”)
CD : charge pump OFF (when “1”)
OS : varicap output OFF (when “1”)
CP : charge pump current switching (200 µA when “1”, 50 µA when “0”)
BVL : VL band switch control (output PNP Tr ON when “1”)
BVH : VH band switch control (output PNP Tr ON when “1”)
FMT : FM trap switch control (output PNP Tr ON when “1”)
BU : UHF band switch control (output PNP Tr ON when “1”)
R0, R1 : Reference divider frequency division ratio setting

—14—

CXA3235/3236N

Reference Divider Frequency Division Ratio Table

R1

0
1
X

R0

1
1
0

Reference divider

1024

512
640

X : Don’t care

3-3) The read data format is as shown below.

Read-mode : Slave Transmitter

MODE

Address byte

Status byte

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 1 0 0 0 MA1 MA0 1 A

PR FL 1 1 1 X X X A

A : acknowledge bit
PR : power-on reset
FL : lock detection signal
MA0, MA1 : address setting

—15—

CXA3235/3236N

I2C Bus Timing Chart

tWSTA

tSSTA

tHSTA tLOW tHIGH

tR tF

tSDAT tHDAT

tSSTO

START CLOCK DATACHANGE STOP

tSSTA =Start setup time
tWSTA =Start waiting time
tHSTA =Start hold time
tLOW =LOW clock pulse width
tHIGH =HIGH clock pulse width

tSDAT =Data setup time
tHDAT =Data hold time
tSSTO =Stop setup time
tR =Rise time
tF =Fall time

SDA

SCL

—16—

CXA3235/3236N

Circuit current vs. Supply voltage 1

AI

CC

- Circuit current [mA]

VCC1 - Supply voltage [V]

Circuit current vs. Supply voltage 2

DI

CC

- Circuit current [mA]

VCC2 - Supply voltage [V]

Band SW output voltage vs. Output current (BU, BVH, BVL)

Output voltage [V]

Output current [mA]

Band SW output voltage vs. Output current (FMT)

Output voltage [V]

Output current [mA]

0 1 2 3 4 65

I/O characteristics (Untuned input)

IF output level [dBm]

RF input level [dBm]

45

40

35

UHF

4.7 4.8 4.9 5.0 5.2 5.3 5.4

15

10

5

4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4

VCC3=9V

VCC3=5V

9.2

9.0

8.8

8.6

5.0

4.8

4.6

4.4
0 5 10 15 20 25

9.2

9.0

8.8

8.6

5.0

4.8

4.6

4.4

VCC3=9V

VCC3=5V

20

0

–20

–40

–60

–60 –50 –40 –30 –20 –10 0 10

5.1

VHF

f

RF=100MHz (VHF)

fRF=450MHz (UHF)
fIF is both f=45MHz

—17—

CXA3235/3236N

Conversion gain vs. Reception frequency (Untuned input)

CG - Conversion gain [dB]

PCS beat characteristics

IF output level [dBm]

SG output level [dBm]

(fP level)

Noise figure vs. Reception frequency (Untuned input, in DSB)

NF - Noise figure [dB]

Reception frequency [MHz]

Next adjacent cross modulation vs. Reception frequency

(Untuned input)

CM - Cross modulation [dBµ]

Reception frequency [MHz]

Oscillation frequency power supply fluctuation (PLL off)

+B drift [kHz]

Oscillation frequency [MHz]

Reception frequency [MHz]

fIF=45MHz

40
35
30
25
20
15
10

5
0

VHF (Low) VHF (High)

UHF

0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900

20

15

10

5

0

VHF (Low)

VHF (High)

UHF

fIF=45MHz

120

100

80

60

40

20

0

fUD=fD+12MHz
f

UD=fD–12MHz

(100kHz, 30% AM)

0 100 200 300 400 500 600 700 800 900

fIF=45MHz

400
300
200
100

0
–100
–200
–300
–400

0 100 200 300 400 500 600 700 800 900

VHF (Low)

VHF (High)

(V

CC=5V)

V

CC+5%

V

CC–5%

UHF

fIF

fBeat

+20

+10

0

–10

–20

–30

–40

–50

–60

–70

–80

–30 –20 –10 0 +10 +20

fLocal=129MHz
fP=83.25MHz
fC=86.83MHz, (fP–12dB)
fS=87.75MHz, (fP–1.7dB)
fIF=45.75MHz
fBeat=fIF±920kHz

—18—

CXA3235/3236N

VHF (Low) 95MHz → VHF (High) 395MHz

UHF 413MHz → UHF 847MHz

5.0V/div
offset 10.0V

T=70ms

–90,0000ms

10,0000ms

20.0ms/div

110,000ms

T=70ms

5.0V/div
offset 10.0V

–90,0000ms

10,0000ms

20.0ms/div

110,000ms

Tuning Response Time

—19—

CXA3235/3236N

IF output spectrum

IF output spectrum

VHF (Low)
fRF=55MHz
fLO=100MHz

RF input level : –40dBm

RL=0dBm

10dB/div

CENTER 45.0MHz

RES BW 1.0kHz

VBW 10Hz

SPAN 100.0kHz

SWP 30.0s

RF input level : –40dBm

RL=0dBm

10dB/div

VHF (High)
fRF=350MHz
fLO=395MHz

CENTER 45.0MHz

RES BW 1.0kHz

VBW 10Hz

SPAN 100.0kHz

SWP 30.0s

—20—

CXA3235/3236N

IF output spectrum

RF input level : –40dBm

RL=0dBm

10dB/div

UHF (Low)
fRF=800MHz
fLO=845MHz

CENTER 45.0MHz

RES BW 1.0kHz

VBW 10Hz

SPAN 100.0kHz

SWP 30.0s

—21—

CXA3235/3236N

12 13

MS

j100

j50

j25

0

50

–j25

–j50

–j100

350MHz

50MHz

1000p

S11

VHFin

j100

j50

j25

0

50

–j25

–j50

800MHz

–j100

350MHz

1000p

S11

UHFin1

UHFin2

14 15

VHF Input Impedance

UHF Input Impedance

—22—

CXA3235/3236N

j100

j50

j25

0

50

45MHz

–j25

–j50

–j100

IF output Impedance

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT

LEAD MATERIAL
PACKAGE MASS

EPOXY RESIN
SOLDER/PALLADIUM

42/COPPER ALLOY

30PIN SSOP (PLASTIC)

∗9.7 ± 0.1

∗5.6 ± 0.1

0.65

0.22 – 0.05

30

1 15

16

1.25

+ 0.2
– 0.1

7.6 ± 0.2

0.15

+ 0.05
– 0.02

0.1 ± 0.1

0.5 ± 0.2

0° to 10°

A

DETAIL A

SSOP-30P-L01
SSOP030-P-0056

0.1g

NOTE: Dimension “∗” does not include mold protrusion.

PLATING

0.10

0.13

M

+ 0.1

Package Outline Unit : mm

CXA3235/3236N

—23—

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).