Page 1
—1—
E90167J04-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD 7V
• Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5 V
• Input voltage VIN VDD + 0.5 to VSS – 0.5 V
(Analog)
• Input voltage VI VDD + 0.5 to VSS – 0.5 V
(Digital)
• Output voltage VO VDD + 0.5 to VSS – 0.5 V
(Digital)
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25 V
DVDD, DVSS
| DVSS – AVSS | 0 to 100 mV
• Reference input voltage
VRB 0 to V
VRT to 2.7 V
• Analog input VIN 1.8Vp-p above
• Clock pulse width
Tpw1, Tpw0 22.5 ns (min) to 1.1 µs (max)
• Operating ambient temperature
Topr –40 to +85 °C
Description
The CXD1176Q is an 8-bit CMOS A/D converter
for video use that features a sync clamp function. The
adoption of a 2 step-parallel method realizes low
power consumption and a maximum conversion
speed of 20MSPS.
Features
• Resolution power: 8-bit ± 1/2LSB (DL)
• Maximum sampling frequency: 20MSPS
• Low power consumption: 60mW (at 20MSPS typ.)
(Reference current excluded)
• Built-in sync type clamp function
• Built-in monostable multivibrator for clamp pulse
generation
• Built-in sync pulse polarity selection function
• Clamp pulse direct input possible
• Built-in clamp ON/OFF function
• Built-in reference voltage self-bias circuit
• Input CMOS compatible
• 3-state TTL compatible output
• Single 5 V power supply
• Low input capacity: 11 pF
• Reference impedance: 330 Ω (typ.)
Applications
TV and VCR digital systems and a wide range of
applications where high-speed A/D conversion is
required.
Structure
Silicon gate CMOS IC
8-bit 20MSPS Video A/D Converter with Clamp Function
32 pin QFP (Plastic)
CXD1176Q
Page 2
—2—
CXD1176Q
Block Diagram and Pin Configuration
2
3
4
5
6
7
8
10
11
12
9
30
31
32
1
Clock generator
Upper
data
latch
Lower
data
latch
Lower encoder
(4 BIT)
Lower encoder
(4 BIT)
Upper encoder
(4 BIT)
Lower sampling
comparator (4 BIT)
Lower sampling
comparator (4 BIT)
Upper sampling
comparator (4 BIT)
Reference supply
M · M
26
27
29
28
25
24
23
22
21
20
19
18
17
16
15
14
13
DVss
CCP VREFCLE
VRBS
VRB
AVss
AVss
V
IN
AVDD
AVDD
VRT
VRTS
AV
DD
PW
Sync
SEL
OE
DVss
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DV
DD
DVDD
CLK
NC
NC
Page 3
—3—
CXD1176Q
Pin Description
Pin No. Symbol Equivalent circuit Description
1 to 8
D0 to D7
CLK
SEL
Sync
D0 (LSB) to D7 (MSB) output
Clock input
When SEL is at low, with the falling
edge of Pin 14 (sync) as trigger, the
monostable multivibrator generates
clamp pulses.
When SEL is at high, with the rising
edge of Pin 14 (sync) as trigger, it
generates clamp pulses.
Trigger pulse input to the monostable
multivibrator.
Trigger polarity can be selected
through Pin 13 (SEL).
12
13
14
Di
DVDD
DVSS
12
DVDD
DVSS
14
9, 32
NC
NC pin
10, 11
DVDD
Digital +5 V
DVDD
DVSS
13
Page 4
—4—
CXD1176Q
15
PW
18
VRT
24
VRB
21 VIN
25
VRBS
17
VRTS
When a clamp pulse is generated at
the monostable multivibrator, the
pulse width is determined by the
external R and C.
When the clamp pulse is directly
input, it is input to Pin 15 (PW). The
signal voltage of the low period is
clamped. (Here, Pin 14 (sync) is fixed
to either low or high.)
When shorted with VRT, generates
approx. +2.6 V.
Reference voltage (top)
Reference voltage (bottom)
Analog input
When shorted with VRB, generates
approx. +0.5 V.
Pin No. Symbol
Equivalent circuit Description
22, 23
AVSS
16, 19, 20 AVDD
17
AV
DD
18
24
AV
DD
AVSS
21
AV
DD
AVSS
25
AVSS
Analog +5 V
Analog ground
15
DV
DD
DVSS
Page 5
—5—
CXD1176Q
Pin No. Symbol Equivalent circuit Description
26 VREF
CCP
CLE
OE
Clamp reference voltage input.
Clamps to provide a clamp period
input signal equal to the reference
voltage.
Integrates the voltage for clamp
control.
CCP and VIN voltage changes are in
positive phase.
When CLE is at low, clamp function is
activated.
When CLE is at high, clamp function
is OFF and only the usual A/D
converter function is active.
By connecting CLE pin to DVDD via a
several hundred Ω resistance, the
clamp pulse can be tested.
When OE is at low, Data is output.
When OE ia at high, D0 to D7 pins
turn to high impedance.
27
29
30
26
AV
DD
AVSS
27
AV
DD
AVSS
29
CLAMP
PULSE
DV
DD
DVSS
30
DV
DD
DVSS
28, 31
DVSS
Digital ground.
Page 6
—6—
CXD1176Q
Digital Output
Correspondence between the analog input voltage and the digital output code is indicated in the chart below.
tr = 4.5ns tf = 4.5ns
2.5V
tPLZ
tPHZ
10%
90%
tPZH
1.3V
1.3V
tPZL
10%
90%
5V
0V
V
OH
VOL (≠ DVSS)
V
OH (≠ DVDD)
V
OL
OE input
Output 1
Output 2
Input signal
voltage
Step
Digital output code
MSB LSB
VRT
.
.
.
.
.
.
.
.
.
.
.
.
VRB
0
.
.
.
127
128
.
.
.
255
1 1 1 1 1 1 1 1
.
.
.
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
.
.
.
0 0 0 0 0 0 0 0
Timing Chart. I
Timing Chart. II
Clock
Analog input
Data output
TPW1 TPW0
N
N – 3 N – 2 N – 1 N N + 1
N + 1
N + 2
N + 3
N + 4
Td = 18ns
: Points where analog signals are sampled.
Page 7
—7—
CXD1176Q
Electrical Characteristics
Analog characteristics (Fc = 20 MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C)
Conversion speed
Analog input band width
(–1dB)
Offset voltage
∗1
Integral non-linearity error
Differential non-linearity erro
r
Differential gain error
Differential phase error
Aperture jitter
Sampling delay
Clamp offset voltage
∗2
Clamp pulse width
(Sync pin input)
Clamp pulse delay
Fc
BW
EOT
EOB
EL
ED
DG
DP
taj
tsd
Eoc
tcpw
tcpd
0.5
–60
+20
0
–50
1.75
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
VIN = 0.5 to 2.5 V
fIN = 1 kHz ramp
Envelope
Potential difference to VRT
Potential difference to VRB
End point
NTSC 40 IRE mod ramp
Fc = 14.3 MSPS
VIN = DC,
PWS = 3 µs
C = 100 pF,
R = 130 kΩ (15 PIN)
18
–40
+40
+0.5
±0.3
1.0
0.5
30
4
+20
–30
2.75
25
20
–20
+60
+1.3
±0.5
+40
–10
3.75
MSPS
MHz
mV
LSB
%
deg
ps
ns
mV
µs
ns
Item Symbol Conditions Min. Typ. Max. Unit
VREF = 0.5 V
VREF = 2.5 V
∗1
The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”.
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2LSB of the voltage when the output data changes from “11111111” to “11111110”.
∗2
Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be
generated.
Page 8
—8—
CXD1176Q
DC characteristics
(Fc = 20 MSPS, VDD = 5 V, VRB = 0.5 V, VRT = 2.5 V, Ta = 25 °C)
Supply current
Reference pin current
Analog input capacitance
Reference resistance
(VRT to VRB)
Self-bias I
Self-bias II
Digital input voltage
Digital input current
Digital output current
IDD
IREF
CIN
RREF
VRB1
VRT1 to VRB1
VRT2
VIH
VIL
IIH
IIL
IOH
IOL
IOZH
IOZL
4.5
230
0.48
1.96
4.0
–1.1
3.7
Fc = 20 MSPS
NTSC ramp wave input
VIN = 1.5 V + 0.07 Vrms
VRB and VRBS are shorted
VRT and VRTS are shorted
VRB = AGND
VRT and VRTS are shorted
VDD = 4.75 to 5.25 V
Ta = –40 to +85 °C
VDD = max
OE = VSS
VDD = min
OE = VDD
VDD = max
12
6.6
11
300
0.52
2.08
2.32
18
8.7
450
0.56
2.22
1.0
5
5
16
16
mA
mA
pF
Ω
V
V
V
µA
mA
µA
Item Conditions Min. Typ. Max. Unit
Timing
(Fc = 20 MSPS, VDD = 4.75 to 5.25 V, VRB = 0.5 V, VRT = 2.5 V, Ta = –40 to +85 °C)
Output data delay
Tri-state output
enable time
Tri-state output
disable time
TDL
tPZH
tPZL
tPHZ
tPLZ
2.5
8
with TTL 1 gate and 10pF load
RL = 1kΩ, CL = 20 pF
OE = 3 V → 0 V
RL = 1 kΩ, CL = 20 pF
OE = 0 V → 3 V
18
6
18
30
10
30
ns
ns
ns
Item Symbol Conditions Min. Typ. Max. Unit
VIH = VDD
VIL = 0V
VOH = VDD – 0.5 V
VOL = 0.4V
VOH = VDD
VOL = 0V
Page 9
—9—
CXD1176Q
Electrical Characteristics Measurement Circuit
Integral non-linearity error
Differential non-linearity error }measurement circuit
Offset voltage
+V
–V
A < B A > B
COMPARATOR
A8
to
A1
A0
B8
to
B1
B0
DUT
CXD1176Q
BUFFER
S1
S2
S1: ON
IF A < B
S2: ON IF B > A
88
CONTROLLER
DVM
8
000 · · · 00
to
111 · · · 10
CLK (20MHz)
VIN
“0” “1”
Maximum operational speed
Differential gain error }measurement circuit
Differential phase error
S.G.
NTSC
SIGNAL
SOURCE
S.G.
(CW)
CXD
1176Q
10bit
D/A
VECTOR
SCOPE
COUNTER
H.P.F
TTL
ECL
AMP
TTL
ECL
FC
1
2
V
IN 8 8
620
–5.2V
CLK
620
–5.2V
1
2
CX20202A-1
ERROR RATE
D.G
D.P.
40 IRE
MODULATION
100
0
–40
SYNC
0.5V
2.5V
IAE
BURST
2.5V
0.5V
Fc – 1kHz
Digital output current measurement circuit
VDD
VRT
VIN
VRB
CLK
OE
GND
2.5V
0.5V
VOH
+
–
I
OH
VDD
VRT
VIN
VRB
CLK
OE
GND
VOL
+
–
I
OL
2.5V
0.5V
DVDD
RL
RL
To output pin
Measurement
point
C
L
Tri-state output measurement circuit
Note) CL includes capacitance of the probe and others.
Page 10
—10—
CXD1176Q
S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4)
MD (0) MD (1) MD (2) MD (3)
RV (0) RV (1) RV (2) RV (3)
S (1) C (1) S (3) C (3)H (3)H (1)
LD (–1) LD (1)
C (0) S (2) C (2) S (4)H (0) H (2) H (4)
LD (–2) LD (0) LD (2)
Out (–2) Out (–1) Out (0) Out (1)
Vi (1) Vi (2) Vi (3) Vi (4)
Analog input
External clock
Upper comparators block
Upper data
Lower reference voltage
Lower comparators A block
Lower data A
Lower comparators B block
Lower data B
Digital output
Timing Chart 3
Operation (See Block Diagram and Timing Chart 3)
1. The CXD1176Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2
lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT –
VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper
data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self
generation of VRT (Reference voltage top) and VRB (Reference voltage bottom).
Page 11
—11—
CXD1176Q
2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It
features the following operating modes which are respectively indicated on the timing chart with S, H, C
symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.
3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled
with the falling edge of the first clock by means of the upper comparator block and the lower comparator A
block.
The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to
the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the
second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes
1. VDD, VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital
and analog VDD pins, use a ceramic capacitor of about 0.1 µF set as close as possible to the pin to bypass
to the respective GND’s.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be
prevented by inserting a resistance of about 100 Ω in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1 µF, stable characteristics are obtained. By shorting
VRT and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6 V and VRB = 0.6 V, is activated.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks
and with the following rising edge. The delay from the clock rising edge to the data output is about 18 ns.
6. OE pin
By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.
7. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply.
This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
Page 12
—12—
CXD1176Q
Application Circuit
(1) Case where clamp pulse is directly input (self-bias used)
2
3
4
5
6
7
8
10
11
12
13
1415
16
17
18
19
20
21
22
23
24
25
26
27
28
32
1
D6
0.1µ
LATCH
CK
Q
∗
0.01µ
CLAMP PULSE IN
CLOCK IN
HCO4
+5V (Analog)
VIDEO IN
75Ω
10µ
0.1µ
10P
+5V (Analog)
0.01µ
VREF
20k
GND (Analog)
29
30
31
0.01µ
GND (Digital)
9
+5V (Digital)
D7
D6
D5
D4
D3
D2
D1
D0
∗
The clamp pulse is latched by the ADC sampling clock, but that is not necessary for clamp basic operation.
However, slight beat may be generated as vertical sag according to the relation between the sampling
frequency and clamp pulse frequency.
At such time, the latch circuit is effective. (See page 20 Notes on Operation 5.)
(2) Example where pedestal clamp is executed by sync pulse (self-bias used)
2
3
4
5
6
7
8
10
11
12
14
16
17
18
19
20
21
22
23
24
25
26
27
28
32
1
0.1µ
LATCH
CK
Q
∗
0.01µ
HCO4
75Ω
10µ
0.1µ
10P
0.01µ
VREF
20k
29
30
31
0.01µ
9
13
15
+5V (Analog)
+5V (Analog)
GND (Analog)
GND (Digital)
SYNC IN
CLOCK IN
VIDEO IN
+5V (Digital)
D7
D6
D5
D4
D3
D2
D1
D0
Page 13
—13—
CXD1176Q
(3) Digital clamp (self-bias used)
2
3
4
5
6
7
8
9
10
11
12
13
16
17
18
19
20
21
22
23
24
25
26
27
28
32
1
+5V (Digital)
0.1µ
OPEN
0.01µ
CLOCK IN
HCO4
+5V (Analog)
VIDEO IN
75Ω
10µ
0.1µ
10P
0.01µ
GND (Analog)
29
30
31
GND (Digital)
DAC,
PWM,
etc.
Latch,
Subtracter,
Comparator,
etc.
1415
CLAMP
PULSE IN
Clamp Level
setting data
(4) When clamp is not used (self-bias used)
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27
28
32
1
0.1µ
0.01µ
CLOCK IN
HCO4
+5V (Analog)
VIDEO IN
75Ω
0.1µ
10P
0.01µ
GND (Analog)
29
30
31
GND (Digital)
+5V (Digital)
9
+5V (Digital)
D7
D6
D5
D4
D3
D2
D1
D0
Page 14
—14—
CXD1176Q
8-bit 20MSPS ADC and DAC Evaluation Board
Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD1176Q (8bit 20MHz A/D) and CXD1171M (8-bit 40MHz D/A).
The evaluation board is composed of a main board common to either type, to which is added sub board
CXD1176Q or sub board CXD1171M. The junction is made through a socket.
To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is
mounted CXD1176Q and CXD1171M respectively. Those IC’s are mounted according to recommended print
patterns designed to provide maximum performance to the A/D and D/A converters.
Block Diagram
ANALOG CIRCUIT
MOUNT PORTION
ANALOG INPUT
INTERFACE
ANALOG CIRCUIT
MOUNT PORTION
V REF
ADC
SOCKET
DAC
SOCKET
CLOCK
BUFFER
DATA LATCH
OSC
DIGITAL
CIRCUIT MOUNT
PORTION
–5V+5VGND CLOCK OE SEL SYNC CLE BLK
VOUT
SW
8
8
4
Unnecessary
at self-bias use
V
IN
Characteristics
• Resolution 8 bit
• Maximum conversion rate 20 MHz
• Digital input level CMOS level
• Supply voltage ±5.0 V (Single +5 V power supply possible at self bias use)
Supply voltage
Item
+5 V
–5 V
150
20
mA
Min. Typ.
Max. Unit
Clock input
CMOS compatible
Pulse width TCW1 22.5 ns (min)
TCW0 22.5 ns (min)
Page 15
—15—
CXD1176Q
Analog Output (CXD1171M) (RL > 10 kΩ)
Item
Analog output 1.9 2.0 2.1 V
Min. Typ. Max. Unit
Output Format (CXD1176Q)
The table shows the output format of AD Converter.
Analog input
voltage
VRT
.
.
.
.
.
.
.
.
.
.
.
.
VRB
0
.
.
.
127
128
.
.
.
255
1 1 1 1 1 1 1 1
.
.
.
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
.
.
.
0 0 0 0 0 0 0 0
Step
Digital output code
MSB LSB
tPD (DA)
ts
th
tDD
tPD (AD)
Tdc
Tpw1
Tpw0
Analog input
External clock
AD clock
AD output
Latch output
DA input
DA clock
DA output
Timing Chart
Item
Clock High time
Clock Low time
Clock Delay
Data delay AD
Data delay (latch)
Set up time
Hold time
Data delay DA
TPW1
TPW0
Tdc
tPD (AD)
tDD
tS
th
tPD (DA)
25
25
5
10
Symbol Min.
18
10
Typ.
24
30
5
Max.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Page 16
—16—
CXD1176Q
NCNCAVSSAVSS
IREF
VREF
AVDDAVDD
IOIONC
DV
DD
NC
DV
SS
CLK
BLK
D7
D6
D5D4D3D2D1
D0
CLK
DV
DD
D7
D6
D5D4D3
D2D1D0
DV
SS
OE
PWNCNC
V
RT
AVDD
AVDD
VIN
AVSS
AVSS
VRB
VREF
CLE
R8 3.3k
(16R)
R7 200
(R)
V out
VR4
20k
OUTPUT
GAIN
ADJUST
13
14
15
16
17
18
19
20
21
22
23
24
Q2
R5
510
VR2
2k
AV
DD
VRT
ADJUST
Q1
VR1
2k
R6
510
R4
510
VRB
ADJUST
SW1
SW2
C3
0.01
C4
0.01
SW3
VR3
20k
AVDD
R3
33
C2
10µ
R2
75
AVSS
Q3
C1
470µ
R1
100k
VIDEO INPUT
CLAMP
VOLTAGE
ADJUST
47µ
AVSS
74S174
(LATCH)
DV
DD
0.01µ
0.01µ
0.01µ
13
14
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DV
DD
CLK
DV
DD
CLK DVSS
CLEAR
DV
SS
CLEAR
DV
SS
2
3
4
5
6
7
1
8
9
10
11
12
13
14
2
3
4
5
6
7
8
1
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
1
9
10
11
12
13
14
15
16
74S174
(LATCH)
74S04
OR
74HC04
(INV BUFFER)
C5
0.1
OSC SWITCH
EXT/INT
BLK
SYNC
OE
SEL
CLE
R9
75
R10
75
47µ
7
1
DV
SS
14
0.01µ
DV
DD
EXTERNAL CLOCK
INPUT
0.01
DVDD
DVSS
DVDD
DVSS
OSC out
VR5
20k
SEL
SYNC
V
RTS
VRBS
47µ
8
(R
IN = 75Ω)
SYNC INT
DV
DD
AV
DD
GND
+5V
–5V
CMOS ADC/DAC Peripheral Circuit Board (Main Board)
Page 17
—17—
CXD1176Q
CMOS ADC/DAC Peripheral Circuit Board (Sub Board)
NC
CXD1176Q
2
3
4
5
6
7
8
1
C3
0.1µ
C5
C2 0.1µ
25
26
27
28
29
30
31
32
C1 0.01µ
17
18
19
20
21
22
23
24
CXD1171M
C1
C4
9
10
11
12
2
3
4
5
6
7
8
1
C2C3
13
14
15
16
17
18
19
20
21
22
23
24
9
10
11
12
2
3
4
5
6
7
8
1
13
14
17
18
19
20
21
22
23
24
15
16
9
10
11
12
13
14
2
3
4
5
6
7
8
1
9
10
11
12
13
1415
16
17
18
19
20
21
22
23
24
15
16
25
26
27
28
SYNC
SEL
CLK
DV
DD
D7
D6
D5
D4
D3
D2
D1
D0
DV
SS
OE
PW
NC
V
RTS
VRT
AVDD
AVDD
VIN
AVSS
AVSS
VRB
VRBS
VREF
CLE
NC
DV
SS
CLK
BLK
D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
AV
SS
AVSS
IREF
VREF
AVDD
AVDD
IO
IO
NC
DV
DD
Page 18
—18—
CXD1176Q
List of Parts
resistance
R1 100 kΩ
R2 75 Ω
R3 75 Ω
R4 510 Ω
R5 510 Ω
R6 510 Ω
R7 R = 200 Ω
R8 18R ≈ 3.3 kΩ
R9 75 Ω
R10 75 Ω
VR1 2 kΩ
VR2 2 kΩ
VR3 20 kΩ
VR4 20 kΩ
VR5 20 kΩ
capacitance
C1 470 µF/6.3 V (chemical)
C2 10 µF/16 V (chemical)
C3 0.01 µF
C4 0.01 µF
C5 0.1 µF
C6 0.1 µF
C7 0.1 µF
C8 0.1 µF
C9 0.1 µF
C10 0.1 µF
C11 47 µF/10 V (chemical)
C12 47 µF/10 V (chemical)
C13 47 µF/10 V (chemical)
C14 0.1 µF
transistor
Q1 2SC2785
Q2 2SC2785
Q3 2SC2785
IC
IC1 74S174
IC2 74S174
IC3 74S04
oscillator
OSC
others
connector BNC071
SW AT1D2M3
Adjustment
1. Vref adjustment (VR1, VR2)
Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2.
When self-bias is used, there is no need for adjustment. Reference voltage is set through self-bias delivery.
2. Setting of clamp reference voltage (VR3)
Clamp reference voltage is set.
3. DAC output full-scale adjustment (VR4)
Full-scale voltage of D/A converter output is adjusted at the PCB shipment, the full-scale voltage is
adjusted to approx. 2 V.
4. Sync (clamp) pulse interface (VR5)
This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is
performed to obtain a threshold of approx. 2.5 V to an H sync of 0 to 5 V.
Page 19
—19—
CXD1176Q
5. OE, SEL, Sync, BLK, CLE, Sync INT
The following pins are set on the main board: OE, SEL, Sync, CLE, Sync INT (CXD1176Q) and BLK
(CXD1171M). For the pins function, refer to the specifications. The difference between Sync pin and Sync
INT pin is that you input a horizontal synchronizing signal above 3.5 Vp-p Sync INT pin. The pulse
threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case
cut off the junction line between Sync and Sync INT pin.
At the PCB shipment the main board pins are set as follows.
• OE ... Low (A/D output ON)
• SEL ... Low (Pulse generated with Sync falling edge as trigger)
• Sync ... Line junction with Sync INT pin
• CLE ... Low (Clamp function ON)
• BLK ... Low (Blanking OFF)
6. Clamp pulse input method
One method, as shown in Application Circuit examples (1) and (2), is to directly input the clamp pulse. The
other is to use the built-in monostable multivibrator. The method is selected through SW1. At the PCB
shipment it is set to direct input. To use the built-in monostable multivibrator, it is necessary to mount on
the CXD1176Q sub board, R and C that determine pulse width.
(Ex. R = 130 k, C = 100 p, Tpw = 2.75 µs Typ.)
Points on the PCB Pattern Layout
1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, See p. 23 Component side
diagram.)
2. At CXD1176Q sub board, C2 and C3 capacitors serve the important role of bringing out CXD1176Q’s full
performance.
There are over 0.1 µF (ceramic) capacitors with good high frequency characteristics. Layout as close to
the IC as possible.
3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage and power source. Keeping ADC’s
DVSS (Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout
where ADC is close to the voltage supply source, is recommended. (For 2, see p. 23 Component side
diagram.)
4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should
not have any jitter.
5. The PCB layout shows ADC and DAC’s Analog GND independently from the voltage generating source.
On this PCB, the layout aims at providing an independent evaluation of ADC and DAC, as much as
possible. On the actual board, common use will not cause any problems.
Page 20
—20—
CXD1176Q
Notes on Operation
1. Reference voltage
Shorting VRT and VRTS, VRB and VRBS will activate the self-bias function that generates VRT = 2.6 V and
VRB = 0.5 V. On the PCB, either self-bias or the external reference voltage can be selected depending on
the junction method of the jumper line. At shipment from the factory, reference voltage is provided in selfbias. Also, to provide external reference voltage, adjust the dynamic range (VRT – VRB) to above 1.8 Vp-p.
2. Clock input
There are 2 modes for the PCB clock input
1) Provided from the external signal generator. (External clock)
2) Using the crystal oscillator (built-in clock driver). (Internal clock)
The 2 modes are selected using the switch on the PCB.
3. The 2 Latch IC’s (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is,
operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output
data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate
an example layout of Digital signal processing IC.
4. When clamp is not used
Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2
on the main board and DC voltage on the ADC side of C2 turns to about 1/2 (VRT + VRB). To transfer DC
elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open,
Q3 can also be used as buffer. Use the open space for the bias circuit.
5. Clamp pulse latch
On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to either PW
pin or Sync pin. This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements
with GND sampling clock around ADC. If there are no problems with Vsag, latch is not necessary.
6. Peripheral through hole
There is a group of through holes on the Analog input, output and Logic. There are to be used when
mounting additional circuits to the PCB. Use when necessary.
The connector hole on DAC part is used to mount the test chassis and the mount jack.
Page 21
—21—
CXD1176Q
Latch Up Prevention
The CXD1176Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pins 16, 19 and 20) and DVDD (Pin 10 and 11), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
10
11
16
19
20
22
23
28
31
AVDD
+5V
C6
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD1176Q
C14
DV
DD
DIGITAL IC
+5V
b. When analog and digital supplies are from a common source
(i)
10
11
16
19
20
22
23
28
31
C6
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD1176Q
C14
DVDD
DIGITAL IC
+5V
10
11
16
19
20
22
23
28
31
C6
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD1176Q
C14
DVDD
DIGITAL IC
+5V
(ii)
Page 22
—22—
CXD1176Q
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
10
11
16
19
22
23
28 31
AV
DD
+5V
C6
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD1176Q
DV
DD
DIGITAL IC
20
+5V
b. When analog and digital supplies are from a common source
(i)
10
11
16
19
20
22
23
28 31
+5V
C6
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD1176Q
DV
DD
DIGITAL IC
AVDD
10
11
16
19
20
22
23
28
31
+5V
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD1176Q
DVDD
DIGITAL IC
AVDD
(ii)
Page 23
—23—
CXD1176Q
Component Side
Soldering Side (Diagram seen from the component side)
Silk Side
Page 24
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 ALLOY
32PIN QFP (PLASTIC)
9.0 ± 0.2
7.0 – 0.1
1.5 – 0.15
(8.0)
0.1 – 0.1
+ 0.2
+ 0.35
+ 0.3
0.50
0.127 – 0.05
+ 0.1
0° to 10°
0.8
0.3 – 0.1
+ 0.15
1
8
9
32
16
1724
25
M
0.24
0.2g
QFP-32P-L01
QFP032-P-0707
0.1
Package Outline Unit : mm
CXD1176Q
—24—
Page 25
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
42 / COPPER ALLOY
32PIN QFP (PLASTIC)
9.0 ± 0.2
7.0 – 0.1
1.5 – 0.15
(8.0)
0.1 – 0.1
+ 0.2
+ 0.35
+ 0.3
0.50
0° to 10°
0.8
b
1
8
9
32
16
1724
25
M
0.24
0.2g
QFP-32P-L01
QFP032-P-0707
0.1
b = 0.30 – 0.10
( 0.30)
(0.127)
+ 0.15
DETAIL A : SOLDER
b = 0.30 ± 0.03
0.125 ± 0.04
DETAIL A : PALLADIUM
A
0.127 – 0.05
+ 0.10
Package Outline Unit : mm
CXD1176Q
—25—
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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