Datasheet CXA3572R Datasheet (Sony)

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Page 1

CXA3572R

Driver/Timing Generator for Color LCD Panels

Description

The CXA3572R is an IC designed to drive the color

LCD panel ACX306/312.

This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals and a VCO onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc.

Features

• Color LCD panel ACX306/312 driver

• Supports NTSC and PAL systems

• Supports Y/color difference and RGB inputs

• Supports OSD input

• Power saving function (clock stopped)

• Various setting control using a serial interface

circuit (asynchronous type)

• Electronic attenuators (D/A converter)

• VCO (no external oscillator circuit)

• LPF (fc variable)

• COMMON and PSIG output circuits

• Sharpness function

• 2-point γ correction circuit

• R, G, B signal delay time adjustment circuit

• Sync separation circuit

• D/A output pin (0 to 3V, 8 level output)

• Output polarity inversion circuit

• Supports AC drive for LCD panel during no signal

Applications

Compact LCD monitors, etc.

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC1 5.5 V

• Analog input pin voltage

VINA1 (Pins 18, 19, 20, 22, 23, 24 and 25)

VINA2 (Pin 16) GND – 0.3 to VCC2 + 0.3 V

• Digital input pin voltage VIND (Pins 34 and 35) VSS – 0.3 to +5.5 V

• Common input pin voltage VINAD (Pins 31, 32 and 33)

• Operating temperature Topr –15 to +75 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipation (Ta ≤ 25°C)

Operating Conditions

• Supply voltage VCC1 – GND1 2.7 to 3.6 V

48 pin LQFP (Plastic)

VCC215 V VDD 4.6 V

GND – 0.3 to VCC1 + 0.3 V

GND , VSS – 0.3 to +5.5 V

PD 600 mW

VCC2 – GND2 11.0 to 14.0 V VDD – VSS 2.7 to 3.6 V

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E00Y05A11-PS

Page 2

Block Diagram

CXA3572R

SYNC IN

DA OUT

REF

FILTER

RPD

GND1

SEN

SCK

SDAT

XCLR

POF

B/B-Y

R/R-Y

G/Y

+3V

OSD G

OSD R

OSD B

SIG.C

PSIG DC DET

PSIG OUT

+12V

131415161718192021222324

PICTURE Gain

ATT

LPF

TRAP

REF

LPF

SUBCONTRAST

TRAP

SUB-

R, G, B

CONTRAST

CONT R

SUB-

CONT B

PHASE COMPARATOR

30 31

DAC

SERIAL I/F

PICTURE

HUE COLOR

COLOR

HUE

SYNC SEP

CLOCK GENERATOR

PICTURE f0

MATRIX

USERBRIGHT

SYNC SEL

VCO ADJ

Fine

GAMMA1 GAMMA2

VCO ADJ

Coarse

HD_

MODE

γ2

γ1

Analog block 3V

BLK

CSYNC

SUBBRIGHT

R-

XCLP

BRIGHT

S/H

BLIM

SH1

FRP

B-

BRIGHT

SH2

PSIGBRIGHT

PSIG-

BRIGHT

OSD

BLIM

COM

SH4

SH3

PSIG

PowerSW

XSTBY1

COM

Analog block 12V

XSTBY2

FRP

G OUT

G DC DET

R OUT

R DC DET

B OUT

B DC DET

COM

GND2

Digital block 3V

TEST

SERIAL I/F

34 35

PLL COUNTER

TIMING GENERATOR

H. FILTER

VST

VCK

+3V

37 38 39 40 41 42 43 44 45 46 47 48

HDO

VDO

RGT

HCK1

HCK2

HST

WIDE

DWN

– 2 –

Page 3

Pin Description

CXA3572R

Pin No.

VCK

VST

TEST

GND2

COM

B DC DET

B OUT

R DC DET

R OUT

G DC DET

G OUT

VCC2

PSIG OUT

PSIG DC DET

SIG.C

Symbol

I/O

EN pulse output

V clock pulse output

V start pulse output

—

Test (Leave this pin open.)

—

Analog 12.0V GND

Common pad voltage output for LCD panel

B signal DC voltage feedback circuit capacitor connection

B signal output

R signal DC voltage feedback circuit capacitor connection

R signal output

G signal DC voltage feedback circuit capacitor connection

G signal output

—

Analog 12.0V power supply

PSIG output

PSIG signal DC voltage feedback circuit capacitor connection

R, G, B and PSIG output DC voltage adjustment

Description

Input pin for open status

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

NC OSD B OSD R OSD G VCC1 G/Y R/R-Y B/B-Y SYNC IN DA OUT REF FILTER RPD GND1 SEN SCK SDAT VD

—

OSD B input

OSD R input

OSD G input

—

Analog 3.0V power supply

G/Y signal input

R/R-Y signal input

B/B-Y signal input

Sync separation circuit input/sync signal input

DAC output

Level shifter circuit REF voltage output for LCD panel

Internal filter circuit f0 adjusting resistor connection

Phase comparator output

—

Analog 3.0V GND

Serial load input

Serial clock input

Serial data input

Vertical sync signal input

35 36

XCLR POF

Power-on reset capacitor connection (timing output block) LCD panel power supply on/off

(Leave this pin open when not using this function.)

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CXA3572R

Pin No.

37 38 39 40 41 42 43 44 45 46 47 48

Symbol

VDD HDO VDO RGT

V HCK1 HCK2 HST VDD WIDE DWN VSS

I/O

—

Digital 3.0V power supply

HDO pulse output

VDO pulse output

Right/left inversion switching signal output

—

Digital 3.0V GND

H clock pulse 1 output

H clock pulse 2 output

H start pulse output

—

Digital 3.0V power supply

WIDE pulse output

Up/down inversion switching signal output

—

Digital 3.0V GND

Description

Input pin for open status

– 4 –

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Analog Block Pin Description

CXA3572R

Pin No.

Symbol

Pin voltage

5 GND2 —

6 COM —

B DC DET

R DC DET

G DC DET

PSIG DC DET

3.0V

Vcc2

GND2

Vcc2

GND2

Equivalent circuit Description

Analog 12.0V GND.

11 15

10k

125k

100k

7 9

COMMON voltage output. The output voltage is controlled by serial communication.

Smoothing capacitor connection for the feedback circuit of R, G, B and PSIG output signal DC level control. Connect a low-leakage capacitor.

B OUT 10 12 14

R OUT

G OUT

PSIG OUT

—

16 SIG.C VCC/2

Vcc2

10 12 14

GND2

Vcc2

GND2

100k

500

R, G, B and PSIG signal outputs. The DC level is controlled to match the SIG.C pin voltage. Low output in power saving mode.

Analog 12.0V power supply.13 VCC2 12.0V

R, G, B and PSIG output DC voltage

200k

setting. Connect a 0.01µF capacitor between

200k

10p

this pin and GND1. When using a SIG.C of other than Vcc2/2, input the SIG.C voltage from an external source.

No connection.17 NC —

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CXA3572R

Pin No.

18 19 20

22 23 24

Symbol Equivalent circuit Description

OSD B

OSD R

OSD G

Pin voltage

Vth1 =

VCC1 × 1/3

Vth2 =

VCC1 × 2/3

Vcc1

18 19 20

GND1

20k

OSD pulse inputs. When one of these input pins exceeds the Vth1 level, all of the outputs go to black limiter level; when an input pin exceeds the Vth2 level, only the corresponding output goes to white limiter level. Connect these pins to GND when not used.

Analog 3.0V power supply.21 VCC13.0V

G/Y R/R-Y B/B-Y

G/Y:

1.8V

R/R-Y, B/B-Y, RGB:

1.8V

Y/color difference:

Vcc1

22 23 24

GND1

In Y/color difference input mode, input the Y signal to Pin 22, the R-Y signal to Pin 23 and the B-Y signal to Pin 24. In RGB input mode, input the G signal to Pin 22, the R signal to Pin 23 and the B signal to Pin 24. Pedestal clamp these pins with external coupling capacitors.

2.0V

25 SYNC IN 0.9V

26 DA OUT —

27 REF VCC1/2

Vcc1

GND1

Vcc1

GND1

Vcc1

10k

100k

80k

15p

25k

Sync separation circuit input, or composite sync/horizontal sync signal input. During input to the sync separation circuit, input via a capacitor.

DA output. Outputs the serial data converted to DC voltage. The current driving capacity is ±1.0mA (max.).

REF output. The current driving capacity (sink) is

1.6mA (max.).

GND1

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CXA3572R

Pin No.

Symbol Equivalent circuit Description

Pin voltage

28 FILTER 1.2V

RPD

Vcc1

GND1

Vcc1

GND1

500

1k 100k

Connect a resistor between this pin and GND1 to control the internal LPF and trap frequencies. Connect a 43kΩ resistor (tolerance ±2%, temperature characteristics ±200ppm or less). This pin is easily affected by external noise, so make the connection between the pin and external resistor, and between the GND side of the external resistor and the GND1 pin as close as possible.

Phase comparator output.29 1.8V

31 32 33

SEN SCK SDAT

—

Vcc1

31 32 33

GND1

Vss

Analog 3.0V GND.30 —GND1

∗

20k

Serial clock, serial load and serial data inputs for serial communication.

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Digital Block Pin Description

CXA3572R

Pin No.

1 2

3 36 38 39 40 42 43 44 46 47

35 31 32 33

Symbol Equivalent circuit Description

Pin voltage

EN VCK VST POF HDO VDO RGT

—

Digital block outputs.

HCK1 HCK2

Vss

HST WIDE DWN

XCLR SEN SCK SDAT

—

353132

Vss

Digital block system reset, and serial clock, serial load and serial data inputs for serial communication.

VDD —

45 41

VSS —

4 TEST —

Vertical sync signal input.34 VD —

Vss

Digital 3.0V power supply.

Digital 3.0V GND. Test.

Leave this pin open.

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CXA3572R

Setting Conditions for Measuring Electrical Characteristics

Use the Electrical Characteristics Measurement Circuit on page 21 when measuring electr ical characteristics. For measurement, the digital block must be initialized and power saving must be canceled by performing Settings 1, 2 and 3 below. In addition, the serial data must be set to the initial settings shown in the table below.

Setting 1. System reset

After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. The serial bus is set to the default values.

XCLR (Pin 35)

TR > 10µs

Setting 2. Horizontal AFC adjustment

In the condition without sync input, adjust so that the HDO pulse output frequency is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz.

Setting 3. Canceling power saving mode

The power-on default is power saving mode, so clear (set all “1”) serial data PS0 and SYNC GEN.

System reset

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Serial data initial settings

CXA3572R

MSB

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

1 1

1 1 1 1 1

0 0 0 0 1 1 1 1

0 0

0 0 1 1 1

LSBADDRESS MSB LSBDA TA

0 0 1 1 0 0 1 1

0 0

1 1 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1

PSIGSW

0 1

0 0

0 0 0 0

(0)

0 0 0

USER-BRIGHT (10000000/LSB) SUB-BRIGHT R (1000000/LSB) SUB-BRIGHT B (1000000/LSB)

CONTRAST (10000000/LSB) SUB-CONTRAST R (1000000/LSB) SUB-CONTRAST B (1000000/LSB)

PSIG-BRIGHT (1000000/LSB)

0 1 0

LPFSW

(0)

BLACK-LIMITER (100000/LSB)

PICTURE-GAIN (00000/LSB)

VCO Coarse (000/LSB)

γ-1 (0000000/LSB) γ-2 (0000000/LSB)

COM-DC (1000000/LSB)

COLOR (1000000/LSB)

HUE (1000000/LSB)

VCO Fine (10000000/LSB)

PICTURE-F0 (000/LSB)

TRAP

(0)

DA (000/LSB)LPF (000/LSB)

INPUT

SEL (0)

SYNC

SEL (1)

MODE

(0)

SLSYP

SYST

(1)

(0)

SLEXVD

(1)

SLFL

(0)

SLMBK

(0)

S/H POSITION (000/LSB)

SB POSITION (100/LSB)

TEST2

(1)

SLDWN

(0)

SLFR

(0)

PONF

(1)

SLRGT

(0)

SL4096

(0)

TEST4 (00000000/LSB)

TEST1

(0)

SLCLP1

(0)

H POSITION (100000/LSB)

HDO POSITION (00000/LSB)

V POSITION (01000/LSB)

SLPOF

(0)

TEST3

(0, 0)

SLCLP0

(0)

SYNC

GEN (1)

SLWD

(0)

SLVDO

(0)

PS0

(1)

SLNTPL

(0)

SLHDO

(0)

Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to “0”.

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Page 11

Electrical Characteristics — DC Characteristics

Analog Block

(Ta = 25°C, VCC1 = VDD = 3.0V, VCC2 = 12.0V, see page 10 for the DAC)

CXA3572R

Item

Current consumption 1 (Y/color difference input)

Current consumption 2 (Y/color difference input)

Current consumption 1 (RGB input)

Current consumption 2 (RGB input)

Current consumption 1 (PS0 = 0)

Current consumption 2 (PS0 = 0)

Current consumption 1 (SYNC GEN = 0)

Current consumption 2 (SYNC GEN = 0)

B DC DET pin voltage R DC DET pin voltage G DC DET pin voltage PSIG DC DET pin voltage SIG.C pin voltage G/Y pin voltage

Symbol Measurement conditions

IRGB1

IRGB2

IPS01

IPS02

ISG1

ISG2

Measure the inflow current to Pin 21.

Measure the inflow current to Pin 13.

Measure the inflow current to Pin 21.

Measure the inflow current to Pin 13.

Measure the inflow current to Pin 21.

Measure the inflow current to Pin 13.

Measure the inflow current to Pin 21.

Measure the inflow current

to Pin 13. V7 V9 V11 V15 V16 V22

Min. Typ. Max. Unit

1.0

3.4

—

0.3

1.0

3.0

6.0

1.8 R/R-Y pin voltage 1 R/R-Y pin voltage 2 B/B-Y pin voltage 1 B/B-Y pin voltage 2

SYNC IN pin voltage REF pin voltage

(power saving mode) FILTER pin voltage OSD R, G, B input voltage SIG. C input voltage

V23 V23 V24 V24

V25 V27 V28

VSIG.C

During Y/color difference input

During RGB input During Y/color difference

input During RGB input During no input

– 11 –

GND

5.0

2.0

1.8

2.0

1.8

1.1

0.2

1.2

VCC1

6.5

Page 12

CXA3572R

Item

Y/Color difference mode Y, R-Y, B-Y signal input level 1

Symbol Measurement conditions Min. Typ. Max. Unit

∗

Y SYNC

(Y on SYNC) R-Y B-Y

∗

Y/Color difference mode Y, R-Y, B-Y signal input level 2

SYNC (Y on SYNC)

R-Y B-Y

RGB mode R, G, B signal input level 1

RGB mode R, G, B signal input level 2

∗

Y signal level (SYNC level is not included.)

∗

SYNC level of Y (G) on SYNC signal.

R, G, B SYNC

(G on SYNC) R, G, B SYNC

(G on SYNC)

∗

INPUT SEL = 0

∗

0.35

0.15

0.4

0.2

(–6dB Attenuate OFF)

0.245

0.311

0.7

INPUT SEL = 1

∗

(–6dB Attenuate ON)

0.3

0.490

Vp-p

0.622

INPUT SEL = 0 (–6dB Attenuate OFF)

∗

INPUT SEL = 1 (–6dB Attenuate ON)

∗

0.35

0.15

0.5

0.2

0.7

0.3

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Page 13

Control Signal Block (Sync signal, serial-serial signal, XCLR, digital output)

(Ta = –15 to +75°C, VCC1 = VDD = 2.7 to 3.6V)

CXA3572R

Item High level input voltage Low level input voltage High level input voltage Low level input voltage High level input current Low level input current High level input current

Symbol

VIH1 VIL1 VIH2 VIL2 | IIH1 | | IIL1 | | IIH2 |

Measurement conditions

VIN = VDD VIN = 0V VIN = VDD

Min. Typ. Max. Unit

VCC1 – 0.7

2.0 0

VCC1

0.7

VDD (VCC1)

0.7 20 20

150

µA

Low level input current High level input current Low level input current High level output voltage Low level output voltage High level output voltage Low level output voltage

∗

SYNC IN (Pin 25)

∗

SEN (Pin 31), SCK (Pin 32), SDAT (Pin 33)

∗

VD (Pin 34)

∗

XCLR (Pin 35)

∗

HCK1 (Pin 42), HCK2 (Pin 43), HST (Pin 44)

∗

EN (Pin 1), VCK (Pin 2), VST (Pin 3), POF (Pin 36), HDO (Pin 38), VDO (Pin 39), RGT (Pin 40),

| IIL2 | | IIH3 | | IIL3 | VOH1 VOL1 VOH2 VOL2

VIN = 0V VIN = VDD VIN = 0V IOH = –1.2mA IOL = 4.0mA IOH = –0.6mA IOL = 2.0mA

2.6

1.0

0.3

WIDE (Pin 46), DWN (Pin 47)

Applicable pins

∗

2, ∗3, ∗4

∗

1, ∗2

∗

(pull-down)

∗

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Page 14

CXA3572R

Electrical Characteristics

AC Characteristics

Unless otherwise specified, Settings 1 and 2, the serial data initial settings, and the following setting conditions are required. Ta = 25°C, VCC1 = 3.0V, VCC2 = 12V, GND1 = GND2 = 0V, VSS = 0V, SW8/10/12/14 = OFF, no video input, SG1 input to TP25 Note: Serial data values in the table are HEX notation.

Item Symbol

Maximum gain between input and output

Minimum gain between input and output

Inverted and non-inverted gain difference

Gain difference between R, G and B

Sub-contrast variable amount

GMAX

GMIN

∆GINV

∆GRGB

∆GSC1

∆GSC2

Serial data setting (HEX)

CONT FFh MODE 00h

CONT 00h MODE 00h

CONT 2Fh

MODE 00h CONT 2Fh

SUB-CONT

00h

SUB-CONT

7Fh

Measurement conditions Min. Typ. Max. Unit

Input SG2 (0.2Vp-p) to TP22 and measure the output amplitude at

TP12. Input SG2 (0.2Vp-p) to TP22 and

measure the output amplitude at

–6

–3

TP12. Input SG2 (0.2Vp-p) to TP22 and

measure the inverted output amplitude Vinv and the non-inverted

—

output amplitude Vninv at TP12. ∆Ginv = 20 log (Vninv/Vinv)

Input SG2 (0.2Vp-p) to TP22 (TP23, TP24), measure the non-inverted output amplitude at TP8, TP10 and TP12, and obtain the maximum and

—

minimum difference between these values.

Set CONT = 26h, input SG2 (0.2Vp-p) to TP22, and assume the non-inverted

–4

–2.0

output amplitude at TP8 and TP10 when SUB-CONT R, B = 40h, 00h and 7Fh as V1, V2 and V3, respectively . ∆Gsc1 = 20 log (V3/V1)

1.0

2.0

∆Gsc2 = 20 log (V2/V1)

±0.4

0.6

–1.0

4.0

Sub-bright variable amount

R, G, B, PSIG and COM output voltage in power saving mode

Black limiter variable amount

∆VSB1

∆VSB2

VPSO

VBL1

VBL2

SUB-BRT

R, B 00h

SUB-BRT

R, B 7Fh

BLK-LIM

00h

BLK-LIM

3Fh

Set U-BRT = 1Ah and measure the non-inverted level at TP8 and TP10 relative to the non-inverted black level at TP12 when SUB-BRT R, B = 7Fh and 00h.

Measure the R, G, B, PSIG and COM output voltages in power saving mode.

Set U-BRT = 00h, measure the non-inverted black limit level at TP12 when BLK-LIM = 00h and 3Fh, and assume the difference from the output DC voltage as VBL1 and VBL2, respectively.

– 14 –

–2.0

0.9

—

4.5

–1.4

1.4

—

2.5

5.0

–0.9

2.0

100

3.0

—

Page 15

CXA3572R

Item Symbol

White limiter variable amount

Black level difference between R, G and B

RGB and PSIG output DC voltage

DC voltage difference between RGB and PSIG

PSIG-BRT variable amount

USER-BRT variable amount

VWL

∆VB

∆Vc

VPB1

VPB2

∆UB1

∆UB2

Serial data setting (HEX)

PSIG-BRT

00h

PSIG-BRT

7Fh

U-BRT

00h

U-BRT

FFh

Measurement conditions Min. Typ. Max. Unit

Set CONT = FFh, input SG2 (0.2Vp-p) to TP22, measure the non-inverted white limit level, and obtain the

0.3

0.6 difference from the output DC voltage. Measure the non-inverted black level

at TP8, TP10 and TP12, and obtain the maximum and minimum

—

difference between these values. Measure the output DC level

(average voltage) at TP8, TP10,

5.8

6.0 TP12 and TP14.

Measure the output average voltage difference at TP8, TP10 and TP14 relative to the output average

—

voltage at TP12.

Assume the PSIG output amplitude

8.5

10.0

when PSIG-BRT = 00h and 7Fh as VPB1 and VPB2, respectively.

Measure the non-inverted black level at TP12 when U-BRT = 00h and FFh

1.0

4.5

2.0

4.8 and assume the difference from the

average voltage as ∆UB1 and ∆UB2, respectively.

1.4

2.0

1.0

300

6.2

300

—

2.5

Vp-p

Level difference between PSIG-BLK and BLK-LIM

HUE variable amount R

HUE variable amount B

Picture variable amount

Color variable amount

∆VBB

∆HUR1

∆HUR2

∆HUB1

∆HUB2

GP1

GP2

GC1

GC2

SLWD

HUE 00h

HUE 3Fh

HUE 00h

HUE 3Fh

PIC-G

00h

PIC-G

1Fh

COLOR

00h

COLOR

50h

Set BLK-LIM = 00h and measure the difference between the inverted and non-inverted black level at TP12 and TP14.

Set U-BRT = 80h, CONT = 80h, COLOR = 40h, input SG4 (56mVp-p) to TP23, input SG4 (100mVp-p) to TP24, and assume the amplitude at TP8 when HUE = 80h, 00h and 3Fh as VB1, VB2 and VB3. Similarly, assume the amplitude at TP10 as VR1, VR2 and VR3.

∆HUR1 = 20 log (VR2/VR1) ∆HUR2 = 20 log (VR2/VR1) ∆HUB1 = 20 log (VB2/VB1) ∆HUB2 = 20 log (VB2/VB1)

Set CONT = 80h, input SG3 to TP22, and measure the TP12 amplitude at f0 relative to the TP12 amplitude at 100kHz when PIC-G = 00h and 1Fh, respectively.

Input SG4 (160mVp-p) to TP23 and TP24, and assume the output amplitude at TP8 and TP10 when COLOR = 00h, 40h and 50h as V1, V2 and V3, respectively. GC1 = 20 log (V1/V2) GC2 = 20 log (V3/V2)

– 15 –

—

1.5

—

1.5

–2.5

—

0.5

—

–5

—

300

—

–2

—

2.5 dB

—

–20

—

Page 16

CXA3572R

Item Symbol

Matrix amplitude ratio

LPF characteristics

Trap characteristics

Frequency response

B-Y/ R-Y

G-Y/ R-Y

G-Y/ B-Y

fc1

fc2

fRGB

Serial data setting (HEX)

CONT 80h

COLOR 40h

LPF 01h

MODE 00h

LPF 07h

MODE 00h

TRAP 1

MODE 00h

Measurement conditions Min. Typ. Max. Unit

Assume the TP10 output when SG4 (0.1Vp-p) is input to TP23 as RR,

0.85

1.00 the TP8 amplitude when SG4 (0.1Vp-p) is input to TP24 as BB, the TP10 amplitude when SG5 (0.1Vp-p) is input to TP23 as RG,

0.41

0.51 and the TP8 amplitude when SG5 (0.1Vp-p) is input to TP24 as BG. B-Y/R-Y = RR/BB G-Y/R-Y = RG/RR

0.15

0.19 G-Y/B-Y = BG/BB

Input SG3 to TP22 and measure the frequency which results in –3dB

—

1.5

relative to the TP12 amplitude at 100kHz when LPF = 01h and 07h.

—

5.2

Set U-BRT = 30h, CONT = DFh, input SG7 (13.5MHz) to TP22, TP23 and TP24, and measure the amount

—

–27

by which each output is attenuated relative to SG7 (100kHz).

Set SW8, SW10 and SW12 = ON, input SG3 to TP22, TP23 and TP24, and measure the frequency which

5.5

—

results in –3dB relative to the TP8, TP10 and TP12 amplitude at 100kHz.

1.15

0.61

0.23

—

–18

—

MHz

REF output voltage

DA adjustment range

γ gain

γ1 adjustment

variable range

VREF

VDA1

VDA2

∆γ1

∆γ2

Vγ1MN

Vγ1MX

DA 00h

DA 07h

CONT 41h

Measure the REF pin output voltage at the output current 1.5mA sink.

Measure the DA output voltage when DA = 00h and 07h.

Output current

1.0mA Output current

–1.0mA

Input SG2 (0.35mVp-p) to TP22 and measure the amplitude at TP8, TP10 and TP12. Assume the output amplitude when GAMMA1 = 7Fh as V1, when GAMMA1 = 3Fh as V2, and when GAMMA1 = GAMMA2 = 3Fh as V3.

∆γ1 = 20 log (V1/V2) ∆γ2 = 20 log (V3/V2)

Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the non-inverted output at TP12 when γ1 = 00h and γ1 = 7Fh from the IRE level of the input signal.

γ1 = 00h: Vγ1MN γ1 = 7Fh: Vγ1MX

1.3

—

2.6

—

100

1.5

—

1.7

0.3

—

IRE

– 16 –

Page 17

CXA3572R

Item Symbol

γ2 adjustment variable range

COMMON control range

OSD threshold value

Data setup time

Vγ2MN

Vγ2MX

COMMIN

COMMX

Vth1 OSD

Vth2 OSD

ts0

ts1

Serial data setting (HEX)

CONT 41h

COM-DC

00h

COM-DC

7Fh

Measurement conditions Min. Typ. Max. Unit

Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the

100

—

non-inverted output at TP12 when γ2 = 00h and γ2 = 7Fh from the IRE level of the input signal. γ2 = 00h: Vγ2MN

—

γ2 = 7Fh: Vγ2MX Measure the COM output DC voltage

when COM-DC = 00h and 7Fh, and

–1.3

–1.0

measure the difference from the COM output DC voltage when COM-DC = 40h.

0.8

1.0

Input SG4 to TP18, TP19 and TP20, gradually raise the high level from 0V, and assume the high level

0.8

1.0

voltage at which the output level goes to BLK-LIM level as Vth1OSD, and the high level voltage at which the output goes to WHITE-LIM level

1.8

2.0

as Vth2OSD . SEN setup time, activated by the

rising edge of SCK. (See Fig. 3.) SDAT setup time, activated by the

rising edge of SCK. (See Fig. 3.)

150

—

IRE

–0.8

1.3

1.2 V

2.2

—

Data hold time

Minimum pulse width

Output transition time

Cross-point time difference

th0

th1 tw1L

tw1H tw2

tTHL

tTLH

tTHL

tTLH

∆T

SEN hold time, activated by the rising edge of SCK. (See Fig. 3.)

SDAT hold time, activated by the rising edge of SCK. (See Fig. 3.)

SCK pulse width. (See Fig. 3.) SCK pulse width. (See Fig. 3.) SEN pulse width. (See Fig. 3.) Measure the transition time of each

output. 90pF load: HST output pin 120pF load: HCK1 and HCK2 output pins (See Fig. 1.)

Measure the transition time of each output. 50pF load: DWN, WIDE, VCK, VST,

TEST, EN, VDO, HDO, POF and RGT output pins

(See Fig. 1.) Measure HCK1/HCK2.

120pF load (See Fig. 2.)

150

150 210

210

—

— —

—

— —

—

ns ns µs

HCK duty

DTYHC

Measure the HCK1/HCK2 duty. 120pF load

– 17 –

Page 18

Electrical Characteristic Measurement Method Diagrams

90%

10%

CXA3572R

∆T

50%

tTLH

tTHL

Fig. 1. Output transition time measurement conditions

SDAT

ts1

SCK

SEN

th1

tw1H tw1L

∆T

Fig. 2. Cross-point time difference measurement conditions

D15D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

50%

ts0

Fig. 3. Serial transfer block measurement conditions

– 18 –

th0

tw2

Page 19

CXA3572R

SG No.

SG1

SG2

Waveform

Horizontal sync signal (CSYNC)

4.7µs

Sine wave video signal; frequency and amplitude variable

3.0Vp-p

Amplitude variable

Horizontal sync signal

SG3

SG4

SG5

25µs 10µs

25µs

0.1Vp-p

High level variable

Horizontal sync signal

10µs

Low level variable

Horizontal sync signal

– 19 –

Page 20

CXA3572R

SG No.

SG6

SG7

SG8

Horizontal sync signal (CSYNC)

Sine wave video signal

Horizontal sync signal (CSYNC)

4.7ns

4.7µs

Waveform

50mVp-p

0.1Vp-p

0.15Vp-p

– 20 –

Page 21

Electrical Characteristics Measurement Circuit

CXA3572R

TP29

6800p

10k

3.3µ

0.01µ

TP38 TP39 TP40

TP42 TP43 TP44

TP46 TP47

+3V

47µ

100k

37 38 39 40 41 42 43 44 45 46 47 48

TP36

HDO VDO RGT Vss1 HCK1 HCK2 HST V

WIDE DWN Vss2

POF

3536

0.1µ 34

XCLR

VCK

VST

3 4

TP33TP32 TP31

3233

SCK

SDAT

TEST

GND2

5 10

SEN

COM

∗

43k

3031

RPD

GND1

B DC DET

FILTER

B OUT

R DC DET

8 9 11 12

TP27 TP26 TP25

2728

REF

B/B-Y

DA OUT

SYNC IN

R/R-Y

Vcc1

OSD G

OSD R

OSD B

SIG.C

PSIG DC DET

PSIG OUT

R OUT

G DC DET

G OUT

G/Y

1µ

0.01µ

TP24

0.01µ

TP23

+3V

0.01µ

TP22

TP20

TP19

TP18

0.01µ

47µ

TP16

0.1µ

Buffer

0.01µ

SW14

TP14

60n

+12V

0.1µ

1010

0.1µ

0.01µ

TP2 TP3

TP1

∗

Resistance value tolerance: ±2%, temperature coefficient: ±200ppm/°C or less

TP6

350p

SW8

TP8

350p

SW10

TP10

SW12

350p

TP12

Locate this resistor as close to the IC pin as possible to reduce the effects of external signals.

– 21 –

47µ

Page 22

CXA3572R

Description of Operation

1) RGB and Y/color difference signal processing block

Signal processing is comprised of picture, HUE, matrix, LPF/trap, contrast, OSD, sample-and-hold, γ correction, bright, sub-bright, sub-contrast and output circuits.

• Input signal mode switching The input mode (RGB input, Y/color difference input) can be switched by the serial communication settings. (During internal sync separation signal input)

During RGB input: The G signal is input to Pins 22 and 25, the B signal to Pin 24, and the

R signal to Pin 23.

During Y/color difference input: The Y signal is input to Pins 22 and 25, the B-Y signal to Pin 24, and

the R-Y signal to Pin 23.

(During external sync signal input)

During RGB input: The G signal is input to Pin 22, the B signal to Pin 24, the R signal to

Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34.

During Y/color difference input: The Y signal is input to Pin 22, the B-Y signal to Pin 24, the R-Y signal

to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34.

• NTSC/PAL switching The input system (NTSC/PAL) can be switched by the serial communication settings.

• Picture circuit This performs aperture correction for the Y signal. The center frequency to be corrected and the correction amount are controlled by serial communication.

• HUE circuit This is the hue adjustment circuit for the color difference signal. It is controlled by ser ial communication.

• Matrix circuit This circuit converts Y, R-Y and B-Y signals into RGB signals.

• LPF circuit This is the band limitation filter for the RGB signal. It is used to eliminate the noise component generated at the front end of this IC. The cut-off frequency can be controlled by serial communication. In addition, when not using the LPF, it can be turned off by serial communication.

• Trap circuit This is used to eliminate the DSP clock and RGB decoder carrier leak generated at the front end of this IC. In addition, when not using the trap, it can be turned off by serial communication.

• Contrast adjustment circuit This adjusts the amplitude to set the input RGB signal to the appropriate output level.

• OSD This inputs the OSD pulses. There are two input threshold values: Vth1 (Vcc1 × 1/3) and Vth2 (Vcc1 × 2/3). When an input exceeds Vth1, the corresponding output falls to the level specified by BLACK-LIMITER. When an input exceeds Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by BLACK-LIMITER.

– 22 –

Page 23

CXA3572R

• Sample-and-hold circuit This circuit performs time axis correction for the RGB output signals in order to support the RGB simultaneous sampling systems of LCD panels.

HCK1

S/H1 S/H4

S/H2 S/H4

RGT = H (Normal)

SH1 SH2 SH3 SH4

SHS1

Through

A C

SHS2

Through

C' B'

RGT = L (right/left inversion)

SH1 SH2 SH3 SH4

SHS1

B A

Through

SHS2

A' C'

Through

S/H3

SH3 SH4SH2SH1

SHS3

Through

SHS3

Through

S/H4

SHS4

Through

B' A'

SHS4

Through

SHS5

Through

B A

SHS5

C B

Through

SHS6

Through

SHS6

Through

A' C'

B' A'

SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse

SHS1, 2, 3, 4, 5, 6: Serial data settings

The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation and other timing is also generated by the digital block. The sample-and-hold timing changes according to the phase relationship with the HCK pulse, so the timing should be set to the SHS1 to SHS6 position in accordance with the actual board.

• γ correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The γ1 gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register γ1, and the γ2 gain transition point B voltage changes as shown in Fig. 3 by adjusting γ2.

Output

Input

Output

Input

Fig. 1 Fig. 2 Fig. 3

– 23 –

Page 24

CXA3572R

• Bright circuit This is used to adjust the black-black amplitude of polarity-inverted RGB output signals. It is not inter linked with the γ transition points.

• White balance adjustment circuit This is used to adjust the white balance. The black level is adjusted by SUB-BRIGHT, and the black-white amplitude is adjusted by SUB-CONTRAST.

• Output circuit RGB output (Pins 8, 10, and 12) signals are inverted each horizontal line by the FRP pulse (internal pulse) supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (SIG.C) of the output signal matches the reference voltage (Vcc2 + GND2)/2 (or the voltage input to SIG.C (Pin 16)). In addition, the white level output is clipped at the limiter operation point that is set by the serial communication WHITE-LIMITER, and the black level output is clipped at the limiter operation point that is set by the serial communication BLACK-LIMITER. The output PSIG signal level is normally adjusted by PSIG-BRIGHT, but during black frame display the level is specified by the BLACK-LIMITER level at some timings. In addition, the RGB output also simultaneously goes to BLACK-LIMITER level output.

RGB IN

1H inverted signal (internal)

Black frame display signal (internal)

PSIG OUT

RGB OUT

BLACK-LIMITER

Set by BLACK-LIMITER

SIG.C

Set by PSIG-BRIGHT

BLACK-LIMITER BLACK-LIMITER

WHITE-LIMITER SIG.C WHITE-LIMITER

BLACK-LIMITER

Set by BLACK-LIMITER

– 24 –

Page 25

CXA3572R

2) Common voltage generation circuit block

The common voltage circuit generates and supplies the common pad voltage to the LCD panel. The voltage is offset by serial communication using the SIG.C voltage as the reference and then output.

3) DA OUT output circuit

The DA OUT output circuit outputs DC 3.0V at equal divisions.

4) REF output circuit

The REF output circuit generates and supplies the panel level shifter circuit reference voltage to the LCD panel.

5) Sync system

• Internal sync separation circuit

Sync separation is performed from the signal input from SYNC IN (Pin 25). An external sync signal can also be input from the same pin (SYNC IN) according to the serial communication setting.

Serial communication setting

SYNC SEL = 0: Internal sync separation. SYNC SEL = 1: External sync signal input. (The inter nal sync separation circuit is set to power saving mode.)

Input pin (Pin 25) processing

During internal sync separation: Input through an external capacitor (0.1µF) During external sync signal input: Directly coupled, input level 3Vp-p positive or negative polarity

• PLL and AFC circuits (VCO setting method) A PLL circuit can be comprised by connecting a PLL circuit phase comparator and frequency division counter and a VCO circuit and exter nal LPF circuit. The PLL error detection signal is generated using the phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency division counter as the RPD output. RPD output is converted to DC error voltage with the lag-lead filter, and then it controls the internal VCO circuit to stabilize the oscillation frequency. The internal clock oscillation frequency is set as follows by adjusting VCO-Coarse/Fine. Adjust the VCO-Coarse/Fine settings so that the HDO pulse output frequency in the condition without sync input is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz.

Clock oscillation frequency

VCO-Coarse: f0 coarse setting (7 steps) from 5 to 25MHz VCO-Fine: Variable by approximately 4MHz using the f0 coarse setting made by

VCO-Coarse as the reference

5MHz

Min: 25MHz Max: 30MHz

VCO-Coarse setting (7 steps)

VCO-Fine setting range (255 steps)

6) Power saving circuit (PS circuit)

A power saving system can be realized together with the LCD panel by independently controlling (serial communication) the operation of each output block. This system is also effective for improving picture quality during power-on/off.

The serial data PS0 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the “Description of Serial Control Operation” and “Power supply and power saving sequence” items.

– 25 –

Page 26

7) Power supply and power saving sequence

Power-on for the CXA3572R and the LCD panel should be performed in the following order.

Power-offPower-on

LCD VDD (LCD panel 12V)

CC2

(analog 12V block)

CC1

V (analog 3V block)

VDD (digital 3V block)

Power saving setting (serial control)

B1 C1

Power saving canceled

∗1

Power saving

PS0 = 0, SLSG = 0

Power saving set

Normal operation

PS0 → 1, SLSG → 1

12 fields 4 fields

Display setting period

(no video display)

When power saving is set to on or off, video display is automatically turned on or off at the above timings.

Normal video display

Picture cancel period

(no video display)

DA OUT (Pin 26) operation

PS0 → 0, SLSG → 0

Power saving

CXA3572R

B2C2

Power-on

min. A1 B1 C1 D1 E1

∗

After the digital 3V VDD has completely risen

100

0 0 0

∗

max.

— — — —

100

and XCLR (Pin 35) is completely high level.

∗

After the 3V VDD/VCC1 has completely risen.

Power-off

min. A2 B2

C2 D2 E2

∗

After the panel 12V VDD has completely

0 0 0

∗

150

max.

— — — —

300

fallen.

• POF (Pin 36) is output as the panel VDD control signal. The POF output can be switched by the serial communication setting, and the POF setting can be made regardless of the power saving setting.

SLPOF POF (Pin 36) output

0 1

Low level High Level (VDD)

Power supply3V power supply

VCC2

POF

VDD

CXA3572R ACX306

Panel power supply configuration using POF output

– 26 –

Page 27

CXA3572R

8) TG block

• H-Position This adjusts the horizontal display position. Set this function so that the picture center matches the center of the LCD panel.

• V-Position This adjusts the vertical display position. Set this function so that the picture center matches the center of the LCD panel.

• Right/left (RGT) and/or up/down (DWN) inversion The video display direction can be switched. The horizontal direction can be switched between right scan and left scan, and the vertical direction between down scan and up scan. Set the display direction in accordance with the LCD panel mounting position.

• Overscan display mode (SLWD) Displaying black in the up/down 6 lines and right/left 18 (19) dots of the display area generates an overscan area (black frame) in the display area. Fine adjustment of the black frame display position is performed by SB-Position.

Black display

6 lines

490 dots

453 dots

240 lines

Display area

Normal display

Display area

Black frame display

228 lines

6 lines

• AC driving of LCD panels during no signal

The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the SYNC IN (Pin 25) and VD (Pin 34) pins.

– 27 –

Page 28

CXA3572R

Description of Serial Control Operation

1) System reset

After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. (See Fig. ) The serial bus is set to the default values.

XCLR (Pin 35)

TR > 10µs

System reset

2) Control method

Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading operation starts from the falling edge of SEN and is completed at the next rising edge. Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the SEN signal is input. In addition, if 16 bits or more of SCK are not input while SEN is low, the transferred data is not loaded to the inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of the SEN pulse are valid data.

SDAT A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SCK

SEN

D: DATAA: ADDRESS

Serial transfer timing

– 28 –

Page 29

2) Serial data map

The serial data map is as follows. Values inside parentheses are the default values.

CXA3572R

MSB

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

1 1

1 1 1 1 1

0 0 0 0 1 1 1 1

0 0

0 0 1 1 1

LSBADDRESS MSB LSBDA TA

0 0 1 1 0 0 1 1

0 0

1 1 0 0 1

0 1 0 1 0 1 0 1

0 1

0 1 0 1 0

(0) (0)

(0) (0) (0) (0)

PSIGSW

(0) (0) (0) (0)

(0)

LPFSW

(0) (0)

D6 D5 D4 D3 D2 D1 D0

USER-BRIGHT (10000000/LSB) SUB-BRIGHT R (1000000/LSB) SUB-BRIGHT B (1000000/LSB)

CONTRAST (10000000/LSB) SUB-CONTRAST R (1000000/LSB) SUB-CONTRAST B (1000000/LSB)

PSIG-BRIGHT (1000000/LSB)

(0)

BLACK-LIMITER (100000/LSB)

PICTURE-GAIN (00000/LSB)

(0)

VCO Coarse (000/LSB)

γ-1 (0000000/LSB) γ-2 (0000000/LSB)

COM-DC (1000000/LSB)

COLOR (1000000/LSB)

HUE (1000000/LSB)

VCO Fine (10000000/LSB)

PICTURE-F0 (000/LSB)

TRAP

(0)

DA (000/LSB)LPF (000/LSB)

INPUT

SEL (0)

SYNC

SEL (0)

MODE

(0)

SLSYP

(0)

SYST

(0) (0)

1 0

S/H POSITION (000/LSB)

SB POSITION (100/LSB)

(0)

SLEXVD

(0)

SLFL

(0)

SLMBK

(0)

TEST2

(1)

SLDWN

(0)

SLFR

(0)

PONF

(0)

SLRGT

(0)

SL4096

(0)

TEST4 (00000000/LSB)

TEST1

(0)

SLCLP1

(0)

H POSITION (100000/LSB)

HDO POSITION (00000/LSB)

V POSITION (01000/LSB)

SLPOF

(0)

TEST3

(00)

SLCLP0

(0)

SYNC

GEN (0)

SLWD

(0)

SLVDO

(0)

PS0

(0)

SLNTPL

(0)

SLHDO

(0)

Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to “0”.

– 29 –

Page 30

CXA3572R

3) Description of control data

• USER-BRIGHT This adjusts the brightness of the RGB output signals. Adjustment from LSB → MSB decreases the amplitude (black – black).

• SUB-BRIGHT R/B This adjusts the brightness of the R and B output signals using the G output signal as the reference. Adjustment from LSB → MSB decreases the amplitude (black – black).

• CONTRAST This adjusts the contrast of the RGB output signals. Adjustment from LSB → MSB increases the amplitude (black – white).

• SUB-CONTRAST R/B This adjusts the contrast of the R and B output signals using the G output signal as the reference. Adjustment from LSB → MSB increases the amplitude (black – white).

• γ-1 This sets the black side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the γ point. When not adjusting γ-1, set γ-1: 0000000 (LSB). Set the γ-1 point to the black side (lower side) of the γ-2 point.

• γ-2 This sets the white side γ point level of the RGB output signals. Adjustment from LSB → MSB lowers the γ point. When not adjusting γ-2, set γ-2: 0000000 (LSB). Set the γ-2 point to the white side (upper side) of the γ-1 point.

• PSIG-BRIGHT This adjusts the brightness of the PSIG output signal. Adjustment from LSB → MSB decreases the amplitude (peak to peak).

• PSIG-SW This switches the PSIG circuit on and off.

D7 Mode

01PSIG OFF

PSIG ON

• COM-DC This adjusts the COMMON output voltage. Adjustment from LSB → MSB increases the output voltage.

• COLOR This adjusts the color gain during Y/color difference input. Adjustment from LSB → MSB increases the gain.

• HUE This adjusts the phase during Y/color difference input. Adjustment from LSB → MSB advances the phase.

– 30 –

Page 31

CXA3572R

• VCO-Fine This finely adjusts the VCO oscillation center frequency. Adjustment from LSB → MSB increases the frequency. Perfor m this adjustment after adjusting VCO-Coarse.

• VCO-Coarse This roughly adjusts the VCO oscillation center frequency. Adjustment from LSB → MSB increases the frequency. Adjust with VCO-Fine set to 10000000 (LSB).

• BLACK-LIMITER This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB → MSB lowers the limiter level.

• PICTURE-GAIN This adjusts the picture gain during Y/color difference input. Adjustment from LSB → MSB raises the gain. When not using the picture function, set PICTURE-GAIN: 00000 (LSB).

• PICTURE-F0 This sets the picture center frequency (f0) during Y/color difference input. See the AC Characteristics for the output level.

D2 Center frequency (f0) typ.

1.0MHz

1.3MHz

1.6MHz

1.9MHz

2.2MHz

2.5MHz

2.8MHz

3.1MHz

• LPF This switches the frequency response of the low-pass filter. Set the fc/–3dB frequency relative to the amplitude 100kHz reference. See the AC Characteristics for the output level.

D6 fc (RGB input/no load/typ.)

—

1.5MHz

2.1MHz

2.7MHz

3.5MHz

4.1MHz

4.6MHz

5.2MHz

– 31 –

Page 32

• LPF-SW This switches the LPF circuit on and off.

D7 Mode

01LPF off

LPF on

• TRAP

This switches the trap circuit on and off.

D3 Mode

01TRAP off

TRAP on

• DA This adjusts the DA output voltage. Adjustment from LSB → MSB raises the output voltage level.

• INPUT-SEL

Set this according to the input signal level.

CXA3572R

D2 Mode

01Normal input

Internally attenuated by –6dB

0.35Vp-p or less, 0.5Vp-p or less with sync

0.35Vp-p or more, 0.5Vp-p or more with sync

Input signal level

• SYNC SEL

This switches between internal sync separation and external sync signal input.

D1 Mode

01Internal sync separation

External sync signal input (internal sync separation circuit power saving)

Input via a coupling capacitor Input level 3Vp-p positive or negative polarity

Input connection method

• MODE

This switches the input signal.

D0 Input signal

01RGB input

Y/color difference input

• PS0 (Default: 0)

This performs the power saving setting. Be sure to use this setting as described in “Power supply and power

saving sequence”. The power-on default for this IC is power saving mode, so the settings should be canceled by serial communication after power-on. The LCD panel power supply must be turned off in power saving mode.

PS0 Mode

0 1

Power saving Normal operation

– 32 –

Page 33

CXA3572R

• SYNC GEN (Default: 0) This sets the sync generator mode. In sync generator mode, only the HDO and VDO pulses are output normally, and all other pulses are low. The LCD panel power supply must be turned off in sync generator mode. Normally set to “1”.

SYNC GEN Mode

0 1

Sync generator mode Normal operation

• SLPOF (Default: 0) This sets the POF (Pin 36) output. The POF output setting can be made regardless of the power saving mode.

SLPOF Mode

0 1

POF = Low output POF = High output

• TEST1 (Default: 0) This is the test mode. Set to “0”.

TEST0 Mode

0 1

Normal operation Test mode

• PONF (Default: 0)

This switches the time until the picture is displayed after power saving is canceled.

PONF Mode

0 1

12 fields 4 fields

• TEST2 (Default: 0) This is the test mode. Set to “1”.

TEST2 Mode

0 1

Test mode Normal operation

• SLNTPL (Default: 0) This switches between NTSC and PAL mode.

SLNTPL Mode

0 1

NTSC PAL

– 33 –

Page 34

• SLWD (Default: 0)

This sets the up/down and/or right/left black frame display.

SLWD Display

CXA3572R

0 1

100% viewing field display Black frame display (95% display)

• TEST3 (Default: 0, 0) This is the test mode. Set to “0, 0”.

TEST3 Mode

0, 0

Normal operation

0, 1 1, 0

Test mode

1, 1

• SLRGT (Default: 0) This switches between normal and right/left inverted display.

SLRGT Setting

0 1

Normal display (right scan) Right/left inverted display (left scan)

• SLDWN (Default: 0) This switches between normal and up/down inverted display.

SLDWN Setting

0 1

Normal display (down scan) Up/down inverted display (up scan)

• SLEXVD (Default: 0) This sets the external VD input. The external VD signal is input via VD (Pin 34). When using internal vertical sync separation, vertical sync separation is performed using the CSYNC input from SYNC IN (Pin 25).

SLEXVD Setting

0 1

Internal vertical sync separation External VSYNC input

• SLSYP (Default: 0) This switches the input sync signal polarity. When performing sync separation with the internal sync separation circuit from YonSYNC or GonSYNC, set this to “0”.

SLSYP HD/CSYNC, VSYNC polarity

0 1

Positive polarity Negative polarity

– 34 –

Page 35

• SLHDO (Default: 0)

This switches the HDO pulse output polarity.

SLHDO HDO polarity

CXA3572R

0 1

Positive polarity Negative polarity

• SLVDO (Default: 0)

This switches the VDO pulse output polar ity.

SLVDO VDO polarity

0 1

Positive polarity Negative polarity

• SLCLP0, SLCLP1 (Default: 0, 0)

These switch the clamp position.

SLCLP1

0 0 1 1

HSYNC

SLCLP0

0 1 0 1

A: Back porch position (during internal sync separation) B: Sync position (during internal sync separation) C: Back porch position (during external sync signal input) D: Sync position (during exter nal sync signal input)

Position

2.0µs

XCLP

00: A 01: B

10: C 11: D

1.3µs

1.0µs

2.9µs

2.0µs

3.6µs

2.0µs

• SL4096 (Default: 0) This function inverts the R, G, B and PSIG output signal polarities every 4096 fields. This further inverts the output polarities that are inverted every 1H for 4096 fields.

SL4096 Polar ity inversion cycle

0 1

1H inversion 1H inversion + 4096-field inversion

• SLFR (Default: 0)

This function inverts the R, G, B and PSIG output signal polarities every field. Nor mally set to 1H inversion.

SLFR Polarity inversion cycle

0 1

1H inversion 1-field inversion

– 35 –

Page 36

• SLFL (Default: 0) This function is used to stop R, G, B and PSIG output signal polarity inversion.

SLFL Polarity inversion cycle

CXA3572R

0 1

Polarity inversion Polarity inversion stopped

• SYST (Default: 0) This invalidates the input horizontal sync (CSYNC, HD) and forcibly sets the free-running status.

SYST Mode

0 1

Normal operation Forced free-running

• H POSITION (Default: 100000/LSB) These set the horizontal display position. The HST pulse position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 1fH increments.

HSYNC

HP: 100000 (LSB) Default

HST

HP: 000000 (LSB)

HP: 111111 (LSB)

30 steps (fH) 31 steps (fH)

• SLMBK (Default: 0) This sets the decimation cycle in PAL mode.

SLMBK Decimation cycle

0 1

1/6, 1/6 decimation 1/6, 1/8 decimation

• HDO POSITION (Default: 00000/LSB) These set the HDO pulse output position. The HDO pulse output position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments.

HSYNC

HP: 00000 (LSB) Default

HDO

31 steps (124fH)

HP: 11111 (LSB)

– 36 –

Page 37

CXA3572R

• V POSITION (Default: 01000/LSB) These set the vertical display position. The VST pulse position is adjusted using the input vertical sync signal as the reference. Adjustment is possible in 1 bit = 1H (1 line) increments.

Vertical sync signal

VP: 01000 (LSB) Default

VST

8 steps (8H) 23 steps (23H)

VP: 00000 (LSB)

VP: 11111 (LSB)

• S/H POSITION (Default: 000/LSB) These set the sample-and-hold pulse output phase.

D7 Sample-and-hold position

Through (sample-and-hold off)

SHS1 SHS2 SHS3 SHS4 SHS5 SHS6

• SB POSITION (Default: 100/LSB) In overscan display mode, fine adjustment of the right/left overscan area (black frame) position is possible in 1 bit = 1fH increments.

HST

(BLK)

(4fH)

3 steps

(3fH)

4 steps

• TEST4 (Default: 00000000/LSB) This is the test mode. Set to 00000000/LSB (8 bits).

– 37 –

4 steps

(4fH)

SBP: 000 (LSB)

SBP: 100 (LSB)

SBP: 111 (LSB)

3 steps

(3fH)

Page 38

Application Circuit

External HD

To LCD Panel

Input (0 to 3V)

CXA3572R

To LCD Panel

0.1µ 100k

0.1µ

33µ

37 38 39 40 41 42 43 44 45 46 47 48

+3V (Digital)

POF

V HDO VDO RGT Vss1 HCK1 HCK2 HST V

WIDE DWN Vss2

To LCD Panel

3536

XCLR

External VD

Input

VCK

VST

3 4

Serial Data

Input

3233

SCK

SDAT

TEST

SEN

GND2

5 10

3031

COM

3.3µ

∗

6800p

10k

43k

RPD

GND1

B DC DET

B OUT

8 9 11 12

0.68µ

10 10 10 10

0.01µ

FILTER

R DC DET

0.68µ

2728

REF

PSIG DC DET

R OUT

0.68µ

B/B-Y

DA OUT

SYNC IN

R/R-Y

G/Y

Vcc1

OSD G

OSD R

OSD B

SIG.C

PSIG OUT

G OUT

G DC DET

0.1µ

B/B-Y R/R-Y

G/Y

0.1µ

+3V (Analog)

33µ

0.01µ

∗

0.68µ

Buffer

0.1µ

To LCD Panel

+12V

33µ

(Analog)

+12V

(Analog)

33µ

22k

To LCD Panel

22k

PSIG Buffer Circuit

∗1

Resistance value tolerance: ±2%, temperature coefficient: ±200ppm/°C or less

∗2

When using a signal center voltage other than Vcc2/2, input an external signal center voltage.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 38 –

OUT

Page 39

CXA3572R

Notes on Operation

(1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired

radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern.

• The digital and analog IC power supplies should be separated, but the GND and VSS should not be separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as possible. The power supplies should also use a plain pattern.

• Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect these capacitors as close to the pins as possible.

• The resistor connected to Pin 28 should be connected as close to the pin as possible, and the wiring from the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin or the connected resistor.

(2) The G/Y (Pin 22), R/R-Y (Pin 23), B/B-Y (Pin 24) and SYNC IN (Pin 25) pin input signals are clamped at

the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low impedance. (Input at an impedance of 1kΩ (max.) or less.)

(3) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the

RGB output pins should have a leak current with a small absolute value and variance. Also, when using the pulse elimination (PAL display) function, the picture quality should be thoroughly evaluated before deciding the capacitance value of the capacitor.

(4) A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel

specifications should be made before deciding the capacitance value.

(5) If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction

depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of using this IC with other circuits before deciding on its use.

(6) Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater

than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up.

(7) Be sure to observe the power supply and power saving sequence specifications specified for this IC.

(8) Do not apply a voltage higher than VDD or lower than VSS to I/O pins.

(9) Do not use this IC under operating conditions other than those given.

(10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may

damage the device, leading to eventual breakdown.

(11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should

be taken to prevent electrostatic discharge.

(12) Always connect the VSS, GND1 and GND2 pins to the lowest potential applied to this IC; do not leave

these pins open. The voltages applied to the power supply pins should be as follows. VSS = GND1 = GND2 ≤ VDD = VCC1 ≤ VCC2.

(13) Be sure to connect the damping resistor of 10Ω to ROUT, GOUT, BOUT, PSIGOUT and COM output.

– 39 –

Page 40

Package Outline Unit: mm

∗ 7.0 ± 0.1

CXA3572R

48PIN LQFP (PLASTIC)

9.0 ± 0.2

0.5

0˚ to 10˚

+ 0.08

0.18 – 0.03

0.1 ± 0.1

0.5 ± 0.2

(0.22)

0.13

(8.0)

+ 0.2

1.5 – 0.1

0.18 ± 0.03

DETAIL B: PALLADIUM

+ 0.05

0.127 – 0.02

0.1

0.127 ± 0.04

0.5 ± 0.2

SONY CODE EIAJ CODE JEDEC CODE

DETAIL A

LQFP-48P-L01

P-LQFP48-7x7-0.5

NOTE: Dimension “∗” does not include mold protrusion.

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREA TMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN

PALLADIUM PLATING

COPPER ALLOY

0.2g

– 40 –

Sony Corporation