Datasheet CXA3555N Datasheet (Sony)

Page 1

All Band Tuner IC with On-chip PLL

Description

The CXA3555N is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniatur ization of the tuner.

Features

• Low power consumption (5V, 63mA typ.)

• Low noise figure, low distortion characteristics

• High gain/low gain selectable

• Supports IF double-tuned/adjacent channel trap

• Balanced oscillator circuits (3 sets) with excellent

oscillation stability

• On-chip PLL supports I2C bus

• On-chip high voltage drive transistor for charge

pump

• Frequency step selectable from 31.25, 50 or

62.5kHz (when using a 4MHz crystal)

• Low-phase noise synthesizer

• On-chip 4-output band switch (output voltage: 5V,

current capacity: 5mA)

• 30-pin SSOP small package

CXA3555N

30 pin SSOP (Plastic)

Absolute Maximum Ratings

• Supply voltage VCC –0.3 to +5.5 V

• Operating temperature Topr –25 to +75 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipation

PD 580 mW

Operating Conditions

Supply voltage VCC 4.75 to 5.30 V

Applications

• TV tuners

• VCR tuners

• CATV tuners

Structure

Bipolar silicon monolithic IC

Note: This IC has pins whose electrostatic discharge strength is weak as the operating frequency is high

and the high-frequency process is used for this IC. Take care of handling the IC.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01326-PS

Page 2

Block Diagram and Pin Configuration

CXA3555N

SCL

SDA

BS1

BS2

IFIN1

IFIN2

Vcc

IF AMP

C BUS

I Interface

Shift Register

Band SW Driver

Programable Divider 14/15 bit

Divider 1/128, 160, 256

Phase Detector

Prescaler 1/2

REF OSC

Charge Pump

IFOUT

ADSW

BS3

REF OSC

CPO

GND2

MIXOUT1

MIXOUT2

GND1

VHFIN

BYP

BS4

UHFIN1

UHFIN2

11 12

13 14

UOSCB2

UOSCE2

UOSCE1

UHFOSC

VHOSC

UHF/VHF

MIX

VLOSC

UOSCB1

VHOSC2

VLOSC2

VHOSC1

VLOSC1

– 2 –

Page 3

Pin Description

CXA3555N

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

Symbol

SCL SDA BS1 BS2 IFIN1 IFIN2 Vcc MIXOUT1 MIXOUT2 GND1 VHFIN BYP BS4 UHFIN1 UHFIN2 VLOSC1

Description

SCL input SDA I/O Band switch output 1 Band switch output 2 IF amplifier input IF amplifier input Power supply MIX output (open collector) MIX output (open collector) Analog circuit GND VHF input VHF input GND and gain switching (low: GND, high: open) Band switch output 4 UHF input UHF input

VHF Low-band oscillator 17 18 19 20 21 22 23 24 25 26 27 28 29 30

VHOSC1 VLOSC2 VHOSC2 UOSCB1 UOSCE1 UOSCE2 UOSCB2 GND2 VT CPO REFOSC BS3 ADSW IFOUT

VHF High-band oscillator

VHF Low-band oscillator

VHF High-band oscillator

UHF oscillator (base pin)

UHF oscillator (emitter pin)

UHF oscillator (base pin)

PLL circuit GND

Tuning voltage output (open collector)

Charge pump output (loop filter connection)

Crystal connection for PLL reference oscillator

Band switch output 3

Address selection (I2C bus)

IF amplifier output

– 3 –

Page 4

Pin Description

CXA3555N

Pin No.

Symbol

1 SCL — Clock input

2SDA — Data input

Pin voltage

[V]

Equivalent circuit Description

40k

3 BS1

4 BS2

13 BS4

28 BS3

High: 4.9 Low: 0.0

3 4

13 28

70k

Band switch outputs. This pin corresponding to the

selected band goes High.

– 4 –

Page 5

CXA3555N

Pin No.

5 IFIN1

Symbol

Pin voltage

[V]

Equivalent circuit Description

1.6k

IF inputs.

2.0

These pins must be connected to the mixer outputs via coupling capacitance.

6 IFIN2

7VCC — Power supply.

8 MIXOUT1

Mixer outputs. These pins output the signal in

—

open collector format, and they must be connected to the

9 MIXOUT2

power supply via a load.

10 GND1 — Analog circuit GND.

11 VHFIN

2.4 during VHF reception

0.0 during UHF reception

3k 3k

15p

150k

57k

VHF input. The input format is unbalanced input.

VHF input GND and gain switching.

12 BYP

VCC

(when open)

GND: low gain Open: high gain (However, when control byte GC is "0")

14 UHFIN1

15 UHFIN2

0.0 during VHF reception

2.3 during UHF reception

14 15

3k 3k

UHF inputs. Input a balanced signal to Pins 14 and 15, or ground either of Pin 14 or 15 with a capacitor and input the signal to the other pin.

– 5 –

Page 6

CXA3555N

Pin No.

Symbol

16 VLOSC1

18 VLOSC2

17 VHOSC1

19 VHOSC2

Pin voltage

[V]

0.0

Equivalent circuit Description

16 18

3333

External resonance circuit connection for VL oscillator.

50k

17 19

2020

50k

External resonance circuit connection for VH oscillator.

50k

2.4 during

20 UOSCB1

21 UOSCE1

22 UOSCE2

23 UOSCB2

VHF reception

2.2 during UHF reception

2.0 during VHF reception

1.5 during UHF reception

2.0 during VHF reception

1.5 during UHF reception

2.4 during VHF reception

2.2 during UHF reception

23 22 21 20

External resonance circuit connection for UHF oscillator.

24 GND2 — PLL circuit GND.

25 VT —

Varicap drive voltage output. This pin outputs the signal in open collector format, and it must be connected to the tuning power supply via a load.

26 CPO 2.0

Charge pump output. Connects the loop filter.

– 6 –

Page 7

CXA3555N

Pin No.

Symbol

Pin voltage

[V]

27 REFOSC 4.4

29 ADSW

1.25

(when open)

Equivalent circuit Description

30k

25p

Crystal connection for reference oscillator.

38p

150k

Address selection. Controls address bits 1 and 2.

50k

30 IFOUT 2.8 IF output.

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Page 8

Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.) Circuit Current

(Vcc = 5V, IFVCC = 5V, Ta = 25°C)

CXA3555N

Item Symbol

Iccv

Circuit current

Iccu

OSC/MIX/IF Amplifier Block

Item Symbol

CG1 CG2 CG3 CG4

Conversion gain

∗

CG5 CG6 CG7 CG8 NF1 NF2 NF3

Noise figure

∗1, ∗

NF4

NF5 NF6 NF7 NF8

Measurement conditions

VCC current Band switch output open during VHF operation

VCC current Band switch output open during UHF operation

Measurement conditions VHF operation fRF = 55MHz High gain mode VHF operation fRF = 360MHz High gain mode UHF operation fRF = 360MHz High gain mode UHF operation fRF = 800MHz High gain mode VHF operation fRF = 55MHz Low gain mode VHF operation fRF = 360MHz Low gain mode UHF operation fRF = 360MHz Low gain mode UHF operation fRF = 800MHz Low gain mode VHF operation fRF = 55MHz High gain mode VHF operation fRF = 360MHz High gain mode UHF operation fRF = 360MHz High gain mode UHF operation fRF = 800MHz High gain mode VHF operation fRF = 55MHz Low gain mode VHF operation fRF = 360MHz Low gain mode UHF operation fRF = 360MHz Low gain mode UHF operation fRF = 800MHz Low gain mode

Min. Typ.

19.0

19.5

23.0

17.0

17.5

21.0

22.0

22.5

26.0

20.0

20.5

24.0

24.0 12 12 10 11 13 13 11 12

Max. Unit

25.0

25.5

29.0

23.0

23.5

27.0

27.0 15 15 13 14 16 16 14 15

dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB

1% cross modulation 1

∗1, ∗

Maximum output power

CM1

CM2

CM3

CM4

CM5

CM6

CM7

CM8 Pomax

VHF operation fD = 55MHz fUD = ±12MHz (30% AM) High gain mode

VHF operation fD = 360MHz fUD = ±12MHz (30% AM) High gain mode

UHF operation fD = 360MHz fUD = ±12MHz (30% AM) High gain mode

UHF operation fD = 800MHz fUD = ±12MHz (30% AM) High gain mode

VHF operation fD = 55MHz fUD = ±12MHz (30% AM) Low gain mode

VHF operation fD = 360MHz fUD = ±12MHz (30% AM) Low gain mode

UHF operation fD = 360MHz fUD = ±12 MHz (30% AM) Low gain mode

UHF operation fD = 800MHz fUD = ±12 MHz (30% AM) Low gain mode

50Ω load, saturation output

– 8 –

100

103

101

104

102

98 11

dBµ

dBm

Page 9

CXA3555N

Item Symbol

Switch ON drift (PLL not

operating)

∗

Supply voltage drift (PLL not

operating)

∗

Oscillator phase noise

∆fsw1

∆fsw2

∆fsw3

∆fsw4

∆fst1

∆fst2

∆fst3

∆fst4

C/N1

C/N2

Measurement conditions

VHF operation fOSC = 100MHz ∆f from 3s to 3min after switch ON

VHF operation fOSC = 405MHz ∆f from 3s to 3min after switch ON

UHF operation fOSC = 405MHz ∆f from 3s to 3min after switch ON

UHF operation fOSC = 845MHz ∆f from 3s to 3min after switch ON

VHF operation fOSC = 100MHz ∆f when VCC 5V changes ±5%

VHF operation fOSC = 405MHz ∆f when VCC 5V changes ±5%

UHF operation fOSC = 405MHz ∆f when VCC 5V changes ±5%

UHF operation fOSC = 845MHz ∆f when VCC 5V changes ±5%

VHF operation 10kHz offset CP = 1 Phase comparison frequency = 31.25kHz

UHF operation 10kHz offset CP = 1 Phase comparison frequency = 31.25kHz

Min. Typ.

Max. Unit ±300

±600

±350

±400

±100

±450

±100

kHz

dBc/Hz

∗

Value measured with untuned input.

∗

NF meter direct-reading value (DSB measurement).

∗

Value with a desired reception signal input level of –30dBm, an interference signal of 100kHz/30% AM, and an interference signal level where S/I = 46dB measured with a spectrum analyzer.

∗

Value when the PLL is not operating.

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Page 10

PLL Block

CXA3555N

Item

Lock-up time

Reference leak

CL and DA inputs

"H" level input voltage "L" level input voltage "H" level input current "L" level input current

AD input

"H" level input voltage "L" level input voltage "H" level input current "L" level input current

SDA output

Symbol

LUT1

LUT2

REFL

VIL IIH IIL

VIH VIL IIH IIL

Measurement conditions

VHF operation CP = 1 fOSC 100MHz ←→ fOSC 405MHz

UHF operation CP = 1 fOSC 405MHz ←→ fOSC 845MHz

Phase comparison frequency = 31.25kHz CP = 1

VIH = Vcc VIL = GND

Min. Typ.

GND

–0.2

GND

100 –35

Max. Unit

dBc

Vcc

1.5

–0.1

–4

Vcc

200

–100

V µA µA

"H" output leak current "L" output voltage

CPO (charge pump)

Output current 1 Leak current 1 Output current 2 Leak current 2

VT (VC voltage output)

Maximum output voltage Minimum output voltage

REFOSC

Oscillation frequency range Input capacitance

Negative resistance

Band SW

Output current Saturation voltage

ISDALK VSDAL

ICPO1 LeakCP1 ICPO2 LeakCP2

VTH VTL

FXTOSC CXTOSC

RNEG

IBS VSAT

VIN = 5.5V Sink = –3mA

GND

When CP = 0 is selected When CP = 0 is selected When CP = 1 is selected

±120

When CP = 1 is selected

Sink current = 1mA

Crystal source impedance fREF = 4MHz

When ON When ON Source current = 5mA

±30

22 –1

±50

±200

0.15

24 –3

100

0.4

±80

±320

100

0.8

12 26

–5

300

µA

µA nA µA nA

MHz

kΩ

mA mV

Leak current

LeakBS

When OFF IFVCC = 5.5V

– 10 –

0.5

µA

Page 11

CXA3555N

Item

Bus timing (I2C bus)

SCL clock frequency Start waiting time Start hold time Low hold time High hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time

Symbol

fSCL

tW;STA tH;STA tLOW tHIGH tS;STA tH;DAT tS;DAT tR tF tS;STO

Measurement conditions Min. Typ. Max. Unit

1300

600

1300

600 600

600

400

900

300 300

kHz

ns ns ns ns ns ns ns ns ns ns

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Page 12

Electrical Characteristics Measurement Circuit

IF OUT +30V

4700p

CXA3555N

22k

IFOUT

1.2k

ADSW

100p

BS3

XTAL

4MHz

REFOSC

10k 0.056µ

CPO

10k

25VT24

240

GND2

220n

10k

2.5φ

2.5T

1T363

10k

0.5p

56p

0.5p

1T363

56p

7p 2p 7p

UOSCB222UOSCE221UOSCE120UOSCB119VHOSC2

10k 10k

3.4φ

2.5T

10k

1T363

0.5p

12p 12p

10k

56p

VLOSC2

3.4φ

8.5T

56p

1T362

0.5p

10p 10p

0 0

VLOSC1

VHOSC1

SCL

SDA

BS1

BS2

IFIN1

IFIN2

Vcc

MIXOUT1

MIXOUT2

GND1

VHFIN

BYP

BS4

UHFIN1

UHFIN2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1000p

1.2k

5151 1.2k

1n 1n 1.2k 1n 1n

150p

1000p

3.3µ

ADSW SCL SDA +5V VHF IN UHF IN

100

4.5T4.5T

56p 56p

1000p

– 12 –

Page 13

Application Circuit

IF OUT +30V

4700p

22k

CXA3555N

1000p

1.2µH

10p

IFOUT

ADSW

FMT

100p

BS3

XTAL

4MHz

REFOSC

10k

CPO

0.056µ

10k

25VT24

240

0.5p

100p

22p 8p 8p

GND2

UOSCB222UOSCE221UOSCE120UOSCB119VHOSC2

220n

10k

2.0φ

1.5T

1T369

12p

100p

10k 10k

1T363

0.5p

56p

3.4φ

2.5T 51

VLOSC2

10k

VHOSC1

1T362

0.5p

3.4φ

8.5T

VLOSC1

56p

SCL

SDA

BS1

BS2

IFIN1

IFIN2

Vcc

MIXOUT1

MIXOUT2

GND1

VHFIN

BYP

BS4

UHFIN1

UHFIN2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

3.2φ

7.5T

1000p

56p 56p

100

4.5T4.5T

1000p

1n 1n 1n

150p

33p

2002003k

3.8φ

14.5T

47p

ADSW SCL SDA +5V VHF IN UHF IN

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

47p

BVL BVH

3.3µ

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Page 14

CXA3555N

Description of Functions

The CXA3555N is an analog terrestrial TV broadcasting tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF and UHF band signals. In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillation frequency control onto a single chip. The functions of the various circuits are described below.

1. Mixer circuit

This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal.

2. Local oscillation circuit

A VCO is f ormed by externally connecting an LC resonance circuit composed of a varicap diode and inductance.

3. IF amplifier circuit

This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage.

4. PLL circuit

This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports the I2C bus format. The frequency steps of 31.25, 50 or 62.5kHz can be selected by the I2C bus data-based reference divider frequency division setting value.

5. Band switch circuit

The CXA3555N has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data. The emitters for these PNP transistors are connected to the power supply pin (VCC), and are ON and output 5V when the bus data is "1 (H)".

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Page 15

CXA3555N

Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.)

VHF-Low oscillator circuit

• This is a completely balanced oscillator circuit. The oscillation frequency is varied by connecting an LC parallel

resonance circuit including a varicap between Pins 16 and 18 via coupled capacitance and controlling the voltage applied to the varicap.

VHF-High oscillator circuit

• This is a completely balanced oscillator circuit. The oscillation frequency is varied by connecting an LC parallel

resonance circuit including a varicap between Pins 17 and 19 via coupled capacitance and controlling the voltage applied to the varicap.

VHF mixer circuit

• The mixer circuit employs a double balanced mixer with little local oscillation signal leakage.

The input format is base input type, with Pin 12 grounded either directly or via a capacitor and the RF signal input to Pin 11. (Pin 12 can also be used to switch the IC gain according to the applied DC voltage value. When switching the gain with Pin 12, the GC bit of the PLL data must be set to "0".)

• The RF signal is fed from the oscillator, converted to IF frequency and output from Pins 8 and 9. Pins 8 and 9 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 8 and 9.

UHF oscillator circuit

• The oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential

oscillation operation via an LC resonance circuit including a varicap.

• Resonance capacitance is connected between Pins 20 and 21, Pins 21 and 22, and Pins 22 and 23, and an LC resonance circuit including a varicap is connected between Pins 20 and 23.

UHF mixer circuit

• This circuit employs a double balanced mixer like the VHF mixer circuit.

The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input consisting of grounding Pin 14 via a capacitor and input to Pin 15.

• Pins 8 and 9 are the mixer outputs. Pins 8 and 9 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 8 and 9.

IF amplifier circuit

• Pins 5 and 6 are the IF amplifier inputs, and the input impedance is approximately 1.6kΩ.

• The signals frequency converted by the mixer are output from Pins 8 and 9, and Pins 8 and 9 are connected

to Pins 5 and 6 via capacitors. (An adjacent channel trap circuit can be formed by connecting LC parallel circuits in place of capacitors.)

• The signal amplified by the IF amplifier is output from Pin 30. The output impedance is approximately 10Ω.

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Page 16

CXA3555N

Description of PLL Block

This IC is controlled by the I2C bus. The PLL of this IC performs high-speed phase comparison, providing low reference leak and quick lock-up time characteristics. During power on, the power-on reset circuit operates to initialize the frequency data to all "0" and the band data to all "OFF". Power-on reset is performed when VCC ≥ 3.2V at room temperature (Ta = 25°C).

1) Address setting

Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one system. The responding address can be set according to the ADSW pin voltage.

Address

11000MA1MA0R/W

Hardware bits

ADSW pin voltage

0 to 0.1Vcc

OPEN or

0.2Vcc to 0.3Vcc

0.4Vcc to 0.6Vcc

0.9Vcc to Vcc

MA1

0 0 1

MA0

0 1 0

2) Frequency data setting

The VCO lock frequency is obtained according to the following formula.

fosc = 2 × fref × (32M + S)

fosc: local oscillator frequency fref: phase comparison frequency M: main divider frequency division ratio S: swallow counter frequency division ratio

The variable frequency division ranges of M and S are as follows, and are set as binary.

S < M ≤ 1023 0 ≤ S ≤ 31

– 16 –

Page 17

CXA3555N

3) Control format

When performing control for this IC, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data. These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5. When the correct address is received and acknowledged, the data is recognized as frequency data if the first bit of the next byte is "0", and as control data and band switch data if this bit is "1". Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once the control and band switch data have been programmed, 3-byte commands consisting of the address and frequency data are possible. Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions and the new address.

The control format is as shown in the table below.

Slave Receiver

Mode Address byte Divider byte1 Divider byte2 Control byte Band SW byte

MSB

bit 7

1 0

bit 6

1 M9 M1 CP

bit 5

0 M8 M0 GC

bit 4

bit 3

BS4

bit 2 MA1

BS3

bit 1

MA0

BS2

LSB bit 0

0 M3 S0

BS1

A A A A A

X: Don't care A: Acknowledge bit MA0, MA1: address setting M0 to: main divider frequency division ratio setting S0 to: swallow counter frequency division ratio setting CD: charge pump OFF (when "1") OS: varicap output OFF (when "1") CP: charge pump current switching (200µA when "1", 50µA when "0")

GC: gain switching (IC gain reduced by 2dB when "1")

∗

BS1 to BS4: band switch control (output PNP transistor ON when "1") R0, R1: reference divider frequency division ratio setting (See the Ref erence Divider Frequency Division

Ratio Table.)

∗

When switching the gain with the PLL data, ground Pin 12 (BYP) via a capacitor.

Reference Divider Frequency Division Ratio Table

0 1 X

1 1 0

Reference Divider

256 128 160

X: Don't care

– 17 –

Page 18

I2C Bus Timing Chart

SDA

W;STA

CXA3555N

SCL

tS;STA

tH;STA tLOW tHIGH tS;DAT tH;DAT

START

S;STA = Start setup time

t t

W;STA = Start waiting time

H;STA = Start hold time

LOW = Low clock pulse width

HIGH = High clock pulse width

tR tF

tS;STO

CLOCK DATA CHANGE STOP

S;DAT = Data setup time

t t

H;DAT = Data hold time

S;STO = Stop setup time

R = Rise time

F = Fall time

– 18 –

Page 19

Example of Representative Characteristics

Circuit current vs. Supply voltage

60 58

56 54 52 50 48 46

Icc – Circuit current [mA]

44 42

4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 Vcc – Supply voptage [V]

VHF UHF

Band SW output voltage vs. Output current

5.4

5.3

5.2

5.1

5.0

4.9

Output voltage [V]

4.8

4.7

4.6 01234567

(BS1, BS2, BS3, BS4)

Vcc = 5V

Output current [mA]

CXA3555N

Conversion gain vs. Reception frequency

(Untuned input)

VHF (Low)

CG – Conversion gain [dB]

0 100 200

VHF (High)

300 400 500 600 700 800 900

Reception frequency [MHz]

fIF = 45MHz High gain mode

UHF

Next adjacent cross modulation vs. Reception frequency

(Untuned input)

120 110 100

90 80 70 60 50 40 30

CM – Cross modulation [dBµ]

20 10

0 100 200

VHF (Low)

VHF (High)

300 400 500 600 700 800 900

Reception frequency [MHz]

UHF

fUD = fD + 12MHz f

= fD – 12MHz

(100kHz, 30% AM)

fIF = 45MHz High gain mode

– 19 –

Noise figure vs. Reception frequency

(Untuned input, in DSB)

VHF (Low)

NF – Noise figure [dB]

0 100 200

VHF (High)

300 400 500 600 700 800 900

Reception frequency [MHz]

fIF = 45MHz High gain mode

UHF

Oscillation frequency power supply fluctuation

(PLL off)

400

Vcc + 5%

300

200

100

+B drift [kHz]

–100

–200

–300 –400

VHF (Low)

0 100 200

VHF (High)

300 400 500 600 700 800 900

Oscillation frequency [MHz]

Vcc – 5% (Vcc = 5V)

UHF

Page 20

Oscillator phase noise vs. Reception frequency (untuned input)

130

120

110

100

VHF (Low)

VHF (High)

UHF

CXA3555N

fIF = 45MHz High gain mode

VHF (Low)

C/N – Oscillator phase noise [dBc/Hz]

0 100 200 300 400 500

I/O characteristics (untuned input)

VHF (High)

UHF

Reception frequency [MHz]

–10

1kHz offset 10kHz offset 100kHz offset

600 700 800 900

PCS beat characteristics (untuned input)

High gain mode

–10

–20

–30

IF output level [dBm]

–40

fRF = 45MHz

–50

High gain mode

fRF = 145MHz (VHF)

= 495MHz (UHF)

–60

–60 –50 –40 –30 –20 –10 0 10 20

RF level [dBm]

– 20 –

–20

–30

–40

IF output level [dBm]

–50

Beat

Local

= 495MHz

= 449.25MHz

f fc = 452.83MHz

–60

–70

–12dB)

fs = 453.75MHz

–1.7dB)

fIF = 45.75MHz f

Beat

= fIF ± 950kHz

–80

–40 –30 –20 –10 0 10 20

RF level (SG Setting level) [dBm]

Page 21

Tuning Response Time

CXA3555N

VHF (Low) 95MHz → VHF (High) 395MHz

CP = 0

–75.0000ms 125.0000ms25.0000ms

CP = 1

T = 47.2ms

20.0ms/div

T = 15.0ms

5.0V/div Offset 10.0V

–40.0000ms 60.0000ms10.0000ms

10.0ms/div

– 21 –

5.0V/div Offset 10.0V

Page 22

UHF 413MHz → UHF 847MHz

CXA3555N

CP = 0

–70.0000ms 130.0000ms30.0000ms

CP = 1

T = 63.6ms

20.0ms/div

T = 20.2ms

5.0V/div Offset 10.0V

–40.0000ms 60.0000ms10.0000ms

10.0ms/div

– 22 –

5.0V/div Offset 10.0V

Page 23

VHF (High) 395MHz → VHF (Low) 95MHz

CXA3555N

CP = 0

–110.0000ms 90.0000ms–10.0000ms

CP = 1

T = 27.0ms

20.0ms/div

T = 7.2ms

5.0V/div Offset 10.0V

–45.0000ms 55.0000ms5.0000ms

10.0ms/div

– 23 –

5.0V/div Offset 10.0V

Page 24

UHF 847MHz → UHF 413MHz

CXA3555N

CP = 0

–110.0000ms 90.0000ms–10.0000ms

CP = 1

T = 35.6ms

20.0ms/div

T = 14.4ms

5.0V/div Offset 10.0V

–90.0000ms 110.0000ms10.0000ms

20.0ms/div

– 24 –

5.0V/div Offset 10.0V

Page 25

CXA3555N

IF output spectrum

CENTER 45.00013MHz

RES BW 1.0kHz

VBW 10Hz

REF = –10.0dBm

10dB/div

VHF (Low)

= 55MHz

= 100MHz

RF input level: –40dBm

SPAN 50.00kHz

SWP 30.0s

REF = –10.0dBm

10dB/div

VHF (High)

= 350MHz

= 395MHz

CENTER 45.00088MHz

RES BW 1.0kHz

VBW 10Hz

RF input level: –40dBm

SPAN 50.00kHz

SWP 30.0s

REF = –0.0dBm

10dB/div

UHF

= 800MHz

f f

= 845MHz

RF input level: –40dBm

CENTER 45.00188MHz

RES BW 1.0kHz

VBW 10Hz

– 25 –

SPAN 50.00kHz

SWP 30.0s

Page 26

CXA3555N

VHF Input Impedance

j50

j100j25

50MHz

11 12

1000p

350MHz

S11

UHF Input Impedance

–j100–j25

–j50

j50

j100j25

14 15

1000p

350MHz

S11

800MHz

–j100–j25

–j50

– 26 –

Page 27

IF Output Impedance

CXA3555N

j50

j100j25

45MHz 38MHz

–j100–j25

–j50

– 27 –

Page 28

Package Outline Unit: mm

CXA3555N

30PIN SSOP (PLASTIC)

∗9.7 ± 0.1

115

0.13

0.1 ± 0.1

∗5.6 ± 0.1

0.65

b=0.22 ± 0.03

1.25

+ 0.03

0.15 – 0.01

+ 0.2 – 0.1

0.10

7.6 ± 0.2

SONY CODE EIAJ CODE

JEDEC CODE

0˚ to 10˚

0.5 ± 0.2

DETAIL A

SSOP-30P-L01

P-SSOP30-5.6x9.7-0.65

DETAIL B : PALLADIUM

NOTE: Dimension "∗" does not include mold protrusion.

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREA TMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN PALLADIUM PLATING

COPPER ALLOY

0.1g

– 28 –

Sony Corporation