Page 1
CXD1175AM/AP
8-bit 20MSPS Video A/D Converter (CMOS)
Description
The CXD1175A is an 8-bit CMOS A/D converter
for video use. The adoption of a 2-step parallel
system achieves low consumption at a maximum
conversion speed of 20MSPS minimum, 35MSPS
typical.
Features
• Resolution: 8 bit ± 1/2LSB (DL)
• Maximum sampling frequency: 20MSPS
• Low power consumption: 60mW (at 20MSPS typ.)
(reference current excluded)
• Built-in sampling and hold circuit
• Built-in reference voltage self-bias circuit
• 3-state TTL compatible output
• Power supply: 5V single
• Low input capacitance: 11pF
• Reference impedance: 300Ω (typ.)
Applications
TV, VCR digital systems and a wide range of fields
where high speed A/D conversion is required.
Structure
Silicon gate CMOS monolithic IC
CXD1175AM
24 pin SOP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD 7V
•Reference voltage VRT,VRBVDD + 0.5 to Vss – 0.5V
• Input voltage VIN VDD + 0.5 to Vss – 0.5V
(Analog)
• Input voltage VI VDD + 0.5 to Vss – 0.5V
(Digital)
• Output voltage VO VDD + 0.5 to Vss – 0.5V
(Digital)
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVss 4.75 to 5.25 V
DVDD, DVss
| DVss – AVss | 0 to 100 mV
• Reference input voltage
VRB 0 and above V
VRT 2.8 and below V
• Analog input VIN 1.8Vp-p above
• Clock pulse width
TPW1, TPW0 23ns (min) to 1.1µs (max)
• Operating ambient temperature
Topr –40 to +85 °C
CXD1175AP
24 pin DIP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E89321F78-PS
Page 2
Block Diagram and Pin Configuration
CXD1175AM/AP
OE
DV
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DV
CLK
SS
DD
10
11
12
1
24
DVSS
Reference voltage
VRB
2
3
4
5
Lower data
latches
Lower encoder
(4 bit)
Lower
comparators with
S/H (4 bit)
6
7
Lower encoder
(4 bit)
8
Upper data
Lower
comparators with
S/H (4 bit)
23
20
19
18
17
22
21
VRBS
AVSS
AVSS
V
IN
AVDD
VRT
latches
9
Upper encoder
(4 bit)
Upper
comparators with
S/H (4 bit)
Clock generator
16
15
14
13
VRTS
AVDD
AVDD
DV
DD
– 2 –
Page 3
Pin Description and Equivalent Circuits
No. Symbol Equivalent circuit Description
DVDD
When OE = Low, Data is output.
1
OE
1
When OE = High, D0 to D7 pins turn
to High impedance.
DVSS
CXD1175AM/AP
2, 24
3 to 10
11, 13
12
16 VRTS
17
DVSS
D0 to D7
DVDD
CLK
VRT
Digital ground
Di
D0 (LSB) to D7 (MSB) output
Digital +5V
DVDD
12
DVSS
AVDD
Clock input
Shorted with VRT generates, +2.6V.
16
AVDD
Reference voltage (Top)
23
14, 15, 18
19
20, 21
22 VRBS
VRB
AVDD
VIN
AVSS
19
17
23
Reference voltage (Bottom)
AVSS
Analog +5V
AVDD
Analog input
AVSS
Analog GND
AVSS
Shorted with VRB generates +0.6V.
22
– 3 –
Page 4
CXD1175AM/AP
Digital output
Compatibility between analog input voltage and the digital output code is indicated in the chart below.
Input signal
voltage
VRT
:
:
:
:
VRB
Clock
Amalog input
Data output
Step
0
:
127
128
:
255
TPW1 TPW0
N
N – 3 N – 2 N – 1 N N + 1
Digital output code
MSB LSB
1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
:
0 0 0 0 0 0 0 0
N + 1
N + 2
N + 3
N + 4
OE input
Output 1
Output 2
Td = 18ns
Timing Chart 1
tr = 4.5ns tf = 4.5ns
90%
2.5V
tPLZ
10%
tPHZ
90%
tPZL
tPZH
Timing Chart 2
10%
1.3V
1.3V
: Point for analog signal sampling.
5V
0V
OH
V
VOL (≠DVSS)
OH (≠DVDD)
V
V
OL
– 4 –
Page 5
Electrical Characteristics
CXD1175AM/AP
Analog characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Conversion speed
Analog input band width
(–1dB)
Offset voltage
Integral non-linearity error
Differential non-linearity erro
Differential gain error
Differential phase error
Aperture jitter
Sampling delay
∗1
The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”.
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2LSB of the voltage when the output data changes from “11111111” to “11111110”.
∗1
Fc
BW
EOT
EOB
EL
r
ED
DG
DP
taj
tsd
(Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
VDD = 4.75 to 5.25V
Ta = –40 to +85°C
VIN = 0.5 to 2.5V
fIN = 1kHz ramp
Envelope
Potential difference to VRT
Potential difference to VRB
End point
NTSC 40 IRE mod ramp
Fc = 14.3MSPS
0.5
–10
0
18
–35
+15
+0.5
±0.3
1.0
0.5
30
4
20
–60
+45
+1.3
±0.5
MSPS
MHz
mV
LSB
%
deg
ps
ns
– 5 –
Page 6
CXD1175AM/AP
DC characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Supply current
Reference pin current
Analog input capacitance
Reference resistance
(VRT to VRB)
Self-bias I
Self-bias II
Digital input voltage
Digital input current
Digital output current
IDD
IREF
CIN
RREF
VRB1
VRT1 – VRB1
VRT2
VIH
VIL
IIH
IIL
IOH
IOL
IOZH
IOZL
(Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
Fc = 20MSPS
NTSC ramp wave input
VIN = 1.5V + 0.07Vrms
Shorts VRB and VRBS
Shorts VRT and VRTS
VRB = AGND
Shorts VRT and VRTS
VDD = 4.75 to 5.25V
Ta = –40 to +85°C
VIH = VDD
VDD = max
OE = VSS
VDD = min
OE = VDD
VDD = max
VIL = 0V
VOH = VDD – 0.5V
VOL = 0.4V
VOH = VDD
VOL = 0V
4.5
230
0.60
1.96
2.25
3.5
–1.1
3.7
12
6.6
11
300
0.64
2.09
2.39
17
8.7
450
0.68
2.21
2.53
1.0
5
5
16
16
mA
mA
pF
Ω
V
V
V
µA
mA
µA
Timing
Item Symbol Conditions Min. Typ. Max. Unit
Output data delay
Tri-state output
enable time
Tri-state output
disable time
(Fc = 20MSPS, VDD = 4.75 to 5.25V, VRB = 0.5V, VRT = 2.5V, Ta = –40 to +85°C)
TDL
tPZH
tPZL
tPHZ
tPLZ
With TTL 1 gate and 10pF load
RL = 1kΩ, CL = 20pF
OE = 5V → 0V
RL = 1kΩ, CL = 20pF
OE = 0V → 5V
18
3
7
7
15
30
13
26
ns
ns
ns
– 6 –
Page 7
Electrical Characteristics Measurement Circuit
CXD1175AM/AP
Integral non-linearity error
Differential non-linearity error }measurement circuit
Offset voltage
+V
S2
IF A < B
S1: ON
S2: ON IF B > A
S1
–V
A < B A > B
DVM
VIN
DUT
CXD1175A
CLK (20MHz)
COMPARATOR
A8
to
A1
A0
"0" "1"
CONTROLLER
B8
B1
B0
88
to
BUFFER
000 · · · 00
8
111 · · · 10
Maximum operational speed
Differential gain error }measurement circuit
Differential phase error
3-state output measurement circuit
Measurement
point
To output pin
Note) CL includes the capacitance of the probe
and others.
to
DVDD
RL
RLCL
2.5V
F c – 1k Hz
S.G.
0.5V
NTSC
SIGNAL
SOURCE
100
IAE
0
–40
1
AM P
2
40 IR E
MODULATION
BURST
SYNC
V
IN 8 8
CXD
1175A
2.5V
0.5V
S.G.
(CW)
FC
Digital output current measurement circuit
VDD
2.5V
0.5V
VRT
VIN
VRB
CLK
OE
VOL
GND
ERROR RATE
TTL
ECL
–5.2V
CX20202A-1
620
CLK
10bit
D/A
H.P.F
1
2
VECTOR
SCOPE
COUNTER
D.G
620
D.P.
TTL
ECL
I
OL
2.5V
0.5V
+
–
–5.2V
VRT
VIN
VRB
CLK
OE
VDD
GND
VOH
I
OH
+
–
– 7 –
Page 8
Timing Chart 3
External clock
CXD1175AM/AP
Vi (1) Vi (2) Vi (3) Vi (4)
Analog input
Upper comparators block
Upper data
Lower reference voltage
Lower comparators A block
Lower data A
Lower comparators B block
S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4)
MD (0) MD (1) MD (2) MD (3)
RV (0) RV (1) RV (2) RV (3)
S (1) C (1) S (3) C (3)H (3)H (1)
LD (–1) LD (1)
C (0) S (2) C (2) S (4)H (0) H (2) H (4)
Lower data B
Digital output
LD (–2) LD (0) LD (2)
Out (–2) Out (–1) Out (0) Out (1)
Operation (See Block Diagram and Timing Chart)
1. The CXD1175AM/AP is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group
and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between
VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the
upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self
generation of VRT (Reference voltage top) and VRB (Reference voltage bottom).
– 8 –
Page 9
CXD1175AM/AP
2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It
features the following operating modes which are respectively indicated on the timing chart with S, H, C
symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.
3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled
with the falling edge of the first clock by means of the upper comparator block and the lower comparator A
block.
The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to
the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the
second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes
1. VDD, VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital
and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass
to the respective GND’s.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be
prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT
and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6V and VRB = 0.6V, is activated.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks
and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.
6. OE pin
By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.
7. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply.
This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
– 9 –
Page 10
Application Circuit
CXD1175AM/AP
+5V
V IN
+12V
C1
470µ
C3
47µ
C5
0.1µ
R2
180
C4
0.1µ
–12V –12V
C6
47µ
R1
120
∗
: Ceramic Chip Condenser
0.1µF
R3
500
Q1
R4
1k
R11
1k
R12
1k
R13
500
Q2
R5
2k
C2
10µ
IC1
µPC254
IC2
µPC254
R6
500
R7
500
R9
5k
+12V+5V
–12V
Q4
Q5
R8
100
Q3
R10
75
C13
10p
C12
0.1µ
C11
0.1µ
C9
47µ
C10
0.1µ
C8
C7
47µ
∗
+5V
+5V
CLOCK IN
13
14
15
16
17
18
CXD1175AM/AP
19
20
21
22
23
24
HC04
12
11
10
9
8
7
6
5
4
3
2
1
CLK
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
: Analog GND
: Digital GND
Note) It is necessary that AVDD and DVDD pins the common source of power supply.
The gain of analog input signal can be variable by adjustment of value of R3.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 10 –
Page 11
CXD1175AM/AP
8-bit 20MSPS ADC and DAC Evaluation Board
The CXD1175AP/CXA1106P PCB is evaluation PCB for the 8-bit high speed and low power consumption
CMOS A/D converter CXD1175AP and the 8-bit high speed bipolar D/A converter CXD1106P. This PCB
features a high speed and low power consumption CMOS A/D converter, analog input buffer, clock buffer,
latch and high speed bipolar D/A converter designed to fully enhance the performance of A/D and D/A
converters.
Block Diagram
V IN
ANALOG CIRCUIT
MOUNT PORTION
V REF
ANALOG INPUT
BUFFER/DRIVER
ANALOG CIRCUIT
MOUNT PORTION
V OUT
Characteristics
• Resolution 8bit
• Maximum conversion rate 20MHz
• Digital input level TTL level
• Supply voltage ±5.0V
CXA1106P
CXD1175AP
GND +5V –5V
8
DIGITAL CIRCUIT
MOUNT PORTION
CLOCK
DATA LATCH
OSC
SW
CLOCK
Unnecessary during
self-bias usage
8
BUFFER
Supply voltage
Item
Min. Typ. Max. Unit
+5V
–5V
Analog input
AC input voltage
Item
Gain (VIN = 2Vp-p input)
Offset voltage
Clock input
TTL compatible
Pulse width TCW1 25ns (min.)
TCW0 25ns (min.)
150
20
mA
Min. Typ. Max. Unit
0.5
0
2
5
V
– 11 –
Page 12
Analog Output (CXA1106) (RL > 10kΩ)
CXD1175AM/AP
Item
Min. Typ. Max. Unit
Analog output 0.9 1.0 1.1 V
Output Format (CXD1175A)
The table shows the output format of A/D converter.
Input signal
voltage
VRT
:
:
:
:
VRB
Step
0
:
127
128
:
255
Digital output code
MSB LSB
11111111
:
10000000
01111111
:
00000000
Timing Chart
Analog input
External clock
Tpw0
Tpw1
Item
Clock high time
Clock low time
Clock delay
Data delay AD
AD clock
AD output
Latch output
DA input
DA clock
DA output
Tdc
tPD (AD)
tDD
ts
tPD (DA)
th
Symbol Min.
TPW1
TPW0
Tdc
tPD (AD)
25
25
Typ.
18
Max.
24
30
Unit
ns
ns
ns
ns
Data delay (latch)
Set up time
Hold time
Data delay DA
tDD
tS
th
tPD (DA)
10
2
11
– 12 –
17
ns
ns
ns
ns
Page 13
CXD1175AM/AP
IN = 75Ω)
(R
0.1µ
SS
V
8
(Latch)
74S174
9
CLK
7
VSS
1
INPUT
75
1
14
R11
EXT/INT
OSC SWITCH
DVSS
DVDD
8
0.1
EXTERNAL CLOCK
14
DD
V
OSC OUT
0.1µ
SS
V
7
8
4
6
9
3
11
(INV Buffer)
12
2
74S04 or 74HC04
13
5
10
7
4
6
3
5
2
1
Clear
VSS
8
7
4
6
5
Clear
3
2
1
0.1µ
(Latch)
74S174
CLK
9
12
13
11
10
16
14
15
16
14
12
13
11
10
15
VDD
C14
0.1µ
DD
CLK
Vsel
AVSSAVSS
24
Vief
23
2
1
AVtl
5k
VR5
DVSS
DVDD
AVSS
D0 (LSB)D1D2D3D4
NC
22
21
20
4
3
5
VDD
AVdl
18
19
7
6
SS
V
VDD
D5
16
17
CXA1106 (DAC)
8
9
NC
CLK
(MSB) D7
0.1
C10
NC
NC
14
13
15
11
10
12
D6
NC
DV
D7
11
12
13
14
AVDD
DVDD
AVDD
10µ/16
C7
C8
0.1µ
0.1
DAC OUTPUT
OUTPUT GAIN ADJUST
AVDD
VRT
ADJUST
Q5
2k
VR4
Q4
R9
510
2k
VRB
VR3
ADJUST
R10
R4
510
510
AVSS
ADJUST
INPUT BIAS
D6
(MSB)
9
10
16
15
AVDD
VRTS
Q3
C2
/16
22µ
Q2
R5
390
C1
ADJUST
INPUT GAIN
D5D4D3D2D1
8
5
7
6
CXD1175A (ADC)
19
17
18
20
SS
VIN
VRT
C5
R7
0.1
AV
AVDD
C6
0.1
75
R8
2.2k
10k
VR2
R6
2.2k
Q1
R3
680
R2
120
470µ/6.3
51
R1
100
VR1
SS
AV
SS
DV
(LSB)
3
OE
2
1
D0
4
22µ/16
24
22
21
23
SS
VRB
AVSS
VRBS
DV
C13
0.1
47µ/10
C7
DV
DD
AV
DD
GND
+5V
–5V
C12
C11
47µ/10
47µ/10
Peripheral Circuit Board (Top View)
– 13 –
VIDEO INPUT
(RIN = 75Ω)
C2785
Q1 to Q5 (C2785)
EBC
Page 14
List of Parts
CXD1175AM/AP
resistor
R1 51Ω
R2 120Ω
R3 680Ω
R4 510Ω
R5 390Ω
R6 2.2kΩ
R7 75Ω
R8 2.2kΩ
R9 510Ω
R10 510Ω
R11 75Ω
VR1 100Ω
VR2 10kΩ
VR3 2kΩ
VR4 2kΩ
VR5 5kΩ
capacitor
C1 470µF/6.3V (chemical)
C2 22µF/16V (chemical)
C3 0.01µF
C4 10µF/16V (tamtalate)
C5 0.1µF
C6 0.1µF
C7 0.1µF
C8 0.1µF
C9 0.1µF
C10 0.1µF
C11 47µF/10V (chemical)
C12 47µF/10V (chemical)
C13 47µF/10V (chemical)
C14 0.1µF
transistor
Q1 2SC2785
Q2 2SC2785
Q3 2SC2785
Q4 2SC2785
Q5 2SC2785
IC
IC1 74S174
IC2 74S174
IC3 74S04
oscillator
OSC
others
connector BNC071
SW AT1D2M3
Method of Adjustment
1. Vgain (VR1)
Gain adjustment of the analog input.
2. Voffset (VR2)
Offset adjustment of the analog input.
3. Vref (VR3, VR4)
Adjustment of the A/D converter reference voltage.
VRB is adjusted at VR3, and VRT at VR4. Reference voltage is given with self-bias for PCB shipment.
4. Analog output gain (VR5)
Full-scale voltage of the D/A converter output is adjusted.
– 14 –
Page 15
CXD1175AM/AP
Points on the PCB Pattern Layout
1. Layout so that digital current does not flow to analog GND (part 1).
(See Component Side on page 19 for part 1.)
2. Capacitor C6 (between AVSS and AVDD) and capacitor C14 (between DVSS and DVDD) are important
factors to enhance the CXD1175A performance. Those capacitors should feature good high frequency
characteristics over 0.1µF (ceramic capacitor). Layout as close to the IC as possible.
3. Analog GND (AVSS) and Digital GND (DVSS) have a common voltage and a supply source. The DVSS of
A/D converter (part 2) location as close to the voltage source is possible will give even better results. That
is, a layout where the A/D converter is close to the voltage source is recommended. (See Component Side
on page 19 for part 2.)
4. AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13) are provided in the CXD1175A, and a common
voltage source should be used for them as for part 3. (See the paragraph for Latch Up Prevention.) (See
Soldering Side on page 19 for part 3.)
5. The A/D converter samples analog signals at the falling edge of clock. Accordingly, clocks fed to the A/D
converter should not be affected by jitter.
6. In this PCB, to evaluate A/D and D/A converters independently, an independent layout has been adopted
for the analog GND of A/D and D/A converters, from the voltage generation source. For the user’s actual
PCB even a common source poses no problems. For the CXA1106, as analog signals are output with the
supply voltage as reference, take care not to let noise interfere with the analog VDD of D/A converter.
– 15 –
Page 16
CXD1175AM/AP
Notes on Operation
1. Reference voltage
The self-bias function where VRT = 2.6V and VRB = 0.6V is available by shorting VRT and VRTS, VRB and
VRBS in the CXD1175A. At the PCB, either self-bias or external reference voltage can be selected
according to the way the jumper wire is connected. For shipment, the reference voltage is provided by the
self-bias. Also, when reference voltage is to be provided from the exterior, adjust the dynamic range (VRT –
VRB) to 1.8Vp-p or over.
2. Clock input
There are two modes for the PCB clock input.
1) Through an external signal generator (external clock)
2) Using a crystal oscillator (internal clock)
These two modes can be selected with a switch on the PCB.
They are given from the external clock for shipment.
3. Peripheral through hole
There is a number of through holes at the analog input, output and LOGIC areas. Those are used when
additional circuits are to be mounted on the PCB circuit.
4 The two latch ICs (74S174) on the circuit diagram are not absolutely necessary for the A/D and D/A
converter evaluation. That is, when the A/D converter output data is directly input to D/A converter input,
normal operation is maintained. However, as A/D converter output data is hardly ever subject to D/A
conversion without the digital signal processing, the PCB has been fitted with the 74S174 to show a layout
example for digital signal processing IC.
5. Analog input buffer & driver block is designed to handle conventional video band signals. Accordingly, for
tests involving frequencies higher than that, methods shown in the figure below are recommended.
R7 75Ω
50Ω
S.G.
19
V IN
D1175A
High frequency input measurement circuit
– 16 –
Page 17
CXD1175AM/AP
Latch Up Prevention
The CXD1175A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
DD
DV
AV
DD
11
13
C14
2
24
+5V
AV
+5V
SS
C6
14
20
18
15
AVDD DVDD
CXD1175A
AVSS DVSS
21
DVSS
b. When analog and digital supplies are from a common source
(i)
DD
DV
11
13
C14
2
24
+5V
AV
SS
C6
14 15
20
18
AVDD DVDD
CXD1175A
AVSS DVSS
21
DVSS
DIGITAL IC
DIGITAL IC
(ii)
+5V
AV
C6
SS
DVDD
14 15
AVSS DVSS
20
18
AVDD DVDD
CXD1175A
21
11
2
DVSS
– 17 –
13
C14
DIGITAL IC
24
Page 18
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
DV
DD
AV
DD
CXD1175AM/AP
14 15
18
11
13
AVDD DVDD
+5V
+5V
C6
CXD1175A
AVSS DVSS
AV
SS
20
21
2
24
DVSS
b. When analog and digital supplies are from common source
(i)
DV
DD
AVDD
11
13
2
24
+5V
AV
C6
SS
14 15
18
AVDD DVDD
CXD1175A
AVSS DVSS
21
20
DVSS
DIGITAL IC
DIGITAL IC
(ii)
AVDD
+5V
AV
SS
DD
DV
14 15
18
11
AVDD DVDD
CXD1175A
AVSS DVSS
20
21
2
DVSS
13
DIGITAL IC
24
– 18 –
Page 19
Silk Side
Component side
CXD1175AM/AP
Soldering side
1
– 19 –
Page 20
Package Outline Unit: mm
CXD1175AM
CXD1175AM/AP
24PIN SOP (PLASTIC)
CXD1175AP
+ 0.4
15.0 – 0.1
1324
+ 0.3
5.3 – 0.1
112
1.270.45 ± 0.1
± 0.12
M
7.9 ± 0.4
6.9
0.2 – 0.05
+ 0.1
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-24P-L01
∗SOP024-P-0300-A
MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY/PHENOL RESIN
SOLDER PLATING
COPPER ALLOY / 42ALLOY
0.3g
+ 0.4
1.85 – 0.15
0.15
+ 0.2
0.1 – 0.05
0.5 ± 0.2
24PIN DIP(PLASTIC)
+ 0.4
30.2 – 0.1
24 13
+ 0.3
10.16
8.5 – 0.1
112
SONY CODE
EIAJ CODE
JEDEC CODE
0.5 ± 0.1
1.2 ± 0.15
DIP-24P-01
DIP024-P-0400
2.54
+ 0.4
3.7 – 0.1
0.5 MIN
Two kinds of package surface:
1.All mat surface type.
3.0 MIN
2.All mirror surface type.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
2.0g
+ 0.1
0.25 – 0.05
0° to 15°
– 20 –
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