Datasheet CXA3275Q Datasheet (Sony)

PLL/OSC/MIX IC for Digital Tuner

Description

The CXA3275Q is a monolithic tuner IC for single
conversion system digital broadcast tuners. This IC
integrates three sets of local oscillator and mixer
circuits (VHF Low Band/ VHF High Band/UHF Band),
an IF amplifier and a tuning PLL onto a single chip,
enabling further miniaturization of the tuner.

Features

• Balanced oscillators with low-phase noise and

excellent oscillation stability (UHF: 4 pins, VHF: 2 pins)

• High linearity mixer and IF amplifier

• IF output switchable between balanced and

unbalanced

• Low-phase noise PLL synthesizer

(3-wire bus format)

• Reference frequency programmable in 4 bits

• On-chip high voltage drive transistor for charge

pump

• On-chip 4-output band switch (PNP transistor

on/off)

• 40-pin QFP package

Applications

Digital CATV tuners

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage Vcc, PLLVcc –0.3 to +6.0 V

IFVcc –0.3 to +6.0 V

• Storage temperature
Tstg –55 to +150 °C

• Allowable power dissipation
PD 1.58 W

(when mounted on a printed circuit board)

Operating Conditions

• Supply voltage Vcc, PLLVcc 4.5 to 5.5 V

IFVcc 4.5 to 5.5 V

• Operating temperature
Topr –40 to +80 °C

– 1 –

E00461-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA3275Q

40 pin QFP (Plastic)

This IC has pins whose electrostatic discharge strength is weak as a high-frequency process is used for this IC.
Take care when handling the IC.

– 2 –

CXA3275Q

Block Diagram and Pin Configuration

VLMIX VHMIX UMIX

UOSC

VHOSCVLOSC

IF Amp

Ref
OSC

Band
SW

Charge
Pump

Ref
Div.

Lock
Det

Program
Div.

Phase
Det

Bus
Interface

1

2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

32

31

33

34

35

36

37

38

39

40

UIN2

Vcc

MIXOUT1

MIXOUT2

GND

IFIN1

IFIN2

RFGND

UOSCB1

UOSCE1

NC

BS4

BS3

BS2

BS1

VLIN1

VLIN2

VHIN1

VHIN2

UIN1

IFOUT1

IFOUT2

IFVcc

IFGND

VLOSC2

VLOSC1

VHOSC2

VHOSC1

UOSCB2

UOSCE2

PLLVcc

CP

VT

XI

XO

PLLGND

LOCK

SDA

SCL

CE

– 3 –

CXA3275Q

Pin Description and Equivalent Circuit

Pin
No.

Symbol

Pin voltage

[V]

1

IFOUT1

2

3

IFOUT2

IFVcc

2.5

—

5

VLOSC2

6

VLOSC1

2.5

2.5

Equivalent circuit Description

IF outputs.
IFOUT1 and IFOUT2 output a
balanced signal.
When taking a signal as an
unbalanced output, connect
the pin not used for output to
IFVCC. At this time the output
stage current is saved.

IF amplifier power supply.

4 IFGND

—

IF amplifier GND.

13

RFGND

—

Analog GND.

External resonance circuit
connection for VL oscillator.

40k

IFVcc

3

1
2

20k

20k

3k
3k

20k20k

Vcc

5

19

6

7

VHOSC2

8

VHOSC1

2.5

2.5

External resonance circuit
connection for VH oscillator.

20k

20k

3k
3k

20k20k

Vcc

7

19

8

12

UOSCB1

UHF: 2.2
VL/VH: 2.3

11

UOSCE1

UHF: 1.5
VL/VH: –

10

UOSCE2

UHF: 1.5
VL/VH: –

9

UOSCB2

UHF: 2.2
VL/VH: 2.3

External resonance circuit
connection for UHF oscillator.

3k

3k

Vcc

91910 11 12

– 4 –

CXA3275Q

14

IFIN2

15

IFIN1

2.7

2.7

17

MIXOUT2

18 MIXOUT1

—

—

IF inputs.

16 GND

0

GND

19

Vcc

—

Band switch, mixer and local
oscillator circuit power supply.

Mixer outputs.

IFVcc

3

14
15

5k 5k

18 17

20 20

20

UIN2

21 UIN1

VL/VH: 0
UHF: 1.9

VL/VH: 0
UHF: 1.9

UHF inputs.

20

19

21

Vcc

25

VLIN1

VH: 3.16
VL: 3
UHF: 3.24

24

VLIN2

VH: 3.16
VL: 3
UHF: 3.24

23

VHIN1

VH: 3
VL: 3.16
UHF: 3.24

22

VHIN2

VH: 3
VL: 3.16
UHF: 3.24

VH and VL inputs.

Vcc

19

24
25

22
23

5k 5k

Pin
No.

Symbol

Pin voltage

[V]

Equivalent circuit Description

– 5 –

CXA3275Q

26

BS1

29 BS4

ON: 4.9
OFF: 0

Pin 26: Band switch 1 output.
Pin 29: Band switch 4 output.

The pin corresponding to the
band selected by the data
goes High.

20k

Vcc

19

26
29

27

BS2

28 BS3

ON: 4.9
OFF: 0

Pin 27: Band switch 2 output.
Pin 28: Band switch 3 output.

The pin corresponding to the
band selected by the data
goes High.

20k

70k

30k

Vcc

19

27
28

32

CP

33

VT

—

—

Charge pump output.
Connects the loop filter.

Transistor open collector
output for varicap diode drive.
Connects the loop filter.

50

33

32

31

PLLVcc

30 NC

—

NC.

31 PLLVcc

—

PLL VCC.

34

XI

35

XO

3.1

3.0

External reference clock input.
Connects the crystal when
used as a reference oscillator.

Connects the crystal when
used as a reference oscillator.

PLLVcc

31

500

34
35

36 PLLGND

— PLL GND.

Pin
No.

Symbol

Pin voltage

[V]

Equivalent circuit Description

– 6 –

CXA3275Q

37

LOCK

5.0

(lock)

0.2

(unlock)

Lock detection.
High when locked, Low when

unlocked.

37

31

PLLVcc

38

SDA

—

Data input.

PLLVcc

20

5k

31

38

39

SCL

—

Clock input.

PLLVcc

5k

31

39

40

CE

1.25

(when open)

Enable pin.

PLLVcc

50k

150k

31

40

Pin

No.

Symbol

Pin voltage

[V]

Equivalent circuit Description

– 7 –

CXA3275Q

Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.)

(Vcc = 5V, IFVcc = 5V, PLLVcc = 5V, Ta = 25°C)

Circuit Current

OSC/MIX/IF Amplifier Block

CG1-1
CG1-2
CG1-3
CG1-4
CG1-5
CG1-6
CG2-1
CG2-2
CG2-3
CG2-4
CG2-5
CG2-6
NF1
NF2
NF3
NF4
NF5
NF6

Conversion gain 1

∗1

(Unbalanced)

Conversion gain 2

∗

1, ∗2

(Balanced)

Noise figure

∗1, ∗3

(Unbalanced)

VL operation f

RF = 50MHz, fIF = 39MHz

VL operation fRF = 150MHz, fIF = 39MHz
VH operation fRF = 150MHz, fIF = 39MHz
VH operation fRF = 450MHz, fIF = 39MHz
UHF operation fRF = 450MHz, fIF = 39MHz
UHF operation fRF = 850MHz, fIF = 39MHz
VL operation fRF = 50MHz, fIF = 39MHz
VL operation fRF = 150MHz, fIF = 39MHz
VH operation fRF = 150MHz, fIF = 39MHz
VH operation fRF = 450MHz, fIF = 39MHz
UHF operation fRF = 450MHz, fIF = 39MHz
UHF operation fRF = 850MHz, fIF = 39MHz
VL operation fRF = 50MHz, fIF = 39MHz
VL operation fRF = 150MHz, fIF = 39MHz
VH operation fRF = 150MHz, fIF = 39MHz
VH operation fRF = 450MHz, fIF = 39MHz
UHF operation fRF = 450MHz, fIF = 39MHz
UHF operation fRF = 850MHz, fIF = 39MHz

18.5
19
19
19

23.5

24.5

25.5
26
26
26

30.5

31.5

21.5
22
22
22

26.5

27.5

28.5
29
29
29

33.5

34.5

15.5
15
15
15

10.5

10.5

25

25.5

25.5

25.5
30
31
32

32.5

32.5

32.5
37
38

18.5
18
18
18

13.5

13.5

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

Symbol

Item

Measurement conditions Min. Typ. Max. Unit

Symbol

Item

Measurement conditions Min. Typ. Max. Unit

Iccv1

Iccu1

Iccv2

Iccu2

Circuit current

During VHF operation
Unbalanced output
Band switch output open

During UHF operation
Unbalanced output
Band switch output open

During VHF operation
Balanced output
Band switch output open

During UHF operation
Balanced output
Band switch output open

80

85

91

100

113

120

130

137

145

151

170

177

mA

mA

mA

mA

– 8 –

CXA3275Q

OSC/MIX/IF Amplifier Block (cont.)

CM1-1

CM1-2

CM1-3

CM1-4

CM1-5

CM1-6

CM2-1

CM2-2

CM2-3

CM2-4

CM2-5

CM2-6
Pomax

PN 1

PN 2

C/N

∗1, ∗4
1% cross modulation 1
(Unbalanced)

∗1, ∗5
1% cross modulation 2
(Unbalanced)

Maximum output power

∗6

Phase noise 1

∗6

Phase noise 2

∗6, ∗7

Oscillator phase noise

VL operation fD = 50MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)

VL operation fD = 150MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)

VH operation fD = 150MHz, fIF

= 39MHz,

f

UD = ±6MHz (80% AM)

VH operation fD = 450MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)

UHF operation fD = 450MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)

UHF operation fD = 850MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)

VL operation fD = 50MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)

VL operation fD = 150MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)

VH operation fD = 150MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)

VH operation fD

= 450MHz, fIF = 39MHz,

f

UD = ±12MHz (40% AM)

UHF operation fD = 450MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)

UHF operation fD = 850MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)

50Ω load, saturation output, fIF = 45MHz
1kHz offset

Phase comparison frequency = 218.75kHz
Charge pump current: 900µA

10kHz offset
Phase comparison frequency = 218.75kHz
Charge pump current: 900µA

50kHz offset
Phase comparison frequency = 218.75kHz
Charge pump current variable

83.5

83.5

83

83

78

77

91.5

91.5

90

89

85

84

+10

60

87.5

87.5

87

87

82

81

95.5

95.5

94

93

89

88

+13

73

90

70

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBµ

dBm

dBc/Hz

dBc/Hz

dBc

Symbol

Item

Measurement conditions Min. Typ. Max. Unit

– 9 –

CXA3275Q

∗1

Value measured with the untuned input.

∗2

Value compensated for the loss due to the external parts connected to Pins 1 and 2, and converted to the
IC output pin amplitude.

∗3

Noise figure is the direct-reading value of NF meter in DSB.

∗4

∗5

∗6

Value when 14MHz (300mVp-p) is SG (Hewlett-Packard Japan, Ltd.: 8644A) input as the external REF
CLOCK.

∗7

The spectrum analyzer is set for SPAN:100kHz, RBW:3kHz and VBW:100Hz.

SG1

SG2

DUT

Ypad

fD
–30dBm

f

D ± 6MHz

AM80%, Audio 100kHz

Spectrum analyzer

Input value (SG2, 50Ω termination) when S/I = 46dB with the spectrum analyzer

SG1

SG2

DUT

Ypad

fD
–30dBm

f

D ± 12MHz

AM40%, Audio 100kHz

Spectrum analyzer

Input value (SG2, 50Ω termination) when S/I = 46dB with the spectrum analyzer

– 10 –

CXA3275Q

PLL Block

LUT1
LUT2
REFL

VIH
VIL
IIH
IIL

VIH
VIL
IIH
IIL

ICPO2
ICPO4

VTH
VTL

FXTOSC
REFIN1
REFIN2

IBS
VSAT
LeakBS

VLOCKH
VLOCKH

Lock-up time 1
Lock-up time 2
Reference leak

CL and DA input

"H" level input voltage
"L" level input voltage
"H" level input current
"L" level input current

CE input

"H" level input voltage
"L" level input voltage
"H" level input current
"L" level input current

CPO (charge pump)

Output current 1
Output current 2

VT (VC voltage output)

Maximum output voltage
Minimum output voltage

REFOSC

Oscillation frequency range
Drive frequency
Drive level

Band SW

Output current
Saturation voltage
Leak current

LOCK

"H" output voltage
"L" output voltage

fosc 89MHz ←→ fosc 479MHz
fosc 479MHz ←→ fosc 889MHz
Phase comparison frequency = 218.75kHz

VIH = Vcc
VIL = GND

VIH = Vcc
VIL = GND

When 300µA is selected
When 900µA is selected

Sink current = 1mA

External reference clock: sine wave

When ON
When ON Source current = 5mA
When OFF IFV

CC = 5.5V

When locked
When unlocked

3

GND

3

GND

±210
±600

3
3

250

Vcc – 1

0

10
10
65

0

–0.2

100
–35

±300
±900

0.3

4

14

350

150

0.5

Vcc – 0.3

0.1

Vcc

1.5

–0.1

–4

Vcc

1

200

–100

±420

±1215

33

0.8

5

20

500

–5

300

3

Vcc

0.5

ms
ms

dBc

V

V
µA
µA

V

V
µA
µA

µA
µA

V

V

MHz
MHz

mVp-p

mA
mV

µA

V

V

Symbol

Item

Measurement conditions Min. Typ. Max. Unit

– 11 –

CXA3275Q

PLL Block (cont.)

Symbol

Item

Measurement conditions Min. Typ. Max. Unit

tSD
tHD
tWE
tSE
tHE

Bus timing (3-wire bus)

Data setup time
Data hold time
Enable waiting time
Enable setup time
Enable hold time

300
600
300
300
600

ns
ns
ns
ns
ns

– 12 –

CXA3275Q

Electrical Characteristics Measurement Circuit

100k 100k 100k 100k

1n 1n 1n 1n

1n

1n

1n

4T

4T

39p

39p

6T

5V

10µ

6T

1n1n

0.5p
(UK)

0.5p (UK)

0.5p (UK)

1T363

0.5p
(UK)

1T363

56p

56p

12p12p12p12p

8p

8p

2.5p

4p

1.3k

10k

L3

3.3k

3k10k

3k10k

3.3k

1n

1n

5V

20203030

100p220p

1T363 1T363

L1 L2

56p

56p

1n

200

200

2k

10µ

30k

5.1k

200

1n

1n

47n

10n

20

µ-com

5V

30V

100n

100p

51

Inductance Constants

L1
L2
L3

0.5

0.5

0.5

7.5T

1.5T

1.5T

3.2φ

3.2φ

3.4φ

Number of windings Winding diameterWire diameter

UHF

1 2

3 4 5 6 7 8 9

10

11

12

13

14

15

16

17

18

19

20

21

2223

24

25

2627

28

29

30

32

31

33

34

35

36

37

38

39

40

UIN2

Vcc

MIXOUT1

MIXOUT2

GND

IFIN1

IFIN2

RFGND

UOSCB1

UOSCE1

NC

BS4

BS3

BS2

BS1

VLIN1

VLIN2

VHIN1

VHIN2

UIN1

IFOUT1

IFOUT2

IFVcc

IFGND

VLOSC2

VLOSC1

VHOSC2

VHOSC1

UOSCB2

UOSCE2

PLLVcc

CP

VT

XI

XO

PLLGND

LOCK

DA

CL

CE

VHF Low

VHF High

REF CLOCK

∗

1

For IF balanced output

4T

4T

1n

1n

180

180

1 2

IF

IF

∗1

: 14MHz, sine wave, 300mVp-p input (Hewlett-Packard Japan, Ltd.: 8644A)

– 13 –

CXA3275Q

Description of Operation

The CXA3275Q is a tuner IC which frequency converts 55 to 860MHz cable digital broadcasts to IF.
In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC
also integrates a PLL circuit for local oscillation frequency control onto a single chip.
The functions of the various circuits are described below.

1. Mixer circuit

This circuit outputs the frequency difference between the signal input to VLIN, VHIN or UIN and the local
oscillation signal.
There are three sets of mixer circuits for VHF Low Band, VHF High Band and UHF Band.
VHF Low and VHF High are common emitter type mixer input circuits, and UHF is a common base type
mixer input circuit.

2. Local oscillation circuit

A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and
inductance.
There are three sets of oscillation circuits for VHF Low Band, VHF High Band and UHF Band.
VHF Low and VHF High are 2-pin fully differential oscillation circuits and UHF is a 4-pin fully differential
oscillation circuit.

3. IF amplifier circuit

This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage.
IF output is low impedance (emitter follower output), and can be selected from balanced and unbalanced
output.
When unbalanced output is selected, the output stage current can be saved by connecting the pin not used
for output to IFVCC.

4. PLL circuit

This PLL circuit controls the local oscillation frequency.
It consists of a programmable divider, phase comparator, charge pump and reference oscillator.
The control format supports the 3-wire bus format.

5. Band switch circuit

The MT58A has four sets of built-in PNP transistors which can be controlled by the bus data.
These outputs switch the on-chip mixer and oscillator circuits, and the relationship with the control data is
as shown in the table below.

Relationship between the Band Switch Data and Mixer/Oscillator Operation

Band switch data

BS1

∗
∗
∗

BS2

1
0
0

BS3

0
1
0

BS4

∗
∗
∗

Mixer circuit

VHF Low

O

X
X

VHF High

X

O

X

UHF

X
X

O

Oscillation circuit

VHF Low

O
X
X

VHF High

X

O

X

UHF

X
X
O

∗: Don't care
O: Operating
X: Not operating

– 14 –

CXA3275Q

Description of PLL Block

The CXA3275Q supports the 3-wire bus control format.
Serial data is transferred using the DA pin (DATA), CL pin (CLOCK) and CE pin (ENABLE) inputs. Data is
loaded to the shift register at the falling edge of the clock signal, and is latched at the falling edge of the enable
signal.
The clocks during the enable period are counted, and 28 bits of data as counted from the rising edge of the
enable signal are loaded as valid data.
The MT58A has the power-on reset function and the register data become all "0" after the power is turned on.
The threshold value of the power-on reset is approximately 3.0V.

The VCO lock frequency is obtained according to the following formula.

fosc = fref × (16M + S) fosc: Local oscillator frequency fref: Phase comparison frequency

M: Main divider frequency division ratio S: Swallow counter frequency division ratio

The variable frequency division ranges of M and S are as follows, and are set as binary.

S < M ≤ 8191
0 ≤ S ≤ 15

The control format is as shown below.
Serial data (total 28 bits): Band data (4 bits) + various settings (3 bits)

+ reference frequency data (4 bits) + frequency data (17 bits)

Invalid dataFrequency dataVarious dataBand switch dataInvalid data

DATA

BS4 BS3 BS2 0 CP R2 R1 R0 R3 M12 M11 S2 S1 S0CD

CLOCK

145 1112 28

ENABLE

Latch

Time

BS1

M0 to: Main divider frequency division ratio setting
S0 to: Swallow counter frequency division ratio setting
CD: Charge pump OFF and varicap output OFF (when "1")
CP: Charge pump current switching (See the Charge Pump Current Table.)
BS1 to BS4: Band switch control (Output PNP transistor ON when "1". See the Band Switch Output Table.)
R0 to R3: Reference divider frequency division ratio setting. (See the Reference Divider Frequency

Division Ratio Table.)

– 15 –

CXA3275Q

Reference Divider Frequency Division Ratio Table

R3

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

R2

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

R1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

R0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Frequency division ratio

2
4

8
16
32
64

128
256
512

6
12
24
48
96

192
384

Band switch data

BS1

1
0
0
0

BS2

0
1
0
0

BS3

0
0
1
0

BS4

0
0
0
1

Band switch pins

BS1

ON

OFF
OFF
OFF

BS2

OFF

ON
OFF
OFF

BS3
OFF
OFF

ON

OFF

BS4
OFF
OFF
OFF

ON

Operating mode

(MIX/OSC)

UHF

VL

VH

UHF

Band Switch Output Table

Charge Pump Current Table

Charge pump current CP

300µA
900µA

0
1

<Supplement>

• Operation for Power On
When the data transfer is not performed after the power on, both the mixer and oscillator blocks operate in
UHF as the register data are all "0" by the power-on reset.
At this time, the Pin 33 (VT) voltage becomes the value equal to the varicap diode supply voltage (30V) when
the external clock is input to Pin 34 (XI) or when the crystal is connected to this pin for self-oscillation. When
the external clock is not input simultaneously with the power-on or the crystal is not connected, the Pin 33
voltage becomes unstable.

– 16 –

CXA3275Q

3-wire Bus Timing Chart

DATA

CLOCK

ENABLE

3V

3V

1.5V

3V

1.5V

tSD tHD

tWE tSE tHE

tSD: Data setup time
tHD: Data hold time

tHE: Enable hold time
tWE: Enable waiting time

t

SE: Enable setup time

1.5V

– 17 –

CXA3275Q

Characteristics Graphs

UHF

VHF

Circuit current vs. Supply voltage

(Balanced output)

170

150

160

140

120

130

100

110

90
80
70

4.4 4.6 4.8 5.0 5.2 5.4 5.6
Supply voltage [V]

Circuit current [mA]

Band SW output voltage vs. Output current

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5
0246810121416

Output current [mA]

Output voltage [V]

UHF

VHF

Circuit current vs. Supply voltage

(Unbalanced output)

150

130

140

120

100

110

80

90

70
60
50

4.4 4.6 4.8 5.0 5.2 5.4 5.6
Supply voltage [V]

Circuit current [mA]

BS1
BS2
BS3
BS4

– 18 –

CXA3275Q

UHF

Conversion gain vs. Reception frequency

(Untuned input)

35
30

25

20

15

10

5

0

0 200

100 300 600500400 700 800 900

Reception frequency [MHz]

CG – Conversion gain [dB]

UHF

1% adjacent cross modulation vs. Reception frequency

(Untuned input)

120

100

80

60

40

20

0

Reception frequency [MHz]

CM – 1% adjacent cross modulation [dBµ]

VH

fIF = 39MHz

UHF

Noise figure vs. Reception frequency

(Untuned input, in DSB)

35
30

25

20

15

10

5

0

0 200

100 300 600500400 700 800 900

0 200100 300 600500400 700 800 900

Reception frequency [MHz]

NF – Noise figure [dB]

fIF = 39MHz

VL

VH

VL

fD – 12MHz
fD + 12MHz

fIF = 39MHz
(100kHz 40% AM)

UHF

1% adjacent cross modulation vs. Reception frequency

(Untuned input)

120

100

80

60

40

20

0

Reception frequency [MHz]

CM – 1% adjacent cross modulation [dBµ]

0 200100 300 600500400 700 800 900

VL

fD – 6MHz
fD + 6MHz

fIF = 39MHz
(100kHz 80% AM)

VH

VL

VH

– 19 –

CXA3275Q

UHF

OSC phase noise vs. Reception frequency

(Untuned input)

120

110

100

90
80
70
60
50
40
30
20
10

0

0 200

100 300 600500400 700 800 900

Reception frequency [MHz]

OSC phase noise [dBc/Hz]

fIF = 39MHz

UHF

Oscillation frequency supply voltage fluctuation

(PLL off)

600
400

200

0

–200

–400
–600

–800

0 200 600

400 800 1000

Reception frequency [MHz]

+B drift [kHz]

VL

VH

Input/output characteristics (Untuned input)

20

10

0

–10

–20

–30

–40

–50

–60

–50 –40

–30 –20 –10 0 10 20

Input level [dBm] (SG setting value)

Output level [dBm]

fIF = 39MHz

VL

VH

VCC – 10%
VCC + 10%

Supply voltage = 5V

fRF = 440MHz (VH)

f

RF = 50MHz (VL)

f

RF = 850MHz (UHF)

10kHz offset

1kHz offset

100kHz offset

– 20 –

CXA3275Q

VHF Low Input Impedance

0

50

55M

150M

j25

j50

j100

–j25

–j50

–j100

S11

1n

24 25

VHF High Input Impedance

0

50

150M

450M

j25

j50

j100

–j25

–j50

–j100

1n

22 23

S11

– 21 –

CXA3275Q

UHF Input Impedance

0

50

j25

j50

j100

–j25

–j50

–j100

1n

20 21

400

500

600

700

800

900

S11

IF Output Impedance

0

50

50M

40M

20M

30M

j25

j50

j100

–j25

–j50

–j100

S11

1n 5V

1 2 3

– 22 –

CXA3275Q

Sony Corporation

Package Outline Unit: mm

SONY CODE
EIAJ CODE
JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS

EPOXY RESIN
SOLDER / PALLADIUM

42/COPPER ALLOY

PACKAGE STRUCTURE

PLATING

0.2g

QFP-40P-L01
QFP040-P-0707

40PIN QFP (PLASTIC)

9.0 ± 0.4
+ 0.4

0.3 – 0.1

1

10

11

20

21

30

31

40

1.5 – 0.15

+ 0.35

0.127 – 0.05

+ 0.1

(8.0)

A

ADETAIL

0.1 – 0.1

+ 0.15

+ 0.15

7.0 – 0.1

0.5 ± 0.2

0.1

M

0.24

0.65

0° to 10°

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).