Datasheet CXB1567Q Datasheet (Sony)

CXB1567Q

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Limiting Amplifier for Optical Fiber Communication Receiver

Description

The CXB1567Q achieves the 2R optical-fiber
communication receiver functions (Reshaping and
Regenerating) on a single chip. This IC is also
equipped with the signal interruption alarm output
function, which is used to discriminate the existence
of data input.

Features

• Auto-offset canceller circuit

• Signal interruption alarm outputs

• Single 5V power supply

Applications

• SONET/SDH: 622.08Mb/s

• Fiber channel: 531.25Mb/s

48 pin QFP (Plastic)

Absolute Maximum Ratings

• Power supply VCC – VEE –0.3 to +7.0 V

• Storage temperature Tstg –65 to +150 °C

• Input voltage difference: | VD – VD |

Vdif 0.0 to +2.5 V

• Input voltage Vi –0.3 to VCC V

• Output current

(Continuous) IO 0 to 50 mA
(Surge current) 0 to 100 mA

Recommended Operating Conditions

• Supply voltage VCC – VEE 5.0 ± 0.5 V

• Operating temperature Ta –40 to +85 °C

• Termination resistor (Q/Q)

RT1 45 to 55 Ω

• Termination resistor (SD/SD)

RT2 45 to 55 Ω

• Termination voltage VCC – VTT 1.8 to 2.2 V

Structure

Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94709A63-ST

Block Diagram and Pin Configuration

CXB1567Q

VEE

N.C.

EED

V

CCD

V

EED

V

CCD

V

UP

DOWN

CCA

V

EEA

V

N.C.

N.C.

44

45

46

47

48

37

38

39

40

41

42

43

36

N.C.

35

N.C.

34

SD

Block

Alarm

33

SD

D

EE

V

32

31

Peak Hold1

Peak Hold2

D

EE

V

30

N.C.

29

R1

DA

CC

Q

28

V

Q

26

27

Buffer

Output

R3

R1

R2

EE

N.C.

V

25

N.C.

24

23

N.C.

Block

Limiting Amplifier Block

R3

20

19

18

17

16

15

14

13

22

21

EED

V

EED

V

EED

V

EED

V

EED

V

EED

V

CAP1

CAP1

N.C.

EE

V

R2

EE

V

2

N.C.

4

3

A

A

EE

CC

V

V

CAP3

CAP2

7

A

EE

V

6

5

9

8

D

10

D

N.C.

11

A

EE

V

121

N.C.

– 2 –

Pin Description

CXB1567Q

Pin

No.

1
2

3

4

5

6

Symbol

VEE
N.C.

VCCA

VEEA

CAP3

CAP2

Typical pin
voltage (V)

AC

DC

–

5V

0V

–

5V

–1.8V

–1.8V

Equivalent circuit

80

10p

40µA

Description

Negative power supply pin.
No connection.
Positive power supply pin for

analog block.

Negative power supply pin for
analog block.

5

6

80

Capacitance connection pins for

VCCA

alarm block peak hold circuit.
Connect each pin to VCC in
2000pF.

10p

CAP2 pin → Peak hold

capacitance
connection pin for
the limiting
amplifier signal

40µA

V

EEA

CAP3 pin → Peak hold

capacitance
connection pin for
the alarm
level setting block

7

8

9

10
11
12

13
14

15

16

17 to 22

23, 24

25

VEEA

D

N.C.
D

VEEA

N.C.
VEE
N.C.

CAP1

CAP1

VEED
N.C.

VEE

–

5V

–1.3V

–1.3V

–

5V

–

5V

–1.8V
–1.8V

–

5V

–

5V

–0.9V

to

–1.7V

10

Negative power supply pin for
analog block.

Limiting amplifier input pins

VCCA

Ensure that these inputs are
AC-coupled.

8

100

100

1K

7.5k

7.5k

130p

200

200

Negative power supply pin for
analog block.

16
15

No connection.
Negative power supply pin.

1K

V

EEA

No connection.

Capacitance connection pins to
determine the cut-off frequency
for feedback block.

Negative power supply pin for
digital block.

No connection.
Negative power supply pin.

– 3 –

Pin

No.

Symbol

Typical pin
voltage (V)

AC

DC

Equivalent circuit

CXB1567Q

Description

26
27

28

29

30

31, 32

33

34

N.C.

VCCDA

Q

Q

N.C.

VEED

SD

SD

0V

–5V

–0.9V

to

–1.7V

–0.9V

to

–1.7V

–0.9V

to

–1.7V

–0.9V

to

–1.7V

V

CCDA

VEED

V

CCDA

VEED

28

29

33
34

No connection.

Positive power supply pin for
output buffer.

Data signal output pins.
Terminate these pins in 50Ω at
VTT = –2V.

No connection.

Negative power supply pin for
digital block.

Alarm signal output pins.
Terminate these pins in 50Ω at
VTT = –2V.

35, 36

37
38

39

40

41

42

N.C.

VEE
N.C.

VEED

VCCD

VEED

VCCD

–5V

–5V

0V

–5V

0V

No connection.
Negative power supply pin.
No connection.
Negative power supply pin for

digital block.
Positive power supply pin for

digital block.
Negative power supply pin for

digital block.
Positive power supply pin for

digital block.

– 4 –

CXB1567Q

Pin

No.

43

44

45

46

47, 48

Symbol

UP

DOWN

VCCA

VEEA
N.C.

Typical pin
voltage (V)

DC

AC

–

4.7V

–5V

0V

–5V

43
44

Equivalent circuit

1k

100 100

5k

5k

VCCA

VEEA

Description

Resistor connection pins for alarm
level setting.

UP pin → When the

resistance
connected to this
pin is increased, the
alarm level
becomes higher.

DOWN pin →Normally

connect this pin
to VEE.

Positive power supply pin for
analog block.

Negative power supply pin for
analog block.

No connection.

– 5 –

CXB1567Q

Electrical Characteristics

• DC characteristics (VCC = VCCA = 0V, VEED= VEEA= VEE = –5V±10%, Ta = –40°C to +85°C, RT = 50Ω, VTT = –2V)

Item Symbol Conditions Min. Typ. Max. Unit
Supply current
Q/Q High output voltage
Q/Q Low output voltage
SD/SD High output voltage
SD/SD Low output voltage
Input offset voltage
D/D input resistance

IEE
VOH
VOL
VOHS
VOLS
VOFF
Rin

Ta = 0 to 85°C

–93
–1.03
–1.81
–1.25
–1.95

0.75

–59
–0.95
–1.70
–0.95
–1.76

70

1.0

–0.88
–1.62
–0.70
–1.57

1.25

mA

V

µV
kΩ

• AC characteristics (VCC = VCCA = 0V, VEED= VEEA= VEE = –5V±10%, Ta = –40°C to +85°C, RT = 50Ω, VTT = –2V)
Item Symbol Conditions Min. Typ. Max.

Maximum input data rate
Maximum input voltage
Limiting amplifier gain
Q/Q rise time
Q/Q fall time
Identification maximum voltage

amplitude of alarm level

B
VMAX
GL
TTLH
TTHL

VMIN

Single-ended input voltage at D
IC internal amplitude 400mVpp

20% to 80%

622.08
1000

66

20

240
240

450
450

Unit

Mbps

mVpp

dB

ps

mVpp

Hysteresis width
Alarm response assert time
Alarm response deassert time

∗1

CAP2, CAP3 pin capacitance = 2000pF, REX = 400Ω, Vin = 20mVpp (single ended)

∗2

CAP2, CAP3 pin capacitance = 2000pF, REX = 400Ω, Vin = 60mVpp (single ended)

Hys
TAS
TDAS

Electrically tested
Low → High ∗1(SD)
High → Low ∗2(SD)

2.5

4

6

0

8

100

dB

µs

100

– 6 –

DC Electrical Characteristics Measurement Circuit

CXB1567Q

REX

37

38

39

40

41

42

43

44

45

46

36

VTT

–2V

V

35

51 51

34

Alarm

Block

33

32

V

P/H 2

31

P/H 1

VTT

–2V

V

30

51 51

29

28

27

V

26

25

Block

Buffer

Output

Limiting Amplifier Block

24

23

22

21

20

19

18

17

16

C2

15

47

48

2

A

V

EE

–5V

4

3

C3 C3 C1

7

D

V

6

5

9

8

10

C1

11

14

13

121

V

– 7 –

AC Electrical Characteristics Measurement Circuit

Z0 = 50

CXB1567Q

REX

37

38

39

40

42

44

41

43

36

35

34

Alarm

33

Block

32

P/H 2

Z0 = 50

31

P/H 1

30

29

Z0 = 50

28

Z0 = 50

27

26

Buffer

Output

Block

Oscilloscope

50Ω Input

25

24

23

22

21

20

19

18

17

45

46

47

48

2

V

EE

–3V

VCC

+2V

4

3

2000pF 2000pF 1000pF 1000pF

7

RD

VD

6

5

9

8

10

Limiting Amplifier Block

11

RD

16

0.047µF

15

14

13

121

– 8 –

Application Circuit

VTT

–2.0V

51 51 51 51

CXB1567Q

273

39

44

45

47

48

37

38

40

41

42

43

46

36

35

34

Alarm

33

Block

32

P/H 2

31

P/H 1

30

29

28

27

26

25

Block

Buffer

Output

Limiting Amplifier Block

24

23

22

21

20

19

18

17

16

0.047µF

15

14

13

2

VEE

–5.0V

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent
and other right due to same.

4

3

2000pF 2000pF 1000pF 1000pF

7

VD

6

5

9

8

50

10

50

11

121

– 9 –

CXB1567Q

Notes on Operation

1. Limiting amplifier block

The limiting amplifier block is equipped with the auto-offset canceller circuit. When external capacitors C1 and
C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and
IC internal resistor R1 determine the low input cut-off frequency f2, as shown in Fig. 2. Similarly, external
capacitor C2 and internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since
peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on
the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The
typical values of R1,R2, C1 and C2 are as indicated below. When a single-ended input is used, provide AC
grounding by connecting Pin 10 to a capacitor which has the same capacitance as capacitor C1. RD is the
resistor for impedance matching. The same level of output impedance as for the signal source should be
applied to Pin 10.

R1 (internal) : 1kΩ R2 (internal) : 7.5kΩ

f2: 160kHz f1: 450Hz

C1 (external) : 1000pF C2 (external) : 0.047µF

C1

C1

C2

10

15

16

8

To IC interior

R1 R1

R2

R2

D

RD

Fig. 1

Feedback frequency
responce

Amplifier frequency
responce

Gain

f1 f2

Frequency

Fig. 2

– 10 –

CXB1567Q

2. Alarm block

As shown in Fig. 3, the alarm block requires external resistor REX1 for alarm level setting and peak hold
capacitor C3. When the resistance value provided for resistor REX1 is increased, the alarm setting level rises.
When the resistance value provided for REX2 is increased, the alarm setting level lowers. However, the voltage
of Pin 43 should always be higher than that of Pin 44. Normally, short-circuit Pin 44 to VEE (REX2 = 0). See
Fig. 5 for the alarm setting level. In the relationship between the alarm setting level and hysteresis width, the
hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4.
External capacitors C3 are used for input signal and alarm level peak hold capacitance. The C3 capacitance
value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The
deassert time becomes smaller by connecting resistor R10 between VEE and Pin 5 and resistor R11 between
VEE and Pin 6. The REX1 and C3 typical values are indicated below. (A capacitance of approximately 10pF is
built in Pins 5 and 6 respectively.)

REX1: 273Ω (VDAS = 3mVpp)
C3: 2000pF

VCCA

R7, R8, and R9 values
are typical values.

IC interior
IC exterior

SD output

High
level

VDAS → deassert level
VAS → assert level

43

VEE

R7

100 R8R8

REX1

1k

44

VEE

100

5k5k R9R9

R

EX2

From
Limiting
amplifier

Fig. 3

24

20

16

Peak hold

Peak hold

VccA

R10

EE

V

10p

6

Vcc

C3

5

Vcc

10p

C3

VccA

EE

V

SD
SD

R11

VAS

Low
level

V

DAS VAS

0

20 log ( ) = 6.0 dB

Hysteresis width

AS

V

VDAS

Fig. 4

Input amplitude

(mVpp)

12

DAS

, V

AS

V

8

4

0

0 200 400 600 800 1000 1200

EX1 (Ω)

R

Fig. 5

– 11 –

VDAS

Example of Representative Characteristics

Bit error rate vs. Data input level for each data rate

–6

10

–7

10

–8

10

–9

Bit error rate

10

–10

10

CXB1567Q

VEE = –5.0V,
Ta = 27°C,

pattern : PRBS223–1

1062.5Mbps

622.08Mbps

265.5Mbps

–11

10

2345

50

40

30

20

Output RMS jitter [ps]

10

Data input level [mVp-p]

Output RMS jitter vs. Data input level

VEE = –5.0V
Ta = 27°C
D = 622.08Mbps
pattern : PRBS223–1

0

1

100010010

Data input level [mVp-p]

– 12 –

CXB1567Q

VEE = –5.0V
Ta = 27°C
D = 265.5Mbps

pattern = PRBS223–1

Y Axis = 300mV/div
X Axis = 1300ps/div

32.6040ns 39.1040ns26.1040ns

Q

Q

DIN = 2.0Vp-p

V

Q

DIN = 500mVpp

V

Q

32.6040ns 39.1040ns26.1040ns

Q

DIN = 2.5mVpp

V

32.6040ns 39.1040ns26.1040ns

Q

– 13 –

CXB1567Q

VEE = –5.0V
Ta = 27°C
D = 622.08Mbps

pattern = PRBS223–1

Y Axis = 300mV/div
X Axis = 500ps/div

26.2300ns 28.7300ns23.7300ns

Q

Q

DIN = 2.0Vp-p

V

Q

DIN = 500mVpp

V

Q

26.1600ns 28.6600ns23.6600ns

Q

DIN = 3.0mVpp

V

26.2500ns 28.7500ns23.7500ns

Q

– 14 –

CXB1567Q

VEE = –5.0V
Ta = 27°C
D = 1062.5Mbps

pattern = PRBS223–1

Y Axis = 300mV/div
X Axis = 300ps/div

27.9900ns 29.4900ns26.4900ns

Q

Q

DIN = 2.0Vp-p

V

Q

DIN = 500mVpp

V

Q

27.9900ns 29.4900ns26.4900ns

Q

DIN = 10mVpp

V

17.8740ns 19.3740ns16.3740ns

– 15 –

Q

Package Outline Unit: mm

CXB1567Q

48PIN QFP (PLASTIC)

15.3 ± 0.4

+ 0.4

12.0 – 0.1

2536

37

48

112

0.8 0.3 – 0.1

+ 0.15

24

13

± 0.12

M

+ 0.35

2.2 – 0.15

+ 0.1

0.15 – 0.05

0.15

+ 0.2

0.1 – 0.1

13.5

0.9 ± 0.2

SONY CODE
EIAJ CODE
JEDEC CODE

QFP-48P-L04
∗QFP048-P-1212-B

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN
SOLDER / PALLADIUM

PLATING
COPPER / 42 ALLOY

0.7g

– 16 –