Texas Instruments Dual-Single Socket CardBus and UntraMedia Controller PCI7411 User Manual

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PCI7621/PCI7611/PCI7421/PCI7411

Dual/Single Socket CardBus and UltraMedia Controller

With Integrated 1394a"2000 OHCI Two"Port

PHY/Link"Layer Controller With Dedicated Flash Media

Socket

Data Manual

June 2004

Connectivity Solutions

SCPS081

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Contents

Section

Title

Page

1 Introduction . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−1

1.1 Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1

1.1.1 PCI7621 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1

1.1.2 PCI7421 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2

1.1.3 PCI7611 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2

1.1.4 PCI7411 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3

1.1.5 Multifunctional Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3

1.1.6 PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 1−3

1.1.7 Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4

1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5

1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6

1.5 Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7

1.6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7

2

Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1

 

2.1

Detailed Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13

3

Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1

3.1 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 3.2 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 3.3 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 3.4 Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3−2 3.4.1 1394 PCI Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2

3.4.2 Device Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 3.4.3 Serial EEPROM I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3

3.4.4 Functions 0 and 1 (CardBus) Subsystem Identification . . . 3−4 3.4.5 Function 2 (OHCI 1394) Subsystem Identification . . . . . . . 3−5 3.4.6 Function 3 (Flash Media) Subsystem Identification . . . . . . 3−5 3.4.7 Function 4 (SD Host) Subsystem Identification . . . . . . . . . . 3−5 3.4.8 Function 5 (Smart Card) Subsystem Identification . . . . . . . 3−5

3.5 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 3.5.1 PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3−6 3.5.2 Low Voltage CardBus Card Detection . . . . . . . . . . . . . . . . . 3−6 3.5.3 UltraMedia Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 3.5.4 Flash Media Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7 3.5.5 Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 3.5.6 Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 3.5.7 Integrated Pullup Resistors for PC Card Interface . . . . . . . 3−9

iii

Section

 

Title

Page

 

3.5.8

SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . .

3−9

 

3.5.9

LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . .

3−9

 

3.5.10

CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10

 

3.5.11

48-MHzClock Requirements . . . . . . . . . . . . . . . . . . . . . . . . .

3−10

3.6

Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11

 

3.6.1

Serial-BusInterface Implementation . . . . . . . . . . . . . . . . . . .

3−11

 

3.6.2

Accessing Serial-BusDevices Through Software . . . . . . .

3−11

 

3.6.3

Serial-BusInterface Protocol . . . . . . . . . . . . . . . . . . . . . . . . .

3−11

 

3.6.4

Serial-BusEEPROM Application . . . . . . . . . . . . . . . . . . . . . .

3−13

3.7

Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16

3.7.1PC Card Functional and Card Status Change Interrupts . 3−17

3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3−20 3.7.6 SMI Support in the PCI7x21/PCI7x11 Controller . . . . . . . . 3−20

3.8 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20 3.8.1 1394 Power Management (Function 2) . . . . . . . . . . . . . . . . 3−21 3.8.2 Integrated Low-DropoutVoltage Regulator(LDO-VR) . . . .3−22 3.8.3 CardBus (Functions 0 and 1) Clock Run Protocol . . . . . . . 3−22 3.8.4 CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3−22 3.8.516-BitPC Card Power Management . . . . . . . . . . . . . . . . . . . 3−23 3.8.6 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−23 3.8.7 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3−23 3.8.8 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−24 3.8.9 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−25

3.8.9.1CardBus Power Management

(Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . . 3−25

3.8.9.2OHCI 1394 (Function 2)

Power Management . . . . . . . . . . . . . . . . . . . . . . 3−26

3.8.9.3Flash Media (Function 3)

Power Management . . . . . . . . . . . . . . . . . . . . . . 3−26

3.8.9.4SD Host (Function 4)

Power Management . . . . . . . . . . . . . . . . . . . . . . 3−26

 

3.8.9.5

Smart Card (Function 5)

 

 

 

Power Management . . . . . . . . . . . . . . . . . . . . . .

3−26

3.8.10

CardBus Bridge Power Management . . . . . . . . . . . . . . . . . .

3−26

3.8.11

ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−27

3.8.12Master List of PME Context Bits and Global Reset-Only

Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−27

3.9 IEEE 1394 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−30

3.9.1 PHY Port Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . 3−30

3.9.2 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−31

3.9.3 Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−32

iv

Section

Title

Page

4 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1

4.1 PCI Configuration Register Map (Functions 0 and 1) . . . . . . . . . . . . . 4−1 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 4.3 Device ID Register Functions 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.7 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.8 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.9 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7 4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7 4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7 4.12 CardBus Socket Registers/ExCA Base Address Register . . . . . . . . . 4−8 4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8 4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 4.19 CardBus Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 4.20 CardBus Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12 4.21 CardBus I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12 4.22 CardBus I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13 4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13 4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14 4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15 4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−16 4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−17 4.28 PC Card 16-BitI/FLegacy-ModeBase-AddressRegister . . . . . . . . . 4−17 4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−18 4.30 MC_CD Debounce Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−20 4.31 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−21 4.32General-PurposeEvent Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4−23 4.33General-PurposeEvent Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4−24 4.34General-PurposeInput Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−24 4.35General-PurposeOutput Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−25 4.36 Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4−26 4.37 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−27 4.38 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−28 4.39 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−29 4.40 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−30 4.41 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−31

v

Section

Title

Page

4.42

Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−31

4.43

Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . .

4−32

4.44

Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . .

4−33

4.45Power Management Control/Status Bridge Support Extensions

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−34 4.46 Power-ManagementData Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−34 4.47 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−35 4.48 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−35 4.49 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−36 4.50 Serial Bus Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−37

5 ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . 5−1

5.1 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5−5 5.2 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6 5.3 ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7 5.4 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5−8 5.5 ExCA Card Status-ChangeRegister . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−9 5.6 ExCA CardStatus-ChangeInterrupt Configuration Register . . . . . . . 5−10 5.7 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5−11 5.8 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12

5.9ExCA I/O Windows 0 and 1 Start-AddressLow-ByteRegisters . . . . 5−13

5.10 ExCA I/O Windows 0 and 1 Start-AddressHigh-ByteRegisters . . . . 5−13

5.11ExCA I/O Windows 0 and 1 End-AddressLow-ByteRegisters . . . . . 5−14

5.12ExCA I/O Windows 0 and 1 End-AddressHigh-ByteRegisters . . . . 5−14

5.13 ExCA Memory Windows 0−4 Start-AddressLow-ByteRegisters . . . 5−15

5.14ExCA Memory Windows 0−4 Start-AddressHigh-ByteRegisters . . . 5−16

5.15ExCA Memory Windows 0−4 End-AddressLow-ByteRegisters . . . . 5−17

5.16 ExCA Memory Windows 0−4 End-AddressHigh-ByteRegisters . . . 5−18

5.17ExCA Memory Windows 0−4 Offset-AddressLow-ByteRegisters . . 5−19

5.18

ExCA Memory Windows 0−4 Offset-AddressHigh-ByteRegisters

. 5−20

5.19

ExCA Card Detect and General Control Register . . . . . . . . . . . . . . .

. 5−21

5.20

ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 5−22

5.21ExCA I/O Windows 0 and 1 Offset-AddressLow-ByteRegisters . . . 5−23

5.22

ExCA I/O Windows 0 and 1 Offset-AddressHigh-ByteRegisters . . .

5−23

5.23

ExCA Memory Windows 0−4 Page Registers . . . . . . . . . . . . . . . . . . .

5−24

6 CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . .

6−1

6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−8

vi

Section

Title

Page

7 OHCI Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1

7.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2 7.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2 7.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3 7.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4 7.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 7−5 7.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 7−5 7.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−6 7.8 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−6 7.9 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−7 7.10 CardBus CIS Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−8 7.11 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−8 7.12 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−9 7.13 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 7−9 7.14 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−10 7.15 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−10 7.16 Minimum Grant and Maximum Latency Register . . . . . . . . . . . . . . . . . 7−11 7.17 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−11 7.18 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . 7−12 7.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 7−13 7.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . 7−14 7.21 Power Management Extension Registers . . . . . . . . . . . . . . . . . . . . . . . 7−14 7.22 PCI PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−15 7.23 PCI Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . 7−16 7.24 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−17 7.25 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−18 7.26 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−19

8 OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1

8.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−4 8.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−5 8.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 8−6 8.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−6 8.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−7 8.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−7 8.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−8 8.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−8 8.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−9 8.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−10 8.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−10 8.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8−11 8.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−11 8.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−12

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Title

Page

8.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−12 8.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−13 8.17 Self-IDBuffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−14 8.18Self-IDCount Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−15 8.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 8−16 8.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 8−17 8.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−18 8.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−20 8.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 8−22 8.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 8−23 8.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 8−24 8.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 8−25 8.27 Initial Bandwidth Available Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−25 8.28 Initial Channels Available High Register . . . . . . . . . . . . . . . . . . . . . . . . 8−26 8.29 Initial Channels Available Low Register . . . . . . . . . . . . . . . . . . . . . . . . . 8−26 8.30 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−27 8.31 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−28 8.32 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−29 8.33 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−30 8.34 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−31 8.35 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 8−32 8.36 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 8−34 8.37 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8−35 8.38 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8−37 8.39 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 8−37 8.40 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 8−38 8.41 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . 8−39 8.42 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 8−40 8.43 Isochronous Transmit Context Command Pointer Register . . . . . . . . 8−41 8.44 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 8−41 8.45 Isochronous Receive Context Command Pointer Register . . . . . . . . 8−43 8.46 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . 8−44

9 TI Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1

9.1

DV and MPEG2 Timestamp Enhancements . . . . . . . . . . . . . . . . . . . . .

9−1

9.2

Isochronous Receive Digital Video Enhancements . . . . . . . . . . . . . . .

9−2

9.3

Isochronous Receive Digital Video Enhancements Register . . . . . . .

9−2

9.4

Link Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−4

9.5

Timestamp Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−5

10 PHY Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−1

10.1 Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−1 10.2 Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−4 10.3 Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−5

viii

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Title

Page

10.4

Vendor-DependentRegister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−6

10.5

Power-ClassProgramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−7

11 Flash Media Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . .

11−1

11.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−2 11.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−2 11.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−3 11.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−4 11.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 11−5 11.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 11−5 11.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−6 11.8 Flash Media Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−6 11.9 Subsystem Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . 11−7 11.10 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−7 11.11 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−7 11.12 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−8 11.13 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−8 11.14 Minimum Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−9 11.15 Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−9 11.16 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . 11−10 11.17 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . 11−11 11.18 Power Management Control and Status Register . . . . . . . . . . . . . . 11−12 11.19 Power Management Bridge Support Extension Register . . . . . . . . 11−12 11.20 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 11−13 11.21 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−13 11.22 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−14 11.23 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−15

12 SD Host Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−1

12.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−2 12.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−2 12.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−3 12.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−4 12.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 12−5 12.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 12−6 12.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−6 12.8 SD Host Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−7 12.9 Subsystem Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . 12−7 12.10 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−8 12.11 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−8 12.12 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−8 12.13 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−9 12.14 Minimum Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−9 12.15 Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−10

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12.16 Slot Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−10 12.17 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . 12−11 12.18 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . 12−12 12.19 Power Management Control and Status Register . . . . . . . . . . . . . . 12−13 12.20 Power Management Bridge Support Extension Register . . . . . . . . 12−13 12.21 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 12−14 12.22 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−14 12.23 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−15 12.24 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−15 12.25 Slot 0 3.3-VMaximum Current Register . . . . . . . . . . . . . . . . . . . . . . 12−16 12.26 Slot 13.3-VMaximum Current Register . . . . . . . . . . . . . . . . . . . . . . 12−16 12.27 Slot 23.3-VMaximum Current Register . . . . . . . . . . . . . . . . . . . . . . 12−16 12.28 Slot 33.3-VMaximum Current Register . . . . . . . . . . . . . . . . . . . . . . 12−17 12.29 Slot 43.3-VMaximum Current Register . . . . . . . . . . . . . . . . . . . . . . 12−17 12.30 Slot 53.3-VMaximum Current Register . . . . . . . . . . . . . . . . . . . . . . 12−17

13 Smart Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 13−1

13.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−2 13.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−2 13.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−3 13.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−4 13.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 13−5 13.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 13−5 13.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−6 13.8 Smart Card Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 13−6 13.9 Smart Card Base Address Register 1−4 . . . . . . . . . . . . . . . . . . . . . . . . 13−7 13.10 Subsystem Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . 13−7 13.11 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−8 13.12 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−8 13.13 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−8 13.14 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−9 13.15 Minimum Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−9 13.16 Maximum Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−10 13.17 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . 13−10 13.18 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . 13−11 13.19 Power Management Control and Status Register . . . . . . . . . . . . . . 13−12 13.20 Power Management Bridge Support Extension Register . . . . . . . . 13−12 13.21 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 13−13 13.22 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−13 13.23 Subsystem ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−14 13.24 Class Code Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13−14 13.25 Smart Card Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . 13−15 13.26 Smart Card Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . 13−17

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