54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCAS451 ± FEBRUARY 1987 ± REVISED APRIL 1993
•Inputs Are TTL-Voltage Compatible
•Flow-Through Architecture Optimizes PCB Layout
•Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
•EPIC (Enhanced-Performance Implanted CMOS) 1- m Process
•500-mA Typical Latch-Up Immunity at 125°C
•Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
description
54ACT11109 . . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE (TOP VIEW)
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1CLK |
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1PRE |
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1 |
16 |
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1Q |
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2 |
15 |
1K |
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1J |
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1Q |
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3 |
14 |
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GND |
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4 |
13 |
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1CLR |
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VCC |
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2Q |
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5 |
12 |
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2Q |
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6 |
11 |
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2CLR |
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2J |
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2PRE |
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7 |
10 |
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2CLK |
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8 |
9 |
2K |
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54ACT11109 . . . FK PACKAGE
(TOP VIEW)
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (1PRE or 2PRE) or clear (1CLR or 2CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at
www.DataSheet4U.com a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time
interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
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1J |
1CLR |
NC |
V |
2CLR |
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CC |
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1K |
3 |
2 |
1 |
20 19 |
2J |
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4 |
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18 |
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1CLK |
5 |
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17 |
2K |
NC |
6 |
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16 |
NC |
1PRE |
7 |
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15 |
2CLK |
1Q |
8 |
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14 |
2PRE |
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9 |
10 11 12 13 |
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1Q |
GND |
NC |
2Q |
2Q |
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NC ± No internal connection |
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The 54ACT11109 is characterized for operation over the full military temperature range of ±55°C to 125°C. The 74ACT11109 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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CLK |
J |
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Q |
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PRE |
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CLR |
K |
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Q |
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L |
H |
X |
X |
X |
H |
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L |
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H |
L |
X |
X |
X |
L |
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H |
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L |
L |
X |
X |
X |
H² |
H² |
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H |
H |
↑ |
L |
L |
L |
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H |
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H |
H |
↑ |
H |
L |
Toggle |
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H |
H |
↑ |
L |
H |
Q0 |
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Q |
0 |
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H |
H |
↑ |
H |
H |
H |
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L |
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H |
H |
L |
X |
X |
Q0 |
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Q |
0 |
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²This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to the inactive (high) level.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
2±1 |
54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCAS451 ± FEBRUARY 1987 ± REVISED APRIL 1993
logic symbol²
1 |
S |
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1PRE |
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2 |
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14 |
1J |
1Q |
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1J |
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16 |
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1CLK |
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C1 |
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15 |
1K |
3 |
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1K |
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1Q |
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13 |
R |
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1CLR |
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7 |
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2PRE |
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10 |
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6 |
2Q |
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2J |
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8 |
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2CLK |
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9 |
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5 |
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2K |
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2Q |
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11 |
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2CLR |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.5 V to 6 |
V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ± 20 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ± 50 mA |
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Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ± 50 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . ± 100 mA |
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Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . ±65°C to 150°C |
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³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
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54ACT11109 |
74ACT11109 |
UNIT |
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MIN |
MAX |
MIN |
MAX |
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VCC |
Supply voltage |
4.5 |
5.5 |
4.5 |
5.5 |
V |
VIH |
High-level input voltage |
2 |
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2 |
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V |
VIL |
Low-level input voltage |
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0.8 |
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0.8 |
V |
VI |
Input voltage |
0 |
VCC |
0 |
VCC |
V |
VO |
Output voltage |
0 |
VCC |
0 |
VCC |
V |
IOH |
High-level output current |
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± 24 |
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± 24 |
mA |
IOL |
Low-level output current |
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24 |
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24 |
mA |
t / v |
Input transition rise or fall rate |
0 |
10 |
0 |
10 |
ns/ V |
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TA |
Operating free-air temperature |
± 55 |
125 |
± 40 |
85 |
°C |
2±2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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