Siemens SAB-C517A-4R24M, SAB-C517A-4RM, SAB-C517A-L24M, SAB-C517A-LM, SAF-C517A-4R24M Datasheet

Microcomputer Components

8-Bit CMOS Microcontroller

C517A

Data Sheet 10.97

C517A Data Sheet
Revision History:		Current Version: 10.97
Previous Version:		none
Page	Page	Subjects (major changes since last revision)
(in previous	(in current
Version)	Version)

Edition 10.97

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

© Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

8-Bit CMOS Microcontroller

C517A

Advance Information

•Full upward compatibility with SAB 80C517A/83C517A-5

•Up to 24 MHz external operating frequency

–500 ns instruction cycle at 24 MHz operation

•Superset of the 8051 architecture with 8 datapointers

•On-chip emulation support logic (Enhanced Hooks Technology TM)

•32K byte on-chip ROM (with optional ROM protection)

–alternatively up to 64K byte external program memory

•Up to 64K byte external data memory

•256 byte on-chip RAM

•Additional 2K byte on-chip RAM (XRAM)

•Seven 8-bit parallel I/O ports

•Two input ports for analog/digital input

(further features are on next page)

On-Chip Emulation Support Module

Oscillator

Watchdog

XRAM

RAM

Port 0

I/O

Watchdog

Timer

2K x 8

256 x 8

Compare

T0

CPU

Port 1

I/O

CCU

T2

MDU

Power

Timer

(8 Datapointer)

Port 2

Saving

T1

I/O

Modes

10-Bit

ROM

Port 3

I/O

A/D Converter

32k x 8

8 Bit

8 Bit

Port 8

Port 7

Port 6

Port 5

Port 4

I/O

USART

UART

Analog/	Analog/	I/O	I/O
Digital	Digital
Input	Input		MCA03317

Figure 1

C517A Functional Units

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C517A

Features (cont’d):

•Two full duplex serial interfaces (USART)

–4 operating modes, fixed or variable baud rates

–programmable baud rate generators

•Four 16-bit timer/counters

–Timer 0 / 1 (C501 compatible)

–Timer 2 for 16-bit reload, compare, or capture functions

–Compare timer for compare/capture functions

•Powerful 16-bit compare/capture unit (CCU) with up to 21 high-speed or PWM output channels and 5 capture inputs

•10-bit A/D converter

–12 multiplexed analog inputs

–Built-in self calibration

•Extended watchdog facilities

–15-bit programmable watchdog timer

–Oscillator watchdog

•Power saving modes

–Slow down mode

–Idle mode (can be combined with slow down mode)

–Software power-down mode

–Hardware power-down mode

•17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels

•P-MQFP-100 packages

• Temperature Ranges: SAB-C517A TA = 0 to 70 °C SAF-C517A TA = -40 to 85 °C SAH-C517A TA = -40 to 110 °C

Table 1

Ordering Information

Type	Ordering Code	Package	Description
			(8-Bit CMOS microcontroller)
SAB-C517A-4RM	Q67120-DXXXX	P-MQFP-100-2	with mask programmable ROM
			(18 MHz)
SAF-C517A-4RM	Q67120-DXXXX	P-MQFP-100-2	with mask programmable ROM
			(18 MHz) ext. temp. – 40 °C to 85 °C
SAB-C517A-4R24M	Q67120-DXXXX	P-MQFP-100-2	with mask programmable ROM
			(24 MHz)
SAF-C517A-4R24M	Q67120-DXXXX	P-MQFP-100-2	with mask programmable ROM
			(24 MHz) ext. temp. – 40 °C to 85 °C
SAB-C517A-LM	Q67127-C1071	P-MQFP-100-2	for external memory (18 MHz)
SAF-C517A-LM	Q67127-C1063	P-MQFP-100-2	for external memory (18 MHz)
			ext. temp. – 40 °C to 85 °C
SAB-C517A-L24M	Q67127-C1072	P-MQFP-100-2	for external memory (24 MHz)

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C517A

Note: Versions for extended temperature ranges – 40 °C to 110 °C (SAH-C517A) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.

VCC

VSS

Port 7

8-bit Analog/

Digital Input

Port 0

Port 8

8-Bit Digital I/O

4-bit Analog/

Port 1

Digital Input

XTAL1

8-Bit Digital I/O

XTAL2

Port 2

ALE

8-Bit Digital I/O

Port 3

PSEN

C517A

8-Bit Digital I/O

EA

RESET

Port 4

PE/SWD

8-Bit Digital I/O

OWE

Port 5

RO

8-Bit Digital I/O

HWPD

Port 6

VAREF

8-Bit Digital I/O

VAGND

MCL03318

Figure 2

Logic Symbol

Additional Literature

For further information about the C517A the following literature is available:

Title		Ordering Number
C517A 8-Bit CMOS Microcontroller User’s Manual		B158-H7053-X-X-7600
C500	Microcontroller Family	B158-H6987-X-X-7600
Architecture and Instruction Set User’s Manual
C500	Microcontroller Family - Pocket Guide	B158-H6986-X-X-7600

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																						C517A
		P1.5/T2EX	P1.6/CLKOUT	P1.7/T2	P3.7/RD	P3.6/WR	P3.5/T1	P3.4/T0	P3.3/INT1	P3.2/INT0	P3.1/TxD0	P3.0/RxD0	N.C.	N.C.	P7.0/AIN0	P7.1/AIN1	P7.2/AIN2	P7.3/AIN3	P7.4/AIN4	P7.5/AIN5	P7.6/AIN6
CC4/INT2/P1.4	1	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	P7.7/AIN7
																					80
N.C.	2																				79	VAGND
N.C.	3																				78	VAREF
N.C.	4																				77	N.C.
N.C.	5																				76	N.C.
CC3/INT6/P1.3	6																				75	N.C.
CC2/INT5/P1.2	7																				74	N.C.
CC1/INT4/P1.1	8																				73	RESET
CC0/INT3/P1.0	9																				72	P4.7/CM7
VSS	10																				71	P4.6/CM6
VCC	11																				70	P4.5/CM5
XTAL2	12																				69	P4.4/CM4
XTAL1	13																				68	P4.3/CM3
P2.0/A8	14																				67	PE/SWD
P2.1/A9	15										C517A										66	P4.2/CM2
P2.2/A10	16																				65	P4.1/CM1
P2.3/A11	17																				64	P4.0/CM0
P2.4/A12	18																				63	VCC
P2.5/A13	19																				62	VSS
P2.6/A14	20																				61	RO
P2.7/A15	21																				60	P8.3/AIN11
PSEN	22																				59	P8.2/AIN10
ALE	23																				58	P8.1/AIN9
EA	24																				57	P8.0/AIN8
N.C.	25																				56	P6.7
P0.0/AD0	26																				55	P6.6
P0.1/AD1	27																				54	P6.5
N.C.	28																				53	N.C.
N.C.	29																				52	N.C.
P0.2/AD2	30																				51	N.C.
		31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
		P0.3/AD3	P0.4/AD4	P0.5/AD5	P0.6/AD6	P0.7/AD7	HWPD	CCM7/P5.7	CCM6/P5.6	CCM5/P5.5	CCM4/P5.4	CCM3/P5.3	CCM2/P5.2	CCM1/P5.1	CCM0/P5.0	OWE	ADST/P6.0	RxD1/P6.1	TxD1/P6.2	P6.3	P6.4	MCP03319

Figure 3

Pin Configuration P-MQFP-100 Package (Top View)

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Table 2

Pin Definitions and Functions

Symbol	Pin Number	I/O*)	Function
	P-MQFP-100
P1.0 - P1.7	9 - 6, 1,	I/O	Port 1
	100 - 98		is an 8-bit quasi-bidirectional I/O port with internal pullup
			resistors. Port 1 pins that have 1's written to them are
			pulled high by the internal pullup resistors, and in that state
			can be used as inputs. As inputs, port 1 pins being
			externally pulled low will source current (I IL, in the DC
			characteristics) because of the internal pullup resistors.
			The port is used for the low-order address byte during
			program verification. Port 1 also contains the interrupt,
			timer, clock, capture and compare pins that are used by
			various options. The output latch corresponding to a
			secondary function must be programmed to a one (1) for
			that function to operate (except when used for the compare
			functions). The secondary functions are assigned to the
			port 1 pins as follows:
	9		P1.0				CC0	Interrupt 3 input / compare 0 output /
				INT3
								capture 0 input
	8		P1.1	INT4			CC1	Interrupt 4 input / compare 1 output /
								capture 1 input
	7		P1.2	INT5			CC2	Interrupt 5 input / compare 2 output /
								capture 2 input
	6		P1.3	INT6			CC3	Interrupt 6 input / compare 3 output /
								capture 3 input
	1		P1.4					Interrupt 2 input
				INT2
	100		P1.5	T2EX				Timer 2 external reload / trigger input
	99		P1.6	CLKOUT				System clock output
	98		P1.7	T2				Counter 2 input
VSS	10, 62	–	Ground (0V)
			during normal, idle, and power down operation.
VCC	11, 63	–	Supply voltage
			during normal, idle, and power down mode.
*) I = Input
O = Output

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C517A

Table 2
Pin Definitions and Functions				(cont’d)
Symbol		Pin Number		I/O*)	Function
		P-MQFP-100
XTAL2		12		–	XTAL2
					is the input to the inverting oscillator amplifier and input to
					the internal clock generator circuits.
					To drive the device from an external clock source, XTAL2
					should be driven, while XTAL1 is left unconnected.
					Minimum and maximum high and low times as well as rise/
					fall times specified in the AC characteristics must be
					observed.
XTAL1		13		–	XTAL1
					is the output of the inverting oscillator amplifier. This pin is
					used for the oscillator operation with crystal or ceramic
					resonator.
P2.0 - P2.7		14 - 21		I/O	Port 2
					is an 8-bit quasi-bidirectional I/O port with internal pullup
					resistors. Port 2 pins that have 1's written to them are
					pulled high by the internal pullup resistors, and in that state
					can be used as inputs. As inputs, port 2 pins being
					externally pulled low will source current (I IL, in the DC
					characteristics) because of the internal pullup resistors.
					Port 2 emits the high-order address byte during fetches
					from external program memory and during accesses to
					external data memory that use 16-bit addresses
					(MOVX @DPTR). In this application it uses strong internal
					pullup resistors when issuing 1's. During accesses to
					external data memory that use 8-bit addresses
					(MOVX @Ri), port 2 issues the contents of the P2 special
					function register.
		22		O	The
PSEN						Program Store Enable
					output is a control signal that enables the external program
					memory to the bus during external fetch operations. It is
					activated every six oscillator periods except during
					external data memory accesses. The signal remains high
					during internal program execution.
ALE		23		O	The Address Latch enable
					output is used for latching the address into external
					memory during normal operation. It is activated every six
					oscillator periods except during an external data memory
					access.
*) I = Input
O = Output

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C517A

Table 2
Pin Definitions and Functions					(cont’d)
Symbol			Pin Number		I/O*)	Function
			P-MQFP-100
			24		I
EA							External Access Enable
							When held high, the C517A executes instructions from the
							internal ROM as long as the PC is less than 8000H. When
							held low, the C517A fetches all instructions from external
							program memory. For the C517A-L this pin must be tied
							low.
P0.0 - P0.7			26, 27,		I/O		Port 0
			30 - 35				is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
							have 1's written to them float, and in that state can be used
							as high-impedance inputs. Port 0 is also the multiplexed
							low-order address and data bus during accesses to
							external program and data memory. In this application it
							uses strong internal pullup resistors when issuing 1's. Port
							0 also outputs the code bytes during program verification
							in the C517A. External pullup resistors are required during
							program verification.
			36		I
HWPD							Hardware Power Down
							A low level on this pin for the duration of one machine cycle
							while the oscillator is running resets the C517A. A low level
							for a longer period will force the part into hardware power
							down mode with the pins floating. There is no internal
							pullup resistor connected to this pin.
P5.0 - P5.7			44 - 37		I/O		Port 5
							is a quasi-bidirectional I/O port with internal pull-up
							resistors. Port 5 pins that have 1 s written to them are
							pulled high by the internal pull-up resistors, and in that
							state can be used as inputs. As inputs, port 5 pins being
							externally pulled low will source current (IIL, in the DC
							characteristics) because of the internal pull-up resistors.
							This port also serves the alternate function “Concurrent
							Compare” and “Set/Reset Compare”. The secondary
							functions are assigned to the port 5 pins as follows:
							CCM0 to CCM7 P5.0 to P5.7:
							concurrent compare or Set/Reset lines
*) I = Input
	O = Output

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Table 2

Pin Definitions and Functions

(cont’d)

Symbol

Pin Number

I/O*)

Function

P-MQFP-100

OWE

45

I

Oscillator Watchdog Enable

A high level on this pin enables the oscillator watchdog.

When left unconnected this pin is pulled high by a weak

internal pull-up resistor. The logic level at OWE should not

be changed during normal operation. When held at low

level the oscillator watchdog function is turned off. During

hardware power down the pullup resistor is switched off.

P6.0 - P6.7

46 - 50,

I/O

Port 6

54 - 56

is a quasi-bidirectional I/O port with internal pull-up

resistors. Port 6 pins that have 1 s written to them are

pulled high by the internal pull-up resistors, and in that

state can be used as inputs. As inputs, port 6 pins being

externally pulled low will source current (I IL, in the

DC characteristics) because of the internal pull-up

resistors.

Port 6 also contains the external A/D converter control pin

and the transmit and receive pins for the serial interface 1.

The output latch corresponding to a secondary function

must be programmed to a one (1) for that function to

operate.

The secondary functions are assigned to the pins of port 6,

as follows:

46

P6.0

external A/D converter start pin

ADST

47

P6.1

RxD1

receiver data input of serial interface 1

48

P6.2

TxD1

transmitter data input of serial interface 1

P8.0 - P8.3

57 - 60

I

Port 8

is a 4-bit unidirectional input port. Port pins can be used for

digital input, if voltage levels meet the specified input high/

low voltages, and for the higher 4-bit of the multiplexed

analog inputs of the A/D converter, simultaneously.

P8.0 - P8.3

AIN8 - AIN11 analog input 8 - 14

61

O

RO

Reset Output

This pin outputs the internally synchronized reset request

signal. This signal may be generated by an external

hardware reset, a watchdog timer reset or an oscillator

watchdog reset. The

is active low.

RO

*) I = Input

O = Output

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Table 2
Pin Definitions and Functions					(cont’d)
Symbol			Pin Number		I/O*)	Function
			P-MQFP-100
P4.0 - P4.7			64 - 66,		I/O		Port 4
			68 - 72				is an 8-bit quasi-bidirectional I/O port with internal pull-up
							resistors. Port 4 pins that have 1’s written to them are
							pulled high by the internal pull-up resistors, and in that
							state can be used as inputs. As inputs, port 4 pins being
							externally pulled low will source current (I IL, in the DC
							characteristics) because of the internal pull-up resistors.
			67		I				/ Start watchdog timer
PE/SWD							Power saving mode enable
							A low level at this pin allows the software to enter the power
							saving modes (idle mode, slow down mode, and power
							down mode). In case the low level is also seen during
							reset, the watchdog timer function is off on default.
							Usage of the software controlled power saving modes is
							blocked, when this pin is held at high level. A high level
							during reset performs an automatic start of the watchdog
							timer immediately after reset.
							When left unconnected this pin is pulled high by a weak
							internal pull-up resistor. During hardware power down the
							pullup resistor is switched off.
			73		I
RESET							RESET
							A low level on this pin for the duration of two machine
							cycles while the oscillator is running resets the C517A. A
							small internal pullup resistor permits power-on reset using
							only a capacitor connected to VSS .
VAREF			78		–		Reference voltage for the A/D converter
VAGND			79		–		Reference ground for the A/D converter
P7.0 - P7.7			87 - 80				Port 7
							is an 8-bit unidirectional input port. Port pins can be used
							for digital input, if voltage levels meet the specified input
							high/low voltages, and for the lower 8-bit of the multiplexed
							analog inputs of the A/D converter, simultaneously.
							P7.0 - P7.7 AIN0 - AIN7			analog input 8 - 14

*) I = Input O = Output

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Table 2

Pin Definitions and Functions

(cont’d)

Symbol

Pin Number

I/O*)

Function

P-MQFP-100

P3.0 - P3.7

90

- 97

I/O

Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup

resistors. Port 3 pins that have 1's written to them are

pulled high by the internal pullup resistors, and in that state

can be used as inputs. As inputs, port 3 pins being

externally pulled low will source current (I IL, in the DC

characteristics) because of the internal pullup resistors.

Port 3 also contains the interrupt, timer, serial port and

external memory strobe pins that are used by various

options. The output latch corresponding to a secondary

function must be programmed to a one (1) for that function

to operate. The secondary functions are assigned to the

pins of port 3, as follows:

90

P3.0

RxD0

Receiver data input (asynch.) or data

input/output (synch.)of serial interface 0

91

P3.1

TxD0

Transmitter data output (asynch.) or

clock output (synch.) of serial interface 0

92

P3.2

External interrupt 0 input /

INT0

timer 0 gate control input

93

P3.3

External interrupt 1 input /

INT1

timer 1 gate control input

94

P3.4

T0

Timer 0 counter input

95

P3.5

T1

Timer 1 counter input

96

P3.6

control output; latches the data byte

WR

WR

from port 0 into the external data

memory

97

P3.7

control output; enables the external

RD

RD

data memory

N.C.

2 - 5, 25,

–

Not connected

28, 29, 32,

These pins of the P-MQFP-100 package need not be

43, 44,

connected.

51

- 53,

74

- 77

88, 89

*) I = Input

O = Output

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						C517A
	Oscillator Watchdog
			RAM	XRAM	ROM
XTAL1		OSC & Timing	256 x 8	2k x 8	32k x 8
XTAL2
ALE		CPU
PSEN
		8 Datapointer
EA
					Emulation
PE/SWD	Programmable				Support
					Logic
RESET	Watchdog Timer
HWPD		Timer 0			Port 0	Port 0
						8-Bit Digital I/O
RO
OWE		Timer 1			Port 1	Port 1
						8-Bit Digital I/O
		Timer 2
		Capture			Port 2	Port 2
						8-Bit Digital I/O
		Compare Unit
	Compare Timer				Port 3	Port 3
						8-Bit Digital I/O
	Serial Channel 0
	Programmable				Port 4	Port 4
	Baud Rate Generator					8-Bit Digital I/O
	Serial Channel 1				Port 5	Port 5
	Programmable					8-Bit Digital I/O
	Baud Rate Generator
		Interrupt Unit			Port 6	Port 6
						8-Bit Digital I/O
VAREF		A/D Converter				Port 7
VAGND		10 Bit			Port 7	8-Bit Analog/
						Digital Input
		Analog				Port 8
	S & H				Port 8	4-Bit Analog/
			MUX
						Digital Input
	C517A
					MCB03320

Figure 4

Block Diagram of the C517A

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C517A

CPU

The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1μs (24 MHz: 500 ns).

Special Function Register PSW (Address D0H)								Reset Value : 00H
Bit No.	MSB							LSB
	D7H	D6H	D5H	D4H	D3H	D2H	D1H	D0H
D0H	CY	AC	F0	RS1	RS0	OV	F1	P	PSW

Bit	Function
CY	Carry Flag
	Used by arithmetic instruction.
AC	Auxiliary Carry Flag
	Used by instructions which execute BCD operations.
F0	General Purpose Flag
RS1	Register Bank select control bits
RS0	These bits are used to select one of the four register banks.

		RS1	RS0	Function
		0	0	Bank 0 selected, data address 00H-07H
		0	1	Bank 1 selected, data address 08H-0FH
		1	0	Bank 2 selected, data address 10H-17H
	1		1	Bank 3 selected, data address 18H-1FH
OV	Overflow Flag
	Used by arithmetic instruction.
F1	General Purpose Flag
P	Parity Flag
	Set/cleared by hardware after each instruction to indicate an odd/even
	number of “one” bits in the accumulator, i.e. even parity.

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C517A

Memory Organization

The C517A CPU manipulates operands in the following five address spaces:

–up to 64 Kbyte of program memory (32K on-chip program memory for C517A-4R)

–up to 64 Kbyte of external data memory

–256 bytes of internal data memory

–2K bytes of internal XRAM data memory

–a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C517A.

FFFFH

int.

ext.

FFFFH

ext.

(XMAP0 = 0)

(XMAP0 = 1)

F800H

Indirect

Direct

8000 H

F7FF H

Address

Address

FFH

FFH

7FFF H

Internal

Special

Function

RAM

Regs.

80 H

80 H

int.

ext.

ext.

7F H

(EA = 1)

(EA = 0)

Internal

RAM

0000 H

0000 H

00 H

"Code Space"

"Data Space"

"Internal Data Space"

MCB03321

Figure 5

C517A Memory Map

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C517A

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting

the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

a)

b)

		&
+	RESET	RESET
	C517A	C517A

c)

+ RESET

C517A

MCS03323

Figure 6

Reset Circuitries

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Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Crystal Oscillator Mode

Driving from External Source

C

N.C.

XTAL1

XTAL1

3.5 - 24

MHz

External Oscillator

XTAL2

Signal

XTAL2

C

Crystal Mode: C = 20 pF

10 pF

(Incl. Stray Capacitance)

MCS03245

Figure 7

Recommended Oscillator Circuitries

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C517A

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

			ICE-System interface
			to emulation hardware
SYSCON		RESET	RSYSCON
		EA
PCON			RPCON		EH-IC
		ALE
TCON			RTCON
		PSEN
	C500	Port 0		Enhanced Hooks
	MCU			Interface Circuit
opt.		Port 2	RPORT RPORT
I/O Ports	Port 3	Port 1	2	0	TEA TALE	TPSEN
		Target System Interface				MCS03254

Figure 8

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

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Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area.

The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F8H, FFH) are bitaddressable. The SFRs of the C517A are listed in table 3 and table 4. In table 3 they are organized in groups which refer to the functional blocks of the C517A. Table 4 illustrates the contents of the SFRs in numeric order of their addresses.

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Table 3

Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after

Reset

CPU

ACC

Accumulator

E0H 1)

00H

B

B-Register

F0H 1)

00H

DPH

Data Pointer, High Byte

83H

00H

DPL

Data Pointer, Low Byte

82H

00H

DPSEL

Data Pointer Select Register

92

XXXX X000

B

3)

H

PSW

Program Status Word Register

D0H 1)

00H

SP

Stack Pointer

81H

07H

A/D-

ADCON0 2)

A/D Converter Control Register 0

D8

H

1)

00

H

Converter

ADCON1

A/D Converter Control Register 1

DCH

0XXX 0000B 3)

ADDATH

A/D Converter Data Register, High Byte

D9H

00H

ADDATL

A/D Converter Data Register, Low Byte

DA

H

00XX XXXX

3

B

Interrupt

IEN0 2)

Interrupt Enable Register 0

A8

H

1)

00

B8

H

System

IEN1 2)

Interrupt Enable Register 1

H

1)

00

H

IEN2

Interrupt Enable Register 2

9A

XX00 00X0

B

3)

H

IP0 2)

Interrupt Priority Register 0

A9

00

H

H

IP1

Interrupt Priority Register 1

B9

XX00 0000

3)

H

B

IRCON0 2)

Interrupt Request Control Register 0

C0

H

1)

00

H

IRCON1

Interrupt Request Control Register 1

D1H

00H

TCON 2)

Timer 0/1 Control Register

88

1)

00

H

H

T2CON 2)

Timer 2 Control Register

C8

H

1)

00

98

H

S0CON 2)

Serial Channel 0 Control Register

1)

00

H

H

CTCON 2)

Compare Timer Control Register

E1

0X00 0000

B

3)

H

MUL/DIV

ARCON

Arithmetic Control Register

EFH

0XXXXXXXB 3)

Unit

MD0

Multiplication/Division Register 0

E9H

XXH 3)

MD1

Multiplication/Division Register 1

EAH

XXH 3)

MD2

Multiplication/Division Register 2

EBH

XXH 3)

MD3

Multiplication/Division Register 3

ECH

XXH 3)

MD4

Multiplication/Division Register 4

EDH

XXH 3)

MD5

Multiplication/Division Register 5

EEH

XXH 3)

Timer 0 /

TCON 2)

Timer 0/1 Control Register

88

1)

00

H

H

Timer 1

TH0

Timer 0, High Byte

8CH

00H

TH1

Timer 1, High Byte

8DH

00H

TL0

Timer 0, Low Byte

8AH

00H

TL1

Timer 1, Low Byte

8BH

00H

TMOD

Timer Mode Register

89H

00H

1)Bit-addressable special function registers

2)This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3)‘X’ means that the value is undefined and the location is reserved

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C517A

Table 3

Special Function Registers - Functional Blocks (cont’d)

Block	Symbol	Name	Address			Contents after
						Reset
Compare/	CCEN	Compare/Capture Enable Register	C1H			00H
Capture	CC4EN	Compare/Capture 4 Enable Register	C9H			00H
Unit	CCH1	Compare/Capture Register 1, High Byte	C3H			00H
(CCU)	CCH2	Compare/Capture Register 2, High Byte	C5H			00H
Timer 2	CCH3	Compare/Capture Register 3, High Byte	C7H			00H
	CCH4	Compare/Capture Register 4, High Byte	CFH			00H
	CCL1	Compare/Capture Register 1, Low Byte	C2H			00H
	CCL2	Compare/Capture Register 2, Low Byte	C4H			00H
	CCL3	Compare/Capture Register 3, Low Byte	C6H			00H
	CCL4	Compare/Capture Register 4, Low Byte	CEH			00H
	CMEN	Compare Enable Register	F6H			00H
	CMH0	Compare Register 0, High Byte	D3H			00H
	CMH1	Compare Register 1, High Byte	D5H			00H
	CMH2	Compare Register 2, High Byte	D7H			00H
	CMH3	Compare Register 3, High Byte	E3H			00H
	CMH4	Compare Register 4, High Byte	E5H			00H
	CMH5	Compare Register 5, High Byte	E7H			00H
	CMH6	Compare Register 6, High Byte	F3H			00H
	CMH7	Compare Register 7, High Byte	F5H			00H
	CML0	Compare Register 0, Low Byte	D2H			00H
	CML1	Compare Register 1, Low Byte	D4H			00H
	CML2	Compare Register 2, Low Byte	D6H			00H
	CML3	Compare Register 3, Low Byte	E2H			00H
	CML4	Compare Register 4, Low Byte	E4H			00H
	CML5	Compare Register 5, Low Byte	E6H			00H
	CML6	Compare Register 6, Low Byte	F2H			00H
	CML7	Compare Register 7, Low Byte	F4H			00H
	CMSEL	Compare Input Select	F7H			00H
	CRCH	Comp./Rel./Capt. Register High Byte	CBH			00H
	CRCL	Comp./Rel./Capt. Register Low Byte	CAH			00H
	COMSETL	Compare Set Register Low Byte	A1H			00H
	COMSETH	Compare Set Register, High Byte	A2H			00H
	COMCLRL	Compare Clear Register, Low Byte	A3H			00H
	COMCLRH	Compare Clear Register, High Byte	A4H			00H
	SETMSK	Compare Set Mask Register	A5H			00H
	CLRMSK	Compare Clear Mask Register	A6H			00H
	CTCON 2)	Compare Timer Control Register	E1H			0X00 0000B 3)
	CTRELH	Compare Timer Rel. Register, High Byte	DFH			00H
	CTRELL	Compare Timer Rel. Register, Low Byte	DEH			00H
	TH2	Timer 2, High Byte	CDH			00H
	TL2	Timer 2, Low Byte	CCH			00H
	T2CON 2)	Timer 2 Control Register	C8	H	1)	00
	IRCON0 2)	Interrupt Request Control Register 0	C0			H
				H	1)	00
						H

1)Bit-addressable special function registers

2)This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3)‘X’ means that the value is undefined and the location is reserved

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