Siemens SAB-C515C-8RM, SAB-C515C-LM, SAF-C515C-8RM, SAF-C515C-LM Datasheet

Microcomputer Components

8-Bit CMOS Microcontroller

C515C

Data Sheet 07.97

C515C Data Sheet
Revision History :		1997-07-01
Previous Releases :		09.96
Page	Subjects (changes since last revision)
4	SSC transfer rate at 10 MHz = 2.5 MHz
19	Figure reference corrected
52, 53	Power saving modes : description of hardware power down mode added
56, 57	Icc specification has been extended
62	tSCLK for Master Mode corrected

Edition 1997-07-01

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

© Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).

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Siemens AG is an approved CECC manufacturer.

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Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

8-Bit CMOS Microcontroller

C515C

Advance Information

•Full upward compatibility with SAB 80C515A

•64k byte on-chip ROM (external program execution is possible)

•256 byte on-chip RAM

•2K byte of on-chip XRAM

•Up to 64K byte external data memory

•Superset of the 8051 architecture with 8 datapointers

•Up to 10 MHz external operating frequency (1 s instruction cycle time at 6 MHz external clock)

•On-chip emulation support logic (Enhanced Hooks Technology TM)

•Current optimized oscillator circuit and EMI optimized design

•Eight ports : 48+1 digital I/O lines, 8 analog inputs

–Quasi-bidirectional port structure (8051 compatible)

–Port 5 selectable for bidirectional port structure (CMOS voltage levels)

•Full-CAN controller on-chip

–256 register/data bytes are located in external data memory area

–max.1 MBaud at 8-10 MHz operating frequency

•Three 16-bit timer/counters

–Timer 2 can be used for compare/capture functions

(further features are on next page)

Figure 1

C515C Functional Units

Enhanced Hooks Technology TM is a trademark of Siemens AG.

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C515C

Features (continued) :

•10-bit A/D converter with multiplexed inputs and built-in self calibration

•Full duplex serial interface with programmable baudrate generator (USART)

•SSC synchronous serial interface (SPI compatible)

–Master and slave capable

–Programmable clock polarity / clock-edge to data phase relation

–LSB/MSB first selectable

–2.5 MHz transfer rate at 10 MHz operating frequency

•Seventeen interrupt vectors, at four priority levels selectable

•Extended watchdog facilities

–15-bit programmable watchdog timer

–Oscillator watchdog

•Power saving modes

–Slow-down mode

–Idle mode (can be combined with slow-down mode)

–Software power-down mode with wake-up capability through INT0 pin

–Hardware power-down mode

•CPU running condition output pin

•ALE can be switched off

•Multiple separate VCC/VSS pin pairs

•P-MQFP-80-1 package

• Temperature Ranges : SAB-C515C-8R SAF-C515C-8R SAH-C515C-8R

TA = 0 to 70 °C TA = -40 to 85 °C TA = -40 to 110 °C

The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1 s at 6 MHz). The C515C is mounted in a P-MQFP-80 package.

Ordering Information

Type	Ordering Code	Package	Description
			(8-Bit CMOS microcontroller)
SAB-C515C-LM	Q67121-C1066	P-MQFP-80-1	for external memory (10 MHz)
SAF-C515C-LM	Q67121-C1058	P-MQFP-80-1	for external memory (10 MHz)
			ext. temp. – 40 °C to 85 °C
SAB-C515C-8RM	Q67121-DXXXX	P-MQFP-80-1	with mask programmable ROM (10 MHz)
SAF-C515C-8RM	Q67121-DXXXX	P-MQFP-80-1	with mask programmable ROM (10 MHz)
			ext. temp. – 40 °C to 85 °C

Note: Versions for extended temperature ranges – 40 °C to 110 °C (SAH-C515C-LM and SAH- C515C-8RM) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.

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C515C

Figure 2

Logic Symbol

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C515C

Figure 3

C515C Pin Configuration (P-MQFP-80-1, Top View)

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C515C

Table 1

Pin Definitions and Functions

Symbol		Pin Number	I/O*)		Function
		P-MQFP-80
		1	I
RESET					RESET
					A low level on this pin for the duration of two machine
					cycles while the oscillator is running resets the C515C. A
					small internal pullup resistor permits power-on reset
					using only a capacitor connected to VSS .
VAREF		3	–		Reference voltage for the A/D converter
VAGND		4	–		Reference ground for the A/D converter
P6.0-P6.7		12-5	I		Port 6
					is an 8-bit unidirectional input port to the A/D converter.
					Port pins can be used for digital input, if voltage levels
					simultaneously meet the specifications high/low input
					voltages and for the eight multiplexed analog inputs.
*) I = Input
O = Output

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C515C

Table 1

Pin Definitions and Functions (cont’d)

Symbol	Pin Number	I/O*)	Function
	P-MQFP-80
P3.0-P3.7	15-22	I/O	Port 3
			is an 8-bit quasi-bidirectional I/O port with internal pullup
			resistors. Port 3 pins that have 1's written to them are
			pulled high by the internal pullup resistors, and in that
			state can be used as inputs. As inputs, port 3 pins being
			externally pulled low will source current (I IL, in the DC
			characteristics) because of the internal pullup resistors.
			Port 3 also contains the interrupt, timer, serial port and
			external memory strobe pins that are used by various
			options. The output latch corresponding to a secondary
			function must be programmed to a one (1) for that
			function to operate. The secondary functions are
			assigned to the pins of port 3, as follows:
	15		P3.0	RXD				Receiver data input (asynch.) or
								data input/output (synch.) of serial
								interface
	16		P3.1	TXD				Transmitter data output (asynch.) or
								clock output (synch.) of serial
								interface
	17		P3.2					External interrupt 0 input / timer 0
				INT0
								gate control input
	18		P3.3					External interrupt 1 input / timer 1
				INT1
								gate control input
	19		P3.4	T0				Timer 0 counter input
	20		P3.5	T1				Timer 1 counter input
	21		P3.6							control output; latches the data
				WR				WR
								byte from port 0 into the external
								data memory
	22		P3.7						control output; enables the
				RD				RD
								external data memory
*) I = Input
O = Output

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C515C

Table 1

Pin Definitions and Functions (cont’d)

Symbol			Pin Number	I/O*)	Function
			P-MQFP-80
P7.0 /			23	I/O	Port 7
	INT7
					is an 1-bit quasi-bidirectional I/O port with internal pull-up
					resistor. When a 1 is written to P7.0 it is pulled high by an
					internal pull-up resistor, and in that state can be used as
					input. As input, P7.0 being externally pulled low will
					source current (I IL, in the DC characteristics) because of
					the internal pull-up resistor. If P7.0 is used as interrupt
					input, its output latch must be programmed to a one (1).
					The secondary function is assigned to the port 7 pin as
					follows:
					P7.0			Interrupt 7 input
						INT7
P1.0 - P1.7			31-24	I/O	Port 1
					is an 8-bit quasi-bidirectional I/O port with internal pullup
					resistors. Port 1 pins that have 1's written to them are
					pulled high by the internal pullup resistors, and in that
					state can be used as inputs. As inputs, port 1 pins being
					externally pulled low will source current (I IL, in the DC
					characteristics) because of the internal pullup resistors.
					The port is used for the low-order address byte during
					program verification. Port 1 also contains the interrupt,
					timer, clock, capture and compare pins that are used by
					various options. The output latch corresponding to a
					secondary function must be programmed to a one (1) for
					that function to operate (except when used for the
					compare functions). The secondary functions are
					assigned to the port 1 pins as follows:
			31		P1.0			CC0	Interrupt 3 input / compare 0 output /
						INT3
									capture 0 input
			30		P1.1	INT4		CC1	Interrupt 4 input / compare 1 output /
									capture 1 input
			29		P1.2	INT5		CC2	Interrupt 5 input / compare 2 output /
									capture 2 input
			28		P1.3	INT6		CC3	Interrupt 6 input / compare 3 output /
									capture 3 input
			27		P1.4				Interrupt 2 input
						INT2
			26		P1.5	T2EX			Timer 2 external reload / trigger
									input
			25		P1.6	CLKOUT			System clock output
			24		P1.7	T2			Counter 2 input

*) I = Input O = Output

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C515C

Table 1

Pin Definitions and Functions (cont’d)

Symbol		Pin Number	I/O*)		Function
		P-MQFP-80
XTAL2		36	I		XTAL2
					Input to the inverting oscillator amplifier and input to the
					internal clock generator circuits.
					To drive the device from an external clock source, XTAL2
					should be driven, while XTAL1 is left unconnected.
					Minimum and maximum high and low times as well as
					rise/fall times specified in the AC characteristics must be
					observed.
XTAL1		37	O		XTAL1
					Output of the inverting oscillator amplifier.
P2.0-P2.7		38-45	I/O		Port 2
					is an 8-bit quasi-bidirectional I/O port with internal pullup
					resistors. Port 2 pins that have 1's written to them are
					pulled high by the internal pullup resistors, and in that
					state can be used as inputs. As inputs, port 2 pins being
					externally pulled low will source current (I IL, in the DC
					characteristics) because of the internal pullup resistors.
					Port 2 emits the high-order address byte during fetches
					from external program memory and during accesses to
					external data memory that use 16-bit addresses
					(MOVX @DPTR). In this application it uses strong
					internal pullup resistors when issuing 1's. During
					accesses to external data memory that use 8-bit
					addresses (MOVX @Ri), port 2 issues the contents of
					the P2 special function register.
		46	O		CPU running condition
CPUR
					This output pin is at low level when the CPU is running
					and program fetches or data accesses in the external
					data memory area are executed. In idle mode, hardware
					and software power down mode, and with an active
							signal		is set to high level.
					RESET			CPUR
						can be typically used for switching external
					CPUR
					memory devices into power saving modes.
*) I = Input
O = Output

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C515C

Table 1

Pin Definitions and Functions (cont’d)

Symbol			Pin Number	I/O*)		Function
			P-MQFP-80
			47	O		The
PSEN							Program Store Enable
						output is a control signal that enables the external
						program memory to the bus during external fetch
						operations. It is activated every six oscillator periods,
						except during external data memory accesses. The
						signal remains high during internal program execution.
ALE			48	O		The Address Latch enable
						output is used for latching the address into external
						memory during normal operation. It is activated every six
						oscillator periods, except during an external data
						memory access. ALE can be switched off when the
						program is executed internally.
			49	I
EA						External Access Enable
						When held high, the C515C executes instructions always
						from the internal ROM. When held low, the C515C
						fetches all instructions from external program memory.
P0.0-P0.7			52-59	I/O		Port 0
						is an 8-bit open-drain bidirectional I/O port.
						Port 0 pins that have 1's written to them float, and in that
						state can be used as high-impedance inputs.
						Port 0 is also the multiplexed low-order address and data
						bus during accesses to external program and data
						memory. In this application it uses strong internal pullup
						resistors when issuing 1's.
						Port 0 also outputs the code bytes during program
						verification in the C515C. External pullup resistors are
						required during program verification.
P5.0-P5.7			67-60	I/O		Port 5
						is an 8-bit quasi-bidirectional I/O port with internal pullup
						resistors. Port 5 pins that have 1's written to them are
						pulled high by the internal pullup resistors, and in that
						state can be used as inputs. As inputs, port 5 pins being
						externally pulled low will source current (I IL, in the DC
						characteristics) because of the internal pullup resistors.
						Port 5 can also be switched into a bidirectional mode, in
						which CMOS levels are provided. In this bidirectional
						mode, each port 5 pin can be programmed individually as
						input or output.
*) I = Input
	O = Output

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C515C

Table 1

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

69

I

HWPD

Hardware Power Down

A low level on this pin for the duration of one machine

cycle while the oscillator is running resets the C515C.

A low level for a longer period will force the part to power

down mode with the pins floating.

P4.0-P4.7

72-74, 76-80

I/O

Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull-up

resistors. Port 4 pins that have 1’s written to them are

pulled high by the internal pull-up resistors, and in that

state can be used as inputs. As inputs, port 4 pins being

externally pulled low will source current (I IL, in the DC

characteristics) because of the internal pull-up resistors.

P4 also contains the external A/D converter control pin,

the SSC pins, the CAN controller input/output lines, and

the external interrupt 8 input. The output latch

corresponding to a secondary functionmust be

programmed to a one (1) for that function to operate.

The alternate functions are assigned to port 4 as follows:

72

P4.0

External A/D converter start pin

ADST

73

P4.1

SCLK

SSC Master Clock Output /

SSC Slave Clock Input

74

P4.2

SRI

SSC Receive Input

76

P4.3

STO

SSC Transmit Output

77

P4.4

Slave Select Input

SLS

78

P4.5

External interrupt 8 input

INT8

79

P4.6

TXDC

Transmitter output of the CAN controller

80

P4.7

RXDC

Receiver input of the CAN controller

75

I

/ Start watchdog timer

PE/SWD

Power saving mode enable

A low level on this pin allows the software to enter the

power down, idle and slow down mode. In case the low

level is also seen during reset, the watchdog timer

function is off on default.

Use of the software controlled power saving modes is

blocked, when this pin is held on high level. A high level

during reset performs an automatic start of the watchdog

timer immediately after reset. When left unconnected this

pin is pulled high by a weak internal pull-up resistor.

*) I = Input

O = Output

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Table 1

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

I/O*)

Function

P-MQFP-80

VSSCLK

13

–

Ground (0 V) for on-chip oscillator

This pin is used for ground connection of the on-chip

oscillator circuit.

VCCCLK

14

–

Supply voltage for on-chip oscillator

This pin is used for power supply of the on-chip oscillator

circuit.

VCCE1

32

–

Supply voltage for I/O ports

VCCE2

68

These pins are used for power supply of the I/O ports

during normal, idle, and power-down mode.

VSSE1

35

–

Ground (0 V) for I/O ports

VSSE2

70

These pins are used for ground connections of the I/O

ports during normal, idle, and power-down mode.

VCC1

33

–

Supply voltage for internal logic

This pins is used for the power supply of the internal logic

circuits during normal, idle, and power down mode.

VSS1

34

–

Ground (0 V) for internal logic

This pin is used for the ground connection of the internal

logic circuits during normal, idle, and power down mode.

VCCEXT

50

–

Supply voltage for external access pins

This pin is used for power supply of the I/O ports and

control signals which are used during external accesses

(for Port 0, Port 2, ALE,

PSEN,

P3.6/WR,

and P3.7/RD).

VSSEXT

51

–

Ground (0 V) for external access pins

This pin is used for the ground connection of the I/O ports

and control signals which are used during external

accesses (for Port 0, Port 2, ALE,

and

PSEN,

P3.6/WR,

.

P3.7/RD)

N.C.

2, 71

–

Not connected

These pins should not be connected.

*) I = Input

O = Output

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C515C

Figure 4

Block Diagram of the C515C

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C515C

CPU

The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% threebyte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1 s (10 MHz : 600 ns).

Special Function Register PSW (Address D0H)								Reset Value : 00H
Bit No.	MSB							LSB
	D7H	D6H	D5H	D4H	D3H	D2H	D1H	D0H
D0H	CY	AC	F0	RS1	RS0	OV	F1	P	PSW

Bit	Function
CY	Carry Flag
	Used by arithmetic instruction.
AC	Auxiliary Carry Flag
	Used by instructions which execute BCD operations.
F0	General Purpose Flag
RS1	Register Bank select control bits
RS0	These bits are used to select one of the four register banks.

		RS1	RS0	Function
		0	0	Bank 0 selected, data address 00H-07H
		0	1	Bank 1 selected, data address 08H-0FH
		1	0	Bank 2 selected, data address 10H-17H
		1	1	Bank 3 selected, data address 18H-1FH
OV	Overflow Flag
	Used by arithmetic instruction.
F1	General Purpose Flag
P	Parity Flag
	Set/cleared by hardware after each instruction to indicate an odd/even
	number of "one" bits in the accumulator, i.e. even parity.

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C515C

Memory Organization

The C515C CPU manipulates data and operands in the following five address spaces:

–up to 64 Kbyte of internal/external program memory

–up to 64 Kbyte of external data memory

–256 bytes of internal data memory

–256 bytes CAN controller registers / data memory

–2K bytes of internal XRAM data memory

–a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515C.

Figure 5

C515C Memory Map

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C515C

Control of XRAM/CAN Controller Access

The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller.

Special Function Register SYSCON (Address B1H)								Reset Value : X010XX01B
Bit No.	MSB								LSB
	7	6	5	4	3	2	1	0
B1H	–	PMOD	EALE	RMAP	–	–	XMAP1		XMAP0	SYSCON

The function of the shaded bits is not described in this section.

Bit

Function

XMAP1

XRAM/CAN controller visible access control

Control bit for

RD/WR signals during XRAM/CAN Controller accesses. If

addresses are outside the XRAM/CAN controller address range or if

XRAM is disabled, this bit has no effect.

XMAP1 = 0 : The signals

and

are not activated during accesses to

RD

WR

the XRAM/CAN Controller

XMAP1 = 1 : Ports 0, 2 and the signals

and

are activated during

RD

WR

accesses to XRAM/CAN Controller. In this mode, address

and data information during XRAM/CAN Controller accesses

are visible externally.

XMAP0

Global XRAM/CAN controller access enable/disable control

XMAP0 = 0 : The access to XRAM and CAN controller is enabled.

XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default

after reset). All MOVX accesses are performed via the

external bus. Further, this bit is hardware protected.

Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again.

The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of F700H to FFFFH.

The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the state of pin EA. Table 2 lists the various operating conditions.

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EA = 0

EA = 1

XMAP1, XMAP0

XMAP1, XMAP0

00

10

X1

00

10

X1

MOVX

DPTR

a)P0/P2→Bus

a)P0/P2→Bus

a)P0/P2→Bus

a)P0/P2→Bus

a)P0/P2→Bus

a)P0/P2→Bus

@DPTR

<

b)RD/WR active

b)RD/WR active

b)RD/WR active

b)RD/WR active

b)RD/WR active

b)RD/WR active

XRAM/CAN

c)ext.memory

c)ext.memory

c)ext.memory

c)ext.memory

c)ext.memory

c)ext.memory

address

is used

is used

is used

is used

is used

is used

range

DPTR

a)P0/P2→Bus

a)P0/P2→Bus

a)P0/P2→Bus

a)P0/P2→I/0

a)P0/P2→Bus

a)P0/P2→Bus

≥

(RD/WR-Data)

(RD/WR-Data)

(RD/WR-Data)

XRAMCAN

b)RD/WR

b)RD/WR active

b)RD/WR active

b)RD/WR

b)RD/WR active

b)RD/WR active

address

inactive

c)XRAM is used

c) ext.memory

inactive

c)XRAM is used

c) ext.memory

range

c)XRAM is used

is used

c)XRAM is used

is used

MOVX

XPAGE

a)P0→Bus

a)P0→Bus

a)P0→Bus

a)P0→Bus

a)P0→Bus

a)P0→Bus

@ Ri

<

P2→I/O

P2→I/O

P2→I/O

P2→I/O

P2→I/O

P2→I/O

XRAMCAN

b)RD/WR active

b)RD/WR active

b)RD/WR active

b)RD/WR active

b)RD/WR active

b)RD/WR active

addr.page

c)ext.memory

c)ext.memory

c)ext.memory

c)ext.memory

c)ext.memory

c)ext.memory

range

is used

is used

is used

is used

is used

is used

XPAGE

a)P0→Bus

a)P0→Bus

a)P0→Bus

a)P2→I/O

a)P0→Bus

a)P0→Bus

≥

P2→I/O

P0/P2→I/O

P2→I/O

(RD/WR-Data)

(RD/WR-Data

(RD/WR-Data)

XRAMCAN

P2→I/O

only)

P2→I/O

addr.page

P2→I/O

b)RD/WR

b)RD/WR active

b)RD/WR

b)RD/WR active

b)RD/WR active

range

inactive

inactive

b)RD/WR active

c)XRAM is used

c)ext.memory

c)XRAM is used

c)XRAM is used

c)ext.memory

c)XRAM is used

is used

is used

modes compatible to 8051/C501 family

Table 2

Behaviour of P0/P2 and RD/WR During MOVX Accesses

C515C

C515C

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting

the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6

Reset Circuitries

Figure 7 shows the recommended oscillator circiutries for crystal and external clock operation.

Figure 7

Recommended Oscillator Circuitries

Semiconductor Group

19

1997-07-01

C515C

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function register DPSEL. Figure 8 illustrates the datapointer addressing mechanism.

	-	-	-	-	-		.2	.1		.0
	DPSEL(92 H)														DPTR7
	DPSEL						Selected
							Data-
	.2		.1	.0			pointer
	0		0	0			DPTR 0								DPTR0
	0		0	1			DPTR 1
													DPH(83H)	DPL(82H)
	0		1	0			DPTR 2
	0		1	1			DPTR 3
	1		0	0			DPTR 4									External Data Memory
	1		0	1			DPTR 5
	1		1	0			DPTR 6									MCD00779
	1		1	1			DPTR 7

Figure 8

External Data Memory Addressing using Multiple Datapointers

Semiconductor Group

20

1997-07-01

C515C

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

				ICE-System Interface
			to Emulation Hardware
SYSCON		RESET	RSYSCON
		EA
PCON			RPCON		EH-IC
TCON		ALE	RTCON
		PSEN
	C500	Port 0		Enhanced Hooks
	MCU			Interface Circuit
		Port 2
Optional	Port 3	Port 1	RPort 2	RPort 0	TEA	TALE TPSEN
I/O Ports
			Target System Interface			MCS03280

Figure 9

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

Semiconductor Group

21

1997-07-01