OKI MR27V401DTA, MR27V401DMA, MR27V401DRA Datasheet

¡ Semiconductor

1A

MR27V401D

524,288-Word x 8-Bit One Time PROM

DESCRIPTION

The MR27V401D is a 4Mbit electrically Programmable Read-Only Memory organized as 524,288 word x 8bit. The MR27V401D operates on a single +3V-3.3V power supply and is TTL compatible. Since the MR27V401D operates asynchronously , external clocks are not required , making this device easy-to-use. The MR27V401D is suitable as large-capacity fixed memory for microcomputers and data terminals. It is manufactured using a CMOS double silicon gate technology and is offered in 32-pin DIP, 32-pin SOP or 32-pin TSOP packages.

FEATURES

•524,288 word x 8bit

•Single +3V-3.3V power supply

• Access time	80ns access time (Vcc=+3V)
	70ns access time (Vcc=+3.3V)
• Input / Output TTL compatible
• Three-state output
• Packages	32-pin plastic DIP (DIP32-P-600-2.54)	(Product name : MR27V401DRA)
	32-pin plastic SOP (SOP32-P-525-1.27-K)	(Product name : MR27V401DMA)
	32-pin plastic TSOP (TSOP I 32-P-814-0.50-K) (Product name : MR27V401DTA)

November 1999

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MR27V401D

PIN CONFIGURATION (TOP VIEW)

Vpp	1		32	VCC			Vpp	1		32	VCC
A16	2		31	A18			A16	2		31	A18
A15				A17			A15				A17
	3		30					3		30
A12				A14			A12				A14
	4		29					4		29
A7				A13			A7				A13
	5		28					5		28
A6				A8			A6				A8
	6		27					6		27
A5				A9			A5				A9
	7		26					7		26
A4				A11			A4				A11
	8		25					8		25
A3							A3
	9		24		OE			9		24		OE
A2				A10			A2				A10
	10		23					10		23
A1				CE			A1
	11		22					11		22		CE
A0				D7			A0				D7
	12		21					12		21
D0				D6			D0				D6
	13		20					13		20
D1				D5			D1				D5
	14		19					14		19
D2				D4			D2				D4
	15		18					15		18
VSS				D3			VSS				D3
	16		17					16		17

32-pin DIP

32-pin SOP

A5

A7

A15

Vpp

A18

A14

A8

A11

A4

A6

A12

A16

VCC

A17

A13

A9

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

32-pin TSOP

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

A3

A2

A1

D0

D1

D2

VSS

D3

D4

D5

D6

D7

A10

A0

CE

OE

PIN NAMES

FUNCTIONS

A0 - A18

Address input

D0 - D7

Data output

Chip enable

CE

Output enable

OE

VCC

Power supply voltage

VSS

GND

VPP

Program Power supply voltage

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MR27V401D

BLOCK DIAGRAM

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

Address Buffer

		CE		OE		VPP
		CE		OE		PGM

Decoder			Memory Matrix
Row			524,288X8-Bit
Decoder			Multiplexer
Column			Output Buffer
D0	D1	D2	D3	D4	D5	D6	D7

FUNCTION TABLE

MODE							VPP	VCC		D0 - D7
	CE				OE
READ		L			L					DOUT
OUTPUT DISABLE		L			H		**	3.0V to 3.3V		Hi-Z
STAND-BY		H		*						Hi-Z
PROGRAM		L			H					DIN
PROGRAM INHIBIT		H			H		9.75V	4.0V		Hi-Z
PROGRAM VERIFY		H			L					DOUT

*: Don't Care (H or L)

**: Don't Care (H or L or Open)

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							MR27V401D
	ABSOLUTE MAXIMUM RATINGS
	Parameter	Symbol		Condition	Value			Unit
	Operating temperature under bias	Topr	-		0 to 70			°C
	Storage temperature	Tstg			-55 to 125			°C
	Input voltage	VI			-0.5 to VCC + 0.5			V
	Output voltage	VO		relative to VSS	-0.5 to VCC + 0.5			V
	Power supply voltage	VCC			-0.5 to 5			V
	Program power supply voltage	VPP			-0.5 to 11.5			V
	Power dissipation per package	PD	-		1.0			W

RECOMMENDED OPERATING CONDITIONS

(Ta=0 to 70°C)

Parameter	Symbol	Condition		Min.	Typ.	Max.	Unit
VCC power supply voltage	VCC			2.7	-	3.6	V
VPP power supply voltage	VPP	VCC=2.7V - 3.6V		-0.5	-	VCC+0.5	V
Input "H" level	VIH			2.2	-	VCC+0.5*	V
Input "L" level	VIL			-0.5**	-	0.6	V

Voltage is relative to Vss

*: Vcc+1.5V (Max.) when pulse width of overshoot is less than 10nS.

**: -1.5V (Min.) when pulse width of undershoot is less than 10nS.

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