OKI ML64P168-xxxGP, ML64P168-NGA, ML64P168-NGP, ML64P168-xxxGA Datasheet

FEDL64P168-01

Semiconductor

ML64P168

This version: Sep. 27,1999 Previous version: Jun. 22,1999

4-Bit Microcontroller with Built-in RC Oscillation Type A/D Converter and LCD Driver

GENERAL DESCRIPTION

The ML64P168 is a one-time-programmable ROM-version product, which has one-time PROM (OTP) as internal program memory. On the other hand, the ML64168 is a mask ROM-version product, which has mask ROM as internal program memory.

Unlike the mask ROM-version product (ML64168), the ML64P168 cannot be supplied in the form of a chip.

The ML64P168 has two operation modes, microcontroller operation mode and PROM mode. The microcontroller operation mode is used to operate the ML64P168 like a ML64168 and the PROM mode is used to program or read the PROM.

The ML64P168 is a low power 4-bit microcontroller incorporating the Oki’s original CPU core nX- 4/30.

The ML64P168 provides a minimum instruction execution time of 4.3 s (@700kHz).

The ML64P168 contains 8160-byte program memory, 512-nibble data memory, three 4-bit input-output ports, 4-bit input port, 4-bit output port, 2-channel RC oscillation type A/D converter, LCD driver for up to 120 segments, and buzzer output port.

APPLICATION

The ML64P168 is best suited for low power, high precision thermometers and hygrometers.

FEATURES

∙ Processing speed
Minimum instruction execution time	: 4.3 s @700 kHz
	91.6 s @32.768 kHz
∙ Clock generation circuit
Low-speed clock	: 32.768 kHz crystal oscillator
High-speed clock	: 700 kHz RC oscillator ( with an external resistor )
CPU clock is selectable as Low-speed clock / High-speed clock by software.
∙ Operating voltage	: 1.5 V spec. / 3.0 V spec. ( selectable by mask option )
	1.45 to 1.70 V (1.5V spec.)
	2.7 to 3.5 V (3.0V spec.)
∙ Operating temperature	: 0 to +65° C

The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date.

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∙ Memory space
Internal program memory	: 8160 bytes
Internal data memory	:	512 nibbles
∙ RC oscillation type A/D converter	: 2 channels
		Time division 2-channel method
Counter A	: 1 / ( 104 ×			8 ) × 1
Counter B	: 1 / 214 ×		1
∙ I/O port
Input-output port	: 3 ports		×	4 bits
Input port	: 1 port		×	4 bits
Output port	: 1 port		×	4 bits
		( 8 out of the 34 LCD driver outputs can be used as
		output-only ports by mask option. )
∙ LCD driver	:	34 outputs
(1) At 1/4 duty and 1/3 bias	: 120 segments (max.)
(2) At 1/3 duty and 1/3 bias	:	93 segments (max.)
(3) At 1/2 duty and 1/2 bias	:	64 segments (max.)

Voltage Regulator for LCD Driver (selectable by mask option)

The LCD panel display is stable regardless of temporary supply voltage drop, because the voltage generated by the voltage regulator for LCD driver is supplied to the bias voltage generator as a reference voltage.

LCD Operating Voltage

When the voltage regulator for LCD driver is used

:3.6 V ( Duty cycle = 1/4 or 1/3 )

:2.4 V ( Duty cycle = 1/2 )

When the voltage regulator for LCD driver is not used

	: 4.5 V ( Duty cycle = 1/4 or 1/3 )
	: 3.0 V ( Duty cycle = 1/2 )
∙ Buzzer driver	: 1 output ( 4 output modes selectable )
∙ Serial port	: Synchronous 8-bit transfer
	Selectable as external clock / internal clock
	Selectable as MSB first / LSB first
∙ Capture circuit	: 2 channels ( 32Hz, 64Hz, 128Hz, 256Hz )
∙ Battery check circuit	: 1 ( incorporated into the input-only port )
∙ Watchdog timer
∙ Interrupt
External interrupt	: 2 sources
Internal interrupt	: 8 sources
∙ Package:
80-pin plastic QFP ( QFP80-P-1420-0.80-BK )
Product name	: ML64P168 - xxxGP ( written PROM )
	ML64P168 - NGP	( blanked PROM )
80-pin plastic QFP ( QFP80-P-1414-0.65-K )
Product name	: ML64P168 - xxxGA ( written PROM )
	ML64P168 - NGA	( blanked PROM )
	xxx indicates a code number.

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PROGRAM DEVELOPMENT ENVIRONMENT

∙ Structured Assembler	:	SASM64K
∙ In Circuit Emulator	:	EASE64168
∙ Debugger	:	DT64K

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BLOCK DIAGRAM

			CPU CORE: nX-4/30
			DATA BUS ( 8 )
BSR	TR2	TR0	TR1
MIEF	C	ALU	PCH	PCM PCL
HALT
	B A		H L	X Y

TIMING

CONTROLLER

OSC1

OSC2

XT 2CLK

XT

RST RSTC

TST1 TST2 TST

DATA BUS ( 8 )

SP

BC

INT

5

SIOP

TBC

INT

BD					BD
					CAPR
					INTC
					WDT
INT
IN0
CS0
RS0
CRT0					ADC
RT0
IN1
CS1
RS1

RT1

INT

BUS ADDRESS

		VPP
	IR
	DECORDER
	IR
	ROMR	PROM
		8160
		Bytes

RAM 512 Nibbles

							VDD1
			BIAS				VDD2
							VDD3
							C1
							C2
							L0
			LCD				L1
							to
							L33
			VDDI
							P2.0
			P2
			P3				P2.1
							to
			P4
							P4.3
INT
			VDDI
							P1.0
			P1				P1.1
							P1.2
							P1.3
			VDDI				P0.0
			P0				P0.1
							P0.2
INT							P0.3

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PIN CONFIGURATION (TOP VIEW)

P0.3	P0.2			P0.1	P0.0		P1.3			P1.2		P1.1		P1.0				TST1		RESET		XT		XT		VDD		OSC1		OSC2
																TST2
80		79		78		77		76		75		74		73		72		71		70		69		68		67		66		65

L0	1
L1
	2
L2	3
L3	4
L4	5
L5	6
L6	7
L7	8
L8	9
L9	10
L10	11
L11	12
L12	13
L13	14
L14	15
L15	16
L16	17
P2.0	18
P2.1
	19
P2.2	20
P2.3	21
P3.0	22
P3.1	23
P3.2	24

25		26		27		28		29		30		31		32		33		34		35		36		37		38		39		40
P3.3		P4.0		P4.1		P4.2		P4.3		BD		VPP		VSS	RT0			CRT0		RS0	CS0			IN0		IN1		CS1	RS1

( GP : QFP80-P-1420-0.80-BK )

80-Pin Plastic QFP

64	L33 / P6.3
	L32 / P6.2
63
62	L31 / P6.1
	L30 / P6.0
61
	L29 / P5.3
60
	L28 / P5.2
59
	L27 / P5.1
58
	L26 / P5.0
57
	L25
56
	L24
55
	L23
54
	L22
53
52	L21
	L20
51
	L19
50
	L18
49
	L17
48
	C2
47
	C1
46
	VDD3
45
	VDD2
44
	VDDI
43
42	VDD1
	RT1
41

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PIN CONFIGURATION (TOP VIEW)																						( continued )
			L1		L0		P0.3		P0.2		P0.1		P0.0		P1.3		P1.2		P1.1		P1.0		TST2		TST1		RESET		XT		XT		VDD		OSC1		OSC2		L33 / P6.3		L32 / P6.2
			80		79		78		77		76		75		74		73		72		71		70		69		68		67		66		65		64		63		62		61
L2
	1																																										60
L3	2																																										59
L4	3																																										58
L5	4																																										57
L6	5																																										56
L7	6																																										55
L8	7																																										54
L9	8																																										53
L10	9																																										52
L11	10																																										51
L12	11																																										50
L13	12																																										49
L14	13																																										48
L15	14																																										47
L16	15																																										46
P2.0	16																																										45
P2.1	17																																										44
P2.2	18																																										43
P2.3	19																																										42
P3.0	20																																										41
			21		22		23		24		25		26		27		28		29		30		31		32		33		34		35		36		37		38		39		40
			P3.1		P3.2		P3.3		P4.0		P4.1		P4.2		P4.3		BD		VPP		VSS		RT0		CRT0		RS0		CS0		IN0		IN1		CS1		RS1		RT1		VDD1

( GA : QFP80-P-1414-0.65-K )

80-Pin Plastic QFP

L31 / P6.1

L30 / P6.0

L29 / P5.3

L28 / P5.2

L27 / P5.1

L26 / P5.0

L25

L24

L23

L22

L21

L20

L19

L18

L17

C2

C1

VDD3

VDD2

VDDI

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PIN DESCRIPTIONS

The basic functions of each pin of the ML64P168 is described in Table 1. A symbol with a slash ( / ) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions.

For Type, “ - ” denotes a power supply pin, “ I ” an input pin, “O” an output pin, and “I/O” an inputoutput pin.

Table 1 Pin Descriptions ( Basic Functions )

	Function	Symbol	Pin No.		Type			Description
			GP	GA
		VSS	32	30	-	0V power supply
		VDD	67	65	-	Positive power supply
		VDD1	42	40	-	Bias output for driving LCD (+1.5 V, +1.2 V* )
		VDD2	44	42	-	Bias output for driving LCD (+3.0 V, +2.4 V* )
	Power
		VDD3	45	43	-	Bias output for driving LCD (+4.5 V, +3.6 V* )
	Supply
		VDDI	43	41	-	Positive power supply for I/O port interface
		VPP	31	29	-	Power supply (+12.5 V) for PROM writing
		C1	46	44	-	Pins for connecting a capacitor for generating LCD driving
		C2	47	45	-	bias
		XT	69	67	I	Low-speed clock oscillation input and output pins.
		XT	68	66	O	Connect to a crystal ( 32.768 kHz ).
	Oscillation
		OSC1	66	64	I	High-speed clock oscillation input and output pins.
		OSC2	65	63	O	Connect to an external resistor for oscillation ( ROS ).
	Test	TST1	71	69	I	Input pins for testing.
		TST2	72	70	I	A pull-up resistor is internally connected to these pins.
						System reset input pin.
	Reset	RESET	70	68	I	Setting this pin to ″	L ″	level puts this device into a reset state.
						Then, setting this	pin	to ″ H ″ level starts executing an
						instruction from address 0000H.

*When the voltage regulator for LCD driver is used.

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	Table 1		Pin Descriptions ( Basic Functions ) ( continued )
Function	Symbol	Pin No.			Type	Description
		GP		GA
	P0.0/					4-bit input port ( Port 0 )
	INT1/	77		75		Selectable as pull-up resistor input, pull-down resistor input,
	CAPIN0					or high impedance input by the port 01 control register
	P0.1/					( P01CON ).
	INT1/	78		76
	CAPIN1				I
	P0.2/	79		77
	INT1
	P0.3/
	INT1/	80		78
	CMP
	P1.0	73		71		4-bit output port ( Port 1 )
						Selectable as NMOS open drain output or CMOS output by
	P1.1	74		72
					O	the port 01 control register ( P01CON ).
	P1.2	75		73		P1.0 is a high current drive output port.
	P1.3	76		74
	P2.0/	18		16		4-bit input-output port ( Port 2 )
	INT0					Fllowing can be specified for each bit by the port 2 control
	P2.1/	19		17		registers 0 to 3 ( P20CON to P23CON ).
	INT0					(1) input or output
					I/O
	P2.2/	20		18		(2) pull-up/pull-down resistor input or high impedance input
	INT0					(3) NMOS open drain output or CMOS output
Ports
	P2.3/	21		19
	INT0
	P3.0/	22		20		4-bit input-output port ( Port 3 )
	INT0					Following can be specified for each bit by the port 3 control
	P3.1/	23		21		registers 0 to 3 ( P30CON to P33CON ).
	INT0					(1) input or output
	P3.2/	24		22	I/O	(2) pull-up/pull-down resistor input or high impedance input
	INT0					(3) NMOS open drain output or CMOS output
	P3.3/
	INT0/	25		23
	SIN
	P4.0/					4-bit input-output port ( Port 4 )
	INT0/	26		24		Following can be specified for each bit by the port 4 control
	SOUT					registers 0 to 3 ( P40CON to P43CON ).
	P4.1/					(1) input or output
	INT0/	27		25		(2) pull-up/pull-down resistor input or high impedance input
	SPR				I/O	(3) NMOS open drain output or CMOS output
	P4.2/
	INT0/	28		26
	SCLK
	P4.3/
	INT0/	29		27
	MON

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	Table 1		Pin Descriptions ( Basic Functions ) ( continued )
Function	Symbol	Pin No.			Type	Description
		GP		GA
Buzzer	BD	30		28	O	Output pin for the buzzer driver.
	RT0	33		31	O	Resistance temperature sensor connection pin
						( for channel 0 )
	CRT0	34		32	O	Resistance/capacitance temperature sensor connection pin
						( for channel 0 )
	RS0	35		33	O	Reference resistor connection pin
						( for channel 0 )
	CS0	36		34	O	Reference capacitor connection pin
						( for channel 0 )
A/D	IN0	37		35	I	Input pin for RC oscillator circuit
Converter						( for channel 0 )
	RT1	41		39	O	Resistance temperature sensor connection pin
						( for channel 1 )
	RS1	40		38	O	Reference resistor connection pin
						( for channel 1 )
	CS1	39		37	O	Reference capacitor connection pin
						( for channel 1 )
	IN1	38		36	I	Input pin for RC oscillator circuit
						( for channel 1 )

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	Table 1		Pin Descriptions ( Basic Functions ) ( continued )
Function	Symbol	Pin No.			Type	Description
		GP		GA
	L0	1		79	O	LCD segment and common signals output pins.
	L1	2		80	O
	L2	3		1	O
	L3	4		2	O
	L4	5		3	O
	L5	6		4	O
	L6	7		5	O
	L7	8		6	O
	L8	9		7	O
	L9	10		8	O
	L10	11		9	O
	L11	12		10	O
	L12	13		11	O
	L13	14		12	O
	L14	15		13	O
	L15	16		14	O
LCD	L16	17		15	O
Driver	L17	48		46	O
	L18	49		47	O
	L19	50		48	O
	L20	51		49	O
	L21	52		50	O
	L22	53		51	O
	L23	54		52	O
	L24	55		53	O
	L25	56		54	O
	L26 / P5.0	57		55	O	LCD segment and common signals output pins.
						These pins can be configured to be output ports by a mask
	L27 / P5.1	58		56	O
						option.
	L28 / P5.2	59		57	O
	L29 / P5.3	60		58	O
	L30 / P6.0	61		59	O
	L31 / P6.1	62		60	O
	L32 / P6.2	63		61	O
	L33 / P6.3	64		62	O

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Table 2 Pin Descriptions ( Secondary Functions )

	Function	Symbol	Pin No.		Type	Description
			GP	GA
		P2.0/	18	16		Secondary functions of P2.0 to P2.3, P3.0 to P3.3, and P4.0
		INT0				to P4.3:
		P2.1/	19	17		Level-triggered external 0 interrupt input pins.
		INT0				The change of input signal level causes an interrupt to occur.
					I
		P2.2/	20	18
		INT0
		P2.3/	21	19
		INT0
		P3.0/	22	20
		INT0
		P3.1/	23	21
		INT0
					I
		P3.2/	24	22
		INT0
		P3.3/	25	23
	External	INT0
	Interrupt	P4.0/	26	24
		INT0
		P4.1/	27	25
		INT0
					I
		P4.2/	28	26
		INT0
		P4.3/	29	27
		INT0
		P0.0/	77	75		Secondary functions of P0.0 to P0.3:
		INT1				Level-triggered external 1 interrupt input pins.
		P0.1/	78	76		The change of input signal level causes an interrupt to occur.
		INT1
					I
		P0.2/	79	77
		INT1
		P0.3/	80	78
		INT1
		P0.0/				Secondary functions of P0.0:
			77	75		This pin is assigned the capture circuit trigger input pin of
		CAPIN0
	Capture					CAPR0 function .
					I
	trigger	P0.1/				Secondary functions of P0.1:
			78	76		This pin is assigned the capture circuit trigger input pin of
		CAPIN1
						CAPR1 function .
		P3.3/	25	23	I	Secondary functions of P3.3:
		SIN				This pin is assigned the data input of a serial port.
		P4.0/	26	24	O	Secondary functions of P4.0:
	Serial	SOUT				This pin is assigned the data output of a serial port.
	port	P4.1/	27	25	O	Secondary functions of P4.1:
		SPR				This pin is assigned the ready output of a serial port.
		P4.2/	28	26	I/O	Secondary functions of P4.2:
		SCLK				This pin is assigned the clock input-output of a serial port.

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Table 2 Pin Descriptions ( Secondary Functions ) ( continued )

	Function	Symbol	Pin No.		Type	Description
			GP	GA
	RC					Secondary functions of P4.3:
		P4.3/				This pin is a monitor output of the RC oscillation clock for an
	Oscillation		29	27	O
		MON				A/D converter and a 700kHz RC oscillation clock for a system
	Monitor
						clock.
	Battery	P0.3/				Secondary functions of P0.3:
			80	78	I	This pin is an analog comparator input pin for battery check
	Check	CMP
						circuit.

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MEMORY MAPS

Program Memory ( PROM )

Test program area

1FFFH

32 bytes

1FE0H

8160 bytes

003EH
		Interrupt area
0020H
		CZP area
0010H
		Start address
0000H
			8 bits

Program Memory Map

	Contents of interrupt area
003BH	Watchdog interrupt
0038H	External 0 interrupt
0035H	Serial port interrupt
0032H	External 1 interrupt
002FH	A/D converter interrupt
002CH	256Hz interrupt
0029H	32Hz interrupt
0026H	16Hz interrupt
0023H	1Hz interrupt
0020H	0.1Hz interrupt

Address 0000H is the instruction execution start address by the system reset.

The CZP area from address 0010H to address 001FH is the start address for the CZP subroutine of 1- byte call instruction.

The start address of interrupt subroutine is assigned to the interrupt address from address 0020H to 003DH.

The user area has 8160 bytes of address 0000H to 1FDFH. No program can be stored in the test program area.

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Data Memory

The data memory area consists of 8 banks and each bank has 256 nibbles ( 256 × 4 bits ).

The data RAM is assigned to BANK 6, BANK 7 and peripheral ports are assigned to BANK 0.

7FFH
	BANK7							Data / Stack area ( 128 nibbles )
780H	Data RAM area
	( 256 nibbles )
700H
			512 nibbles
6FFH	BANK6
	Data RAM area
	( 256 nibbles )
600H

07FH Contents of 000H to 07FH

Inaccessible area

SFR area

100H

0FFH

Unused area

080H

07FH

BANK0

000H 000H

4 bits

Data Memory Map

Half the BANK 7 of Data RAM area ( 128 nibbles ) is shared by the stack area. The stack is a memory starting from address 7FFH toward the low-order addresses where 4 nibbles are used by Subroutine Call Instruction and 8 nibbles are used by an interrupt.

The addresses 080H to 0FFH of BANK 0 are not assigned as the data memory, so access to these addresses has no effect. Moreover, it is impossible to access BANK 1 to BANK 5.

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ABSOLUTE MAXIMUM RATINGS ( 1.5 V Spec. )

				(VSS = 0V)
Parameter	Symbol	Condition	Rating		Unit
Power supply voltage 1	VDD1	Ta = 25°C	-0.3 to + 2.0		V
Power supply voltage 2	VDD2	Ta = 25°C	-0.3 to + 4.0		V
Power supply voltage 3	VDD3	Ta = 25° C	-0.3 to + 5.5		V
Power supply voltage 4	VDDI	Ta = 25° C	-0.3 to + 5.5		V
Power supply voltage 5	VDD	Ta = 25° C	-0.3 to + 2.0		V
Input voltage 1	VIN1	VDD input, Ta = 25° C	-0.3 to VDD+ 0.3		V
Input voltage 2	VIN2	VDDI input, Ta = 25° C	-0.3 to VDDI+ 0.3		V
Output voltage 1	VOUT1	VDD1 output, Ta = 25° C	-0.3 to VDD1+ 0.3		V
Output voltage 2	VOUT2	VDD2 output, Ta = 25° C	-0.3 to VDD2+ 0.3		V
Output voltage 3	VOUT3	VDD3 output, Ta = 25° C	-0.3 to VDD3+ 0.3		V
Output voltage 4	VOUT4	VDD output, Ta = 25° C	-0.3 to VDD+ 0.3		V
Output voltage 5	VOUT5	VDDI output, Ta = 25° C	-0.3 to VDD+ 0.3		V
		Ta = 0 to + 65° C	381		mW
		QFP80-P-1420-0.80-BK
Power Dissipation	PD
		Ta = 0 to + 65° C	334		mW
		QFP80-P-1414-0.65-K
Storage temperature	TSTG	-	-55 to + 150		° C

RECOMMENDED OPERATING CONDITIONS ( 1.5V Spec. )

				(VSS = 0V)
Parameter	Symbol	Condition	Rating		Unit
Operating Temperature*	Top	-	0 to + 65		° C
Operating Voltage*	VDD,VDD1	-	1.45 to 1.70		V
	VDDI	-	2.70 to 5.25		V
External 700kHz RC Oscillator	ROS	-	60 to 200		kΩ
Resistance*
Crystal oscillation frequency*	fXT	-	30 to 35		kHz

* : At Non-regulated LCD driver.

In case of select a voltage regulated LCD driver, see P.37/51.

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ELECTRICAL CHARACTERISTICS ( 1.5 V Spec. )

DC Characteristics ( 1.5 V Spec. )

(VSS=0V, VDD1=VDD=1.5V, VDDI=2.7V, Ta=0 to +65° C unless otherwise specified )

	Parameter	Symbol	Condition		Min.	Typ.	Max.	Unit	Measuring
									Circuit
	VDD2 Voltage*	VDD2	Ca, Cb, C12=0.1	+100%	2.8	3.0	3.2	V
				F
				-50%
	VDD3 Voltage*	VDD3	Ca, Cb, C12=0.1	+100%	4.3	4.5	4.7	V
				F
				-50%
	Crystal Oscillation	VSTA	Oscillation start time:		1.47	-	-	V
	Start Voltage		within 5 seconds
	Crystal Oscillation	VHOLD	-		1.40	-	-	V
	Hold Voltage
	Crystal Oscillation	TSTOP	-		0.1	-	1000	ms
	Stop Detection Time
	Internal Crystal	CG	-		10	15	20	pF	1
	Oscillator Capacitance
	External Crystal	CGEX	When external CG used		10	-	30	pF
	Oscillator Capacitance
	Internal Crystal	CD	-		10	15	20	pF
	Oscillator Capacitance
	Internal 700kHz RC	COS	-		8	12	16	pF
	Oscillator Capacitance
	700kHz RC Oscillation	fOSC	External resistor ROS=160kΩ		80	280	350	kHz
	Frequency		VDD = 1.45 to 1.70V
	POR Generation	VPOR1	When VDD is between		0	-	0.4	V
	Voltage		VPOR1 and 1.5V
	POR Non-generation	VPOR2	No POR when VDD is		1.4	-	1.5	V
	Voltage		between VPOR2 and 1.5V
	Battery Check	VRB	Ta = 25° C		0.50	0.60	0.70	V
	Reference Voltage
									2
	VRB Temperature	∆ VRB	-		-	-2	-	mV/° C
	Variation

Notes: 1.”POR” denotes Power On Reset.

2.”TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs.

* : At Non-regulated LCD driver.

In case of select a voltage regulated LCD driver, see P.37/51.

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