MM74C927
March 1988
MM74C925, MM74C926, MM74C927, MM74C928 4-Digit Counters with Multiplexed
7-Segment Output Drivers
General Description
These CMOS counters consist of a 4-digit counter, an internal output latch, NPN output sourcing drivers for a 7-seg- ment display, and an internal multiplexing circuitry with four multiplexing outputs. The multiplexing circuit has its own free-running oscillator, and requires no external clock. The counters advance on negative edge of clock. A high signal on the Reset input will reset the counter to zero, and reset the carry-out low. A low signal on the Latch Enable input will latch the number in the counters into the internal output latches. A high signal on Display Select input will select the number in the counter to be displayed; a low level signal on the Display Select will select the number in the output latch to be displayed.
The MM74C925 is a 4-decade counter and has Latch Enable, Clock and Reset inputs.
The MM74C926 is like the MM74C925 except that it has a display select and a carry-out used for cascading counters. The carry-out signal goes high at 6000, goes back low at 0000.
The MM74C927 is like the MM74C926 except the second most significant digit divides by 6 rather than 10. Thus, if the clock input frequency is 10 Hz, the display would read tenths of seconds and minutes (i.e., 9:59.9).
The MM74C928 is like the MM74C926 except the most significant digit divides by 2 rather than 10 and the carry-out is
an overflow indicator which is high at 2000, and it goes back low only when the counter is reset. Thus, this is a 3(/2-digit counter.
Features
Y Wide supply voltage range |
3V to 6V |
Y Guaranteed noise margin |
1V |
Y High noise immunity |
0.45 VCC (typ.) |
Y High segment sourcing current |
40 mA |
@ VCC b 1.6V, VCC e 5V
Y Internal multiplexing circuitry
Design Considerations
Segment resistors are desirable to minimize power dissipation and chip heating. The DS75492 serves as a good digit driver when it is desired to drive bright displays. When using this driver with a 5V supply at room temperature, the display can be driven without segment resistors to full illumination. The user must use caution in this mode however, to prevent overheating of the device by using too high a supply voltage or by operating at high ambient temperatures.
The input protection circuitry consists of a series resistor, and a diode to ground. Thus input signals exceeding VCC will not be clamped. This input signal should not be allowed to exceed 15V.
Connection Diagrams
Dual-In-Line Package |
Dual-In-Line Package |
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TL/F/5919 ± 1 |
TL/F/5919 ± 2 |
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Top View |
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Top View |
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Order Number MM74C925 |
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Order Number MM74C926, |
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MM74C927 or MM74C928 |
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Output Segment-7 Multiplexed with |
MM74C927, MM74C926, MM74C925, |
Drivers |
MM74C928 |
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Counters Digit-4 |
C1995 National Semiconductor Corporation |
TL/F/5919 |
RRD-B30M105/Printed in U. S. A. |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Voltage at Any Output Pin |
GND b 0.3V to VCC a 0.3V |
Voltage at Any Input Pin |
GND b 0.3V to a15V |
Operating Temperature |
b40§C to a85§C |
Range (TA) |
Storage Temperature Range |
b65§C to a150§C |
Power Dissipation (PD) |
Refer to PD(MAX) vs TA Graph |
Operating VCC Range |
3V to 6V |
VCC |
6.5V |
Lead Temperature |
260§C |
(Soldering, 10 seconds) |
DC Electrical Characteristics Min/Max limits apply at b40§C s Tj s a85§C, unless otherwise noted
Symbol |
Parameter |
Conditions |
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Min |
Typ |
Max |
Units |
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CMOS TO CMOS |
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VIN(1) |
Logical ``1'' Input Voltage |
VCC e 5V |
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3.5 |
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V |
VIN(0) |
Logical ``0'' Input Voltage |
VCC e 5V |
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1.5 |
V |
VOUT(1) |
Logical ``1'' Output Voltage |
VCC e 5V, IO e b10 mA |
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(Carry-Out and Digit Output |
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4.5 |
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V |
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Only) |
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VOUT(0) |
Logical ``0'' Output Voltage |
VCC e 5V, IO e 10 mA |
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0.5 |
V |
IIN(1) |
Logical ``1'' Input Current |
VCC e 5V, VIN e 15V |
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0.005 |
1 |
mA |
IIN(0) |
Logical ``0'' Input Current |
VCC e 5V, VIN e 0V |
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b1 |
b0.005 |
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mA |
ICC |
Supply Current |
VCC e 5V, Outputs Open Circuit, |
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20 |
1000 |
mA |
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VIN e 0V or 5V |
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CMOS/LPTTL INTERFACE |
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VIN(1) |
Logical ``1'' Input Voltage |
VCC e 4.75V |
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VCC b 2 |
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V |
VIN(0) |
Logical ``0'' Input Voltage |
VCC e 4.75V |
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0.8 |
V |
VOUT(1) |
Logical ``1'' Output Voltage |
VCC e 4.75V, |
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(Carry-Out and Digit |
IO e b360 mA |
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2.4 |
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V |
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Output Only) |
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VOUT(0) |
Logical ``0'' Output Voltage |
VCC e 4.75V, IO e 360 mA |
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0.4 |
V |
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OUTPUT DRIVE |
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VOUT |
Output Voltage (Segment |
IOUT e b65 mA, VCC e 5V, Tj e 25§C |
VCC b 2 |
VCC b 1.3 |
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V |
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Sourcing Output) |
IOUT e b40 mA, VCC e |
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Tj e 100§C |
VCC b 1.6 |
VCC b 1.2 |
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V |
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5V |
Ð Tj e 150§C |
VCC b 2 |
VCC b 1.4 |
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V |
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RON |
Output Resistance (Segment |
IOUT e b65 mA, VCC e 5V, Tj e 25§C |
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20 |
32 |
X |
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Sourcing Output) |
IOUT e b40 mA, VCC e |
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Tj e 100§C |
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30 |
40 |
X |
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5V |
Ð Tj e 150§C |
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35 |
50 |
X |
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Output Resistance (Segment |
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0.6 |
0.8 |
%/§C |
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Output) Temperature Coefficient |
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ISOURCE |
Output Source Current |
VCC e 4.75V, VOUT e 1.75V, Tj e 150§C |
b1 |
b2 |
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mA |
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(Digit Output) |
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ISOURCE |
Output Source Current |
VCC e 5V, VOUT e 0V, Tj e 25§C |
b1.75 |
b3.3 |
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mA |
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(Carry-Out) |
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ISINK |
Output Sink Current |
VCC e 5V, VOUT e VCC, Tj e 25§C |
1.75 |
3.6 |
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mA |
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(All Outputs) |
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ijA |
Thermal Resistance |
MM74C925 |
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(Note 4) |
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75 |
100 |
§C/W |
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MM74C926, MM74C927, MM74C928 |
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70 |
90 |
§C/W |
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Note 1: ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits. The table of ``Electrical Characteristics'' provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-90.
Note 4: ijA measured in free-air with device soldered into printed circuit board.
2
AC Electrical Characteristics* TA e 25§C, CL e 50 pF, unless otherwise noted
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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fMAX |
Maximum Clock Frequency |
VCC e 5V, |
Tj e 25§C |
2 |
4 |
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MHz |
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Square Wave Clock |
Tj e 100§C |
1.5 |
3 |
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MHz |
tr, tf |
Maximum Clock Rise or Fall Time |
VCC e 5V |
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15 |
ms |
tWR |
Reset Pulse Width |
VCC e 5V |
Tj e 25§C |
250 |
100 |
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ns |
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Tj e 100§C |
320 |
125 |
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ns |
tWLE |
Latch Enable Pulse Width |
VCC e 5V |
Tj e 25§C |
250 |
100 |
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ns |
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Tj e 100§C |
320 |
125 |
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tSET(CK, LE) |
Clock to Latch Enable Set-Up Time |
VCC e 5V |
Tj e 25§C |
2500 |
1250 |
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ns |
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Tj e 100§C |
3200 |
1600 |
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ns |
tLR |
Latch Enable to Reset Wait Time |
VCC e 5V |
Tj e 25§C |
0 |
b100 |
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ns |
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Tj e 100§C |
0 |
b100 |
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ns |
tSET(R, LE) |
Reset to Latch Enable Set-Up Time |
VCC e 5V |
Tj e 25§C |
320 |
160 |
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ns |
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Tj e 100§C |
400 |
200 |
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ns |
fMUX |
Multiplexing Output Frequency |
VCC e 5V |
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1000 |
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Hz |
CIN |
Input Capacitance |
Any Input (Note 2) |
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5 |
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pF |
*AC Parameters are guaranteed by DC correlated testing.
Functional Description
Reset |
Ð Asynchronous, active high |
Display Select |
Ð High, displays output of counter |
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Low, displays output of latch |
Latch Enable |
Ð High, flow through condition |
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Low, latch condition |
Clock |
Ð Negative edge sensitive |
Segment Output Ð Current sourcing with 40 mA @VOUT e VCC b 1.6V (typ.) Also, sink capability e 2 LTTL loads
Digit Output |
Ð Current sourcing with 1 mA @VOUT e |
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1.75V. Also, sink capability e 2 LTTL |
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loads |
Carry-Out |
Ð 2 LTTL loads. See carry-out waveforms. |
Typical Performance Characteristics
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Typical Average Segment |
Typical Segment Current |
Maximum Power Dissipation |
Current vs Segment |
TL/F/5919 ± 3
Note: VD e Voltage across digit driver
3
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