Page 1
—1—
E92929D01
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage AVDD, DVDD 7V
•Input voltage (All pins)
VIN VDD+0.5 to VSS–0.5 V
• Output current (for each channel)
IOUT 0 to 30 mA
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25 V
DVDD, DVSS 4.75 to 5.25 V
• Reference input voltage
VREF 1.8 to 2.0 V
• Clock pulse width
TPW1,TPW0 9 ns (min.) to 1.1 µs (max.)
• Operating temperature
Topr –20 to +75 °C
Description
The CXD2308Q is a 10-bit high-speed D/A
converter for video band, featuring RGB 3-channel
I/O. This is ideal for use in high-definition TVs and
high-resolution displays.
Features
• Resolution 10-bit
• Maximum conversion speed 50MSPS
• RGB 3-channel I/O
• Differential linearity error ±0.5LSB
• Low power consumption 500 mW (Typ.)
• Single +5 V power supply
• Low glitch
• Stand-by function
Structure
Silicon gate CMOS IC
10-bit 50MSPS RGB 3-channel D/A Converter
64 pin QFP (Plastic)
CXD2308Q
Page 2
—2—
CXD2308Q
Block Diagram
4LSB'S
CURRENT
CELLS
6MSB'S
CURRENT
CELLS
CLOCK
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
4LSB'S
CURRENT
CELLS
6MSB'S
CURRENT
CELLS
CLOCK
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
4LSB'S
CURRENT
CELLS
6MSB'S
CURRENT
CELLS
CLOCK
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
DECODER
LATCHES
DECODER
DECODER
LATCHES
DECODER
DECODER
LATCHES
DECODER
ROG
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
31
32
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
(LSB) R0
R1
R2
R3
R4
R5
R6
R7
R8
(MSB) R9
(LSB) G0
G1
G2
G3
G4
G5
G6
G7
G8
(MSB)G9
(LSB) B0
B1
B2
B3
B4
B5
B6
B7
B8
BLK
CE
DV
DD
AVDD
AVDD
VGR
RO
RO
RCK
ROR
VRR
IRR
AV
DD
AVDD
VGG
GO
GO
GCK
ROG
VRG
IRG
AVDD
AVDD
VGB
BO
BO
BCK
ROB
VRB
IRB
VB
AV
SS
AVSS
DVSS
(MSB) B9
Page 3
—3—
CXD2308Q
Pin Configuration
52
53
54
55
56
57
58
59
60
63
64
61
62
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
4142
43
44
45
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
RO
RO
AV
DD
AVDD
GO
GO
AV
DD
AVDD
BO
BO
AV
DD
AVDD
DVDD
CE
BLK
B9 (MSB)
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
G9 (MSB)
AVss
VGB
ROB
VGG
ROG
VGR
ROR
VRB
VRG
VRR
IRB
IRG
IRR
AVss
VB
DVss
BCK
GCK
RCK
(LSB) R0
R1
R2
R3
R4
R5
R6
R7
R8
(MSB) R9
(LSB) G0
G1
G2
G3
G4
G5
G6
G7
G8
Pin Description and Equivalent Circuit
1 to 10
11 to 20
21 to 30
31
32
33
34
35
36
R0 to R9
G0 to G9
B0 to B9
BLK
CE
RCK
GCK
BCK
DVSS
I
—
Pin No. Symbol I/O Equivalent circuit Description
35
1
DVDD
DVSS
to
Digital input.
R0 (LSB) to R9 (MSB)
G0 (LSB) to G9 (MSB)
B0 (LSB) to B9 (MSB)
Blanking input.
This is synchronized with the clock
input signal for each channel.
No signal for High (0 V output).
Output generated for Low.
Chip enable input.
This is not synchronized with the clock
input signal.
No signal at for High (0 V output) to
minimize power consumption.
Clock inputs.
Digital ground.
Page 4
—4—
CXD2308Q
37
38, 51
45
47
49
46
48
50
39
40
41
42
43
44
VB
AVSS
ROR
ROG
ROB
VGR
VGG
VGB
IRR
IRG
IRB
VRR
VRG
VRB
—
O
I
O
I
Pin No. Symbol I/O Equivalent circuit Description
DVDD
DVSS
DVDD
37
42
44
45
46
49
50
AVSS
39
41
40
AVSS
48
AV
DD
AVDD
AVSS
AVDD
47
AVSS
AVDD
43
Connect to DVSS with a capacitor of
approximately 0.1 µF.
Analog grounds.
Connect to VGR, VGG, and VGB
with the control method of output
amplitude. See Application Circuit.
Connect a capacitor of approximately
0.1 µF.
Reference current output.
Connect to AVSS with a resistance of
1.2 kΩ.
Reference voltage input.
Set output full-scale value (2.0 V).
Page 5
—5—
CXD2308Q
52
56
60
53
57
61
54, 55, 58,
59, 62, 63
64
RO
GO
BO
RO
GO
BO
AVDD
DVDD
—
Pin No. Symbol I/O Equivalent circuit Description
52
53
60
61
AVDD
AVSS
AVDD
AVSS
56
57
Current output.
Output can be retrieved by
connecting a resistance of 75 Ω to
AVSS.
Reverse current output.
Normally connected to AVSS.
Analog VDD.
Digital VDD.
tPW1 tPW0
ts th ts th ts th
tPD
tPD tPD
CLK
DATA
D/A OUT
100%
50%
0%
1.5V
I/O Correspondence Table (output full-scale voltage: 2.00 V)
Input code Output voltage
MSB LSB
1 1 1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0 0 0
:
0 0 0 0 0 0 0 0 0 0
2.0 V
1.0 V
0 V
Description of Operation
Timing Chart
Page 6
—6—
CXD2308Q
Electrical Characteristics (FCLK=50 MHz, AVDD=DVDD=5 V, ROUT=75 Ω, VREF=2.0 V, Ta=25 °C)
Item
Resolution
Conversion speed
Integral non-linearity error
Differential non-linearity error
Precision guaranteed
output voltage range
Output full-scale voltage
Output full-scale ratio ∗1
Output full-scale current
Output offset voltage
Glitch energy
Crosstalk
Supply current
Analog input resistance
Input capacitance
Output capacitance
Digital input voltage
Digital input current
Setup time
Hold time
Propagation delay time
CE enable time ∗
2
CE disable time ∗
2
Symbol
n
FCLK
EL
ED
VOC
VFS
FSR
IFS
VOS
GE
CT
IDD
ISTB
RIN
CI
CO
VIH
VIL
IIH
IIL
ts
th
tPD
tE
tD
Measurement conditions
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
Endpoint
For the same gain
(See the Application Circuit)
When data “0000000000” input
When 1 kHz sine wave input
CE= “L”
CE= “H”
VGR, VGG, VGB,
VRR, VRG, VRB
RO, GO, BO
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
CE=H→L
CE=L→H
Min.
0.5
–2.0
–0.5
1.8
1.8
0
1
2.15
–5
7
3
Typ.
10
1.9
1.9
1.5
27
50
54
100
50
10
1
1
Max.
50
2.0
0.5
2.0
2.0
3
30
1
110
1
9
0.85
5
2
2
Unit
bit
MSPS
LSB
LSB
V
V
%
mA
mV
pV•s
dB
mA
MΩ
pF
pF
V
µA
ns
ns
ns
ms
ms
Full-scale voltage for each channel
∗1
Output full-scale ratio =
Full-scale voltage average value for each channel
–1 × 100 (%)
∗2
When the external capacitors for the VGR, VGG and VGB pins are 0.1 µF.
Electrical Characteristics Measurement Circuit
Analog Input Resistance
Measurement Circuit
Digital Input Current
CXD2308Q
+5.25V
AVDD, DVDD
AVSS, DVSS
V
A
}
Page 7
—7—
CXD2308Q
VGR to VGB
46, 48, 50
ROR to ROB
45, 47, 49
VRR to VRB
42 to 44
IRR to IRB
39 to 41
RCK
10 bit
COUNTER
WITH
LATCH
CLK
50MHZ
SQUARE
WAVE
GCK
BCK
0.1µ
DVss
75
AVss
75
AVss
75
AVss
1.2k
2V
0.1µ
AVDD
OSCILLO
SCOPE
BLK
CE
VB
RO
RO
GO
BO
BO
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
35
34
33
52
53
56
57
60
61
37
31
32
DELAY
CONTROLLER
DELAY
CONTROLLER
GO
Maximum Conversion Speed Measurement Circuit
VGR to VGB
46, 48, 50
ROR to ROB
45, 47, 49
VRR to VRB
42 to 44
IRR to IRB
39 to 41
RCK
10 bit
COUNTER
WITH
LATCH
CLK
50MHZ
SQUARE
WAVE
GCK
BCK
0.1µ
DVss
75
AVss
75
AVss
75
AVss
1.2k
2V
0.1µ
AVDD
OSCILLO
SCOPE
BLK
CE
VB
RO
RO
GO
BO
BO
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
35
34
33
52
53
56
57
60
61
37
31
32
GO
Setup Time
Hold Time Measurement Circuit
Glitch Energy
}
Cross Talk Measurement Circuit
VGR to VGB
46, 48, 50
ROR to ROB
45, 47, 49
VRR to VRB
42 to 44
IRR to IRB
39 to 41
RCK
CLK
50MHZ
SQUARE
WAVE
GCK
BCK
0.1µ
DVss
75
AVss
75
AVss
75
AVss
1.2k
2V
0.1µ
AV
DD
BLK
CE
VB
RO
RO
GO
BO
BO
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
35
34
33
52
53
56
57
60
61
37
31
32
DIGITAL
WAVEFORM
GENERATOR
ALL “1”
GO
SPECTRUM
ANALYZER
Page 8
—8—
CXD2308Q
VGR to VGB
46, 48, 50
ROR to ROB
45, 47, 49
VRR to VRB
42 to 44
IRR to IRB
39 to 41
RCK
CLK
50MHZ
SQUARE
WAVE
GCK
BCK
0.1µ
DVss
75
AVss
75
AVss
75
AVss
1.2k
2V
0.1µ
AVDD
BLK
CE
VB
RO
RO
GO
BO
BO
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
35
34
33
52
53
56
57
60
61
37
31
32
GO
FREQUENCY
DEMULTIPLIER
OSCILLO
SCOPE
DC Characteristics Measurement Circuit
VGR to VGB
46, 48, 50
ROR to ROB
45, 47, 49
VRR to VRB
42 to 44
IRR to IRB
39 to 41
RCK
CLK
50MHZ
SQUARE
WAVE
GCK
BCK
0.1µ
DVss
75
AVss
75
AVss
75
AVss
1.2k
2V
0.1µ
AVDD
BLK
CE
VB
RO
RO
GO
BO
BO
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
35
34
33
52
53
56
57
60
61
37
31
32
GO
CONTROLLER
DVM
Propagation Delay Time Measurement Circuit
Page 9
—9—
CXD2308Q
Application Circuit
(Gain equal)
AVDD
AVSS DVSS
R channel input G channel input
0.1µF
1.2kΩ
NCNC
1kΩ
NC NC
0.1µF
75Ω
75Ω
75Ω
52
53
54
55
56
57
58
59
60
63
64
61
62
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
Clock input
B channel input
DV
DD
ROUT
GOUT
BOUT
AVDD
AVSS
R channel input G channel input
0.1µF
1.2kΩ
1kΩ
0.1µF
75Ω
75Ω
75Ω
0.1µF 0.1µF
52
53
54
55
56
57
58
59
60
63
64
61
62
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
B channel input
Clock input
DV
DD
DVSS
ROUT
GOUT
BOUT
(Gain independently)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 10
—10—
CXD2308Q
Notes on Operation
• How to select the output resistance
The CXD2308Q is a D/A converter of the current output type. To obtain the output voltage connect the
resistance to RO, GO and BO pin. For specifications we have:
Output full scale voltage VFS=1.8 to 2.0 [V]
Output full scale current IFS=less than 30 [mA]
Calculate the output resistance value from the relation of VFS=IFS × ROUT. Also, 16 times resistance of the
output resistance is connected to reference current pin IRR, IRG and IRB. In some cases, however, this
turns out to be a value that does not actually exist. In such a case a value close to it can be used as a
substitute.
Here please note that VFS becomes VFS=VREF × 16ROUT/RIR. VREF is the voltage set at the VRR, VRG and
VRB pins and ROUT is the resistance connected to RO, GO and BO while RIR is connected to IRR, IRG and
IRB. Increasing the resistance value can curb power consumption. On the other hand glitch energy and
data settling time will inversely increase. Set the most suitable value according to the desired application.
• Phase relation between data and clock
To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation
between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and
hold time (tH) as stipulated in the Electrical Characteristics.
• Power supply and ground
To reduce noise effects separate analog and digital systems in the device periphery. For power supply pins,
both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as
possible to the pin.
• Latch up
Analog and digital power supply have to be common at the PCB power supply source. This is to prevent
latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON.
• RO, GO and BO pins
The RO, GO and BO pins are the inverted current output pins described in the Pin Description. The sums
shown below become the constant value for any input data.
a) The sum of the currents output from RO and RO
b) The sum of the currents output from GO and GO
c) The sum of the currents output from BO and BO
However, the performances such as the linearity error of the inverted current output pin output current is not
guaranteed.
• Output full-scale voltage
For the applications using the RGB signal, the color balance may be broken up when the no-adjusted output
full-scale voltage of RO, GO and BO are used.
Page 11
—11—
CXD2308Q
C
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD2308Q
C
DV
DD
DIGITAL IC
+5V
Latch Up Prevention
The CXD2308Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD and DVDD, when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
b. When analog and digital supplies are from a common source
(i)
(ii)
AVDD
+5V
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD2308Q
C
DV
DD
DIGITAL IC
C
+5V
AVSS
DVSS
AVSS DVSS
AVDD DVDD
CXD2308Q
C
DV
DD
DIGITAL IC
C
+5V
Page 12
—12—
CXD2308Q
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
b. When analog and digital supplies are from common source
(i)
(ii)
AVDD
+5V
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD2308Q
DV
DD
DIGITAL IC
C
+5V
C
C
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD2308Q
DVDD
DIGITAL IC
AVDD
C
+5V
+5V
AV
SS
DVSS
AVSS DVSS
AVDD DVDD
CXD2308Q
DV
DD
DIGITAL IC
AVDD
C
Page 13
—13—
CXD2308Q
Example of Representative Characteristics
Output frequency vs. Crosstalk
Output frequency F
O [HZ]
100k 1M 10M
Crosstalk CT [dB]
80
70
60
50
40
AVDD=DVDD=5.0V
FCLK=50MSPS
VREF=2.0V
Ta=25°C
ROUT=75Ω
RIR=1.2kΩ
Ambient temperature vs. Full-scale voltage
Full-scale voltage V
FS
[V]
1.9
1.8
–20 0 25 50 70
Ambient temperature Ta [°C]
Ambient temperature vs. Current consumption
Ambient temperature Ta [°C]
Current consumption I
DD
[mA]
100
–20 0 25 50 75
110
AVDD=DVDD=5.0V
FCLK=50MSPS
VREF=2.0V
ROUT=75
RIR=1.2k
Ω
Ω
AVDD=DVDD=5.0V
FCLK=50MSPS
VREF=2.0V
ROUT=75
RIR=1.2k
Ω
Ω
Page 14
Package Outline Unit : mm
CXD2308Q
—14—
SONY CODE
EIAJ CODE
JEDEC CODE
23.9 ± 0.4
20.0 – 0.1
0.4 – 0.1
+ 0.15
14.0 – 0.1
1
19
20
32
33
51
52
64
0.15 – 0.05
+ 0.1
2.75 – 0.15
16.3
0.1 – 0.05
+ 0.2
0.8 ± 0.2
M
0.2
0.15
+ 0.4
17.9 ± 0.4
+ 0.4
+ 0.35
64PIN QFP(PLASTIC)
QFP-64P-L01
QFP064-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
PACKAGE STRUCTURE
PLATING
1.5g
1.0
0° to10°
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