Page 1
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CXD2452R
E96830C9X
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2452R is a timing generator which generates
the timing pulses for performing progressive scan
readout for digital still cameras and personal
computer image input applications using the
ICX098AK CCD image sensor.
Features
• Base oscillation frequency 36.81MHz (2340fH)
• Monitoring readout allowed
• High-speed/low-speed electronic shutter function
• Horizontal driver for CCD image sensor
• Signal processor IC system clock generation 1170fH,
780fH
• Vertical/horizontal sync (SSG) timing generation
Applications
• Digital still cameras
• Personal computer image input
Structure
Silicon gate CMOS IC
Pin Configuration
Absolute Maximum Ratings
• Supply voltage VDD Vss – 0.5 to +7.0 V
• Input voltage VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
VDDa, VDDb, VDDc, VDDd 3.0 to 3.6 V
• Operating temperature
Topr –20 to +75 °C
Applicable CCD Image Sensors
ICX098AK (Type 1/4 CCD)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
48 pin LQFP (Plastic)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2627
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
OSCI
3MCK
V
SS
1
WEN
TEST
V
DD
1
XCLPOB
H1
V
SS
2
RG
V
DD
2
V
SS
5
CLD
FRI
HRI
HRO
FRO
EBCKSM
SEN
SSK
SSI
V
DD
6
RST
OSCO
XV1
V
DD7
XSUB
XV2
XSG2
XV3
V
SS6
MCK
DSGAT
H2
V
DD3
V
DD4
XSHP
XSHD
V
SS4
1/2MCK
ID
V
SS
3
XCLPDM
XRS
V
DD5
PBLK
XSG1
3/2MCK
*Groups of pins enclosed in the fingure indicate sections for which power supply separationis possible.
Page 2
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CXD2452R
Block Diagram
3
4
7
15
21
30
40
37
34
31
33
WEN
TEST
XCLPDM
XCLPOB
12
H1
9
RG
RST
FRI
HRI
HRO
FRO
EBCKSM
SEN
SSK
SSI
XSUB
DSGAT
13
H2
ID
17
18
19
XSHP
XSHD
XRS
PBLK
41
42
43
44
46
XV1
XV2
XSG2
XV3
XSG1
Latch
27
28
29
Latch
Latch
HRI
differential
1/2
1/3
1/2
1/390
1/525
SSG
32
5
Register
Pulse Generator
2
8
10
11
14
16
20
24
26
39
38
35
45
47
48
1
OSCI
3MCK
V
SS
CLD
V
DD
1/2MCK
OSCO
MCK
36
6
25
3/2MCK
23
1/2
22
Page 3
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CXD2452R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3MCK
Vss1
WEN
ID
TEST
VDD1
XCLPOB
VDD2
RG
Vss2
Vss3
H1
H2
VDD3
XCLPDM
VDD4
XSHP
XSHD
XRS
Vss4
PBLK
1/2MCK
3/2MCK
VDD5
RST
VDD6
SSI
SSK
SEN
EBCKSM
FRO
I
—
O
O
I
—
O
—
O
—
—
O
O
—
O
—
O
O
O
—
O
O
—
—
I
—
I
I
I
I
O
Internal main clock. (2340fH)
GND
Memory write timing.
Stop control possible using the serial interface data.
Vertical direction line identification pulse output.
Stop control possible using the serial interface data.
IC test pin; normally fixed to GND. (With pull-down resistor)
3.3V power supply. (Power supply for common logic block)
CCD optical black signal clamp pulse output.
Stop control possible using the serial interface data.
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output. (780fH)
GND
GND
CCD horizontal register drive clock output. (780fH)
CCD horizontal register drive clock output. (780fH)
3.3V power supply. (Power supply for H1/H2)
Pulse output for dummy bit block clamp .
3.3V power supply. (Power supply for CDS system)
Precharge level sample-and-hold pulse output. (780fH)
Data level sample-and-hold pulse output. (780fH)
Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH)
GND
Pulse output for horizontal and vertical blanking interval pulse cleaning.
Horizontal direction pixel identification pulse output.
Stop control possible using the serial interface data.
System clock output for signal processing IC (1170fH).
Stop control possible using the serial interface data.
3.3V power supply. (Power supply for common logic block)
Internal system reset input. High: Normal status, Low: Reset status
Always input one reset pulse after power-on.
3.3V power supply. (Power supply for common logic block)
Serial interface data input for internal mode settings.
Serial interface clock input for internal mode settings.
Serial interface strobe input for internal mode settings.
CHKSUM enable. (With pull-down resistor)
High: Sum check invalid, Low: Sum check valid
Vertical sync signal output.
Stop control possible using the serial interface data.
Symbol I/O Description
Page 4
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CXD2452R
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
HRO
HRI
FRI
CLD
VSS5
DSGAT
MCK
Vss6
XSUB
XV3
XSG2
XSG1
XV2
VDD7
XV1
OSCO
OSCI
O
I
I
O
—
I
O
—
O
O
O
O
O
—
O
O
I
Horizontal sync signal output.
Stop control possible using the serial interface data.
Horizontal sync signal input.
Vertical sync signal input.
Clock output for analog/digital conversion IC. (780fH)
Phase adjustment in 60° units possible using the serial interface data.
GND
Control input used to stop pulse generation for CCD image sensor, sample-and-
hold IC and analog/digital conversion IC. High: Normal status, Low: Stop status
Controlled pulse can be changed using the serial interface data.
System clock output for signal processor IC. (780fH)
GND
Pulse output for electronic shutter.
CCD vertical register drive pulse output.
CCD sensor readout pulse output.
CCD sensor readout pulse output.
CCD vertical register drive pulse output.
3.3V power supply. (Power supply for common logic block)
CCD vertical register drive pulse output.
Inverter output for oscillation.
Inverter input for oscillation.
Pin
No.
Symbol I/O Description
Page 5
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CXD2452R
Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item Pins
Symbol
Conditions Min. Typ. Max. Unit
∗1
These input pins do not have protective diodes on the internal power supply side.
∗2
These input pins have internal pull-down resistors.
∗3
The above table indicates the condition for 3.3V drive.
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Input voltage 1
∗1
Input
voltage 2
∗1 ∗2
Input
voltage 3
∗2
Output
voltage 1
Output
voltage 2
Output
voltage 3
Output
voltage 4
Output
voltage 5
Output
voltage 6
Output
voltage 7
VDD2
VDD3
VDD4
VDD1, VDD5,
VDD6, VDD7
RST, DSGAT,
SSI, SSK, SEN,
FRI, HRI
EBCKSM
TEST
RG
H1, H2
XSHP, XSHD,
XRS, PBLK,
XCLPDM
3/2MCK, MCK,
CLD
1/2MCK
XV1, XV2, XV3,
XSUB, XSG1,
XSG2, XCLPOB,
ID, WEN
FRO, HRO
VDDa
VDDb
VDDc
VDDd
VIH1
VIL1
VIH2
VIL2
VIH3
VIL3
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VOH5
VOL5
VOH6
VOL6
VOH7
VOL7
3.0
3.0
3.0
3.0
0.8VDDd
0.8VDDd
0.7VDDd
VDDa– 0.8
VDDb – 0.8
VDDc– 0.8
VDDd– 0.8
VDDd– 0.8
VDDd– 0.8
VDDd– 0.8
3.3
3.3
3.3
3.3
3.6
3.6
3.6
3.6
0.2VDDd
0.2VDDd
0.3VDDd
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.6mA
Pull-in current where IOL = 7.2mA
Page 6
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CXD2452R
Inverter I/O Characteristics for Oscillation
(Within the recommended operating conditions)
Logical Vth
Input voltage
Output voltage
Feedback resistor
Oscillation frequency
OSCI
OSCI
OSCO
OSCI, OSCO
OSCI, OSCO
LVth
VIH
VIL
VOH
VOL
RFB
f
0.7VDDd
VDDd/2
500k
20
VDDd/2
2M
0.3VDDd
VDDd/2
5M
50
V
V
V
V
V
Ω
MHz
Feed current where
IOH = –6.0mA
Pull-in current where
IOL = 6.0mA
VIN = VDDd or Vss
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Logical Vth
Input voltage
Input amplitude
3MCK
LVth
VIH
VIL
VIN
0.7VDDd
0.3
VDDd/2
0.3VDDd
V
V
V
Vp-p
fmax 50MHz sine
wave
∗1
Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is
the input amplitude characteristics in the case of input through capacitor.
Item Pins Symbol Conditions Min. Typ. Max. Unit
Item Pins Symbol Conditions Min. Typ. Max. Unit
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CXD2452R
AC Characteristics
1) AC characteristics between the serial interface clocks
0.8VDDd
0.8VDDd
0.2V
DDd
0.2V
DDd
0.2V
DDd
0.8V
DDd
th1ts1
th2ts2
ts3
SSI
SSK
SEN
SEN
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
th2
ts3
SSI setup time, activated by the rising edge of SSK
SSI hold time, activated by the rising edge of SSK
SSK setup time, activated by the rising edge of SEN
SSK hold time, activated by the rising edge of SEN
SEN setup time, activated by the rising edge of SSK
20
20
20
20
20
ns
ns
ns
ns
ns
Definition Min. Typ. Max. Unit
2) Serial interface clock internal loading characteristics
0.2VDDd
0.8VDDd
th4
ts4
HRI
XSG1
SEN
0.2VDDd
FRI
HRI
XSG1
Enlarged view
Example: During recording drive mode
Note) Be sure to maintain a constantly high SEN logic level near the HRI fall immediately before XSG1
generation.
Symbol
ts4
th4
SEN setup time, activated by the falling edge of HRI
SEN hold time, activated by the falling edge of HRI
0
0
ns
ns
Definition Min. Typ. Max. Unit
(Within the recommended operating conditions)
Page 8
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CXD2452R
(Within the recommended operating conditions)
Symbol
tpdPULSE
Output signal delay, activated by the rising edge of SEN
5
100
ns
Definition Min. Typ. Max. Unit
5) Phase identification characteristics using FRI and HRI input
0.2VDDd
FRI
HRI
tpd1
The field is identified as an ODD field .
0.2VDDd
FRI
HRI
tpd1
The field is identified as an EVEN field .
When the HRI logic level is low tpd1 after the
falling edge of FRI
When the HRI logic level is high tpd1 after the
falling edge of FRI
(Within the recommended operating conditions)
Symbol
tpd1
Field identification clock phase, activated by the falling edge of FRI
1100
1300
ns
Definition Min. Typ. Max. Unit
4) RST loading characteristics
0.8VDDd
tw1
0.2V
DDd
RST
(Within the recommended operating conditions)
Symbol
tw1
RST pulse width
35
ns
Definition Min. Typ. Max. Unit
3) Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2452R at the timing shown in 2) above. However, one
exception to this is when the data such as SSGSEL and STB is loaded to the CXD2452R and controlled at the
rising edge of SEN. For STB, see control data D62 to D63 STB in “Description of Operation”.
0.8VDDd
tpdPULSE
SEN
Output signal
Page 9
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CXD2452R
7) Output timing characteristics using DSGAT
tpDSGAT
0.2VDDd
0.2VDDd
DSGAT
H1, H2, RG, XV1, XV2, XV3, XSUB, XSG1, XSG2,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB, CLD
H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF, XV1, XV2, XV3, XSG1, XSG2, XSUB,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB and CLD load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpDSGAT
Time until the above outputs go low after the fall of DSGAT
100
ns
Definition Min. Typ. Max. Unit
6) FRI and HRI loading characteristics
FRI, HRI
MCK
0.8V
DDd
th5ts5
0.8VDDd
0.8V
DDd
MCK load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts5
th5
FRI and HRI setup time, activated by the rising edge of MCK
FRI and HRI hold time, activated by the rising edge of MCK
10
0
ns
ns
Definition Miin. Typ. Min. Unit
8) Output variation characteristics
MCK
WEN, ID
0.8V
DDd
tpd2
Symbol
tpd2
Time until the above outputs change after the rise of MCK
20
40
ns
Definition Miin. Typ. Min. Unit
WEN and ID load capacitance = 10pF
(Within the recommended operating conditions)
Page 10
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CXD2452R
9) H1 and RG waveform characteristics
0.9VDDb
0.1VDDb
0.9VDDb
0.1VDDb
tfH1trH1
0.9V
DDa
0.1VDDa
trRG
0.9VDDa
0.1VDDa
tfRG
RG
H1
VDDb = 3.3V, Topr = 25°C, H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF
(Within the recommended operating conditions)
Symbol
trH1
tfH1
trRG
tfRG
H1 rise time
H1 fall time
RG rise time
RG fall time
10
10
3
3
ns
ns
ns
ns
Definition Min. Typ. Max. Unit
10) I/O pin capacitance
Symbol
CIN
COUT
CI/O
Input pin capacitance
Output pin capacitance
I/O pin capacitance
9
11
11
pF
pF
pF
Definition Min. Typ. Max. Unit
(Within the recommended operating conditions)
Page 11
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CXD2452R
The CXD2452R basically loads and reflects the serial interface data sent in the above format in the readout
portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which XSG1
rises.
There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these
data are distinguished by referring to the former as control data and the latter as adjustment data.
An example of the initialization data for the CXD2452R control data is shown below. This data is based on the
Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin
initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the
3/2 MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71
CHKSUM is valid.
Description of Operation
All pulses output from the CXD2452R are controlled by the RST and DSGAT pins and by the serial interface
data shown below. The details of control by the serial interface data and a description of operation are as
follows.
00 01 02 03 04 05 06 07 08 09 10 11 58 59 60 61 62 63 64 65 66 67 68 69 70 71SSI
SSK
SEN
MSB LSB
D71 D70 D69 D68 D67 D66 D65 D64 D63 D62 D61 D60 D59 D58 D57 D56
MSB LSB
D55 D54 D53 D52 D51 D50 D49 D48 D47 D46 D45 D44 D43 D42 D41 D40
MSB LSB
D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24
MSB LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08
MSB LSB
D07 D06 D05 D04 D03 D02 D01 D00
1 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1
The adjustment data does not normally need to be set. However, when adjustment is difficult due to the
system configuration or for other reasons, the data considered most appropriate at that time should be set as
the initialization data.
Page 12
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CXD2452R
Data
D00
to
D07
D08
to
D15
D16
to
D17
D18
to
D25
D26
to
D35
D36
to
D47
D48
D49
to
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
to
D61
D62
to
D63
D64
to
D71
CHIP
CTGRY
SMD
Shut.FRM
Shut.HD
—
EXPOSE
—
PSMT
SSGSEL
WENSEL
CLPSEL
IDSEL
HMCKSEL
TMCKSEL
HMCKREV
TMCKREV
DSG
STB
CHKSUM
Chip switching
Category switching
Electronic shutter mode setting
Electronic shutter vertical interval
setting
Electronic shutter horizontal interval
setting
—
Recording exposure setting switching
—
Drive mode switching
Internal SSG operation switching
WEN pulse operation switching
XCLPOB pulse operation switching
ID pulse operation switching
1/2MCK pulse operation switching
3/2MCK pulse operation switching
1/2MCK pulse reset polarity switching
2/3MCK pulse reset polarity switching
Pulse generation control
IC pin status control
Check sum bit
See D00 to D07 CHIP.
See D08 to D15 CTGRY.
See D16 to D35
Electronic shutter mode.
See D16 to D35
Electronic shutter mode.
See D16 to D35
Electronic shutter mode.
All 0
All 0
All 0
All 0
All 0
All 0
0
All 0
0
0
0
0
0
0
0
0
0
All 0
All 0
All 0
Symbol Function Data = 0 Data = 1
When a reset
—
OFF
—
Monitoring
OFF
ON
OFF
OFF
OFF
ON
Positive polarity
Negative polarity
—
ON
—
Recording
ON
OFF
ON
ON
ON
OFF
Negative polarity
Positive polarity
See D60 to D61 DSG table.
See D62 to D63 STB table.
See D64 to D71 CHKSUM.
Control Data
Page 13
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CXD2452R
Detailed Description of Each Data
D00 to D07 CHIP
The serial interface data is loaded to the CXD2452R when D00 and D07 are 1. However, this assumes that
either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high.
D08 to D15 CTGRY
Of the data provided to the CXD2452R by the serial interface, the CXD2452R loads D16 and subsequent data
to the control register side when D08 is 0, and to the adjustment register side when D08 is 1. However, this
assumes that the CXD2452R is selected by CHIP and that either the EBCKSM pin is low and D64 to D71
CHKSUM is satisfied or the EBCKSM pin is high.
MSB LSB
D07 D06 D05 D04 D03 D02 D01 D00
1 0 0 0 0 0 0 1
Function
Loading to the CXD2452R
MSB LSB
D15 D14 D13 D12 D11 D10 D09 D08
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
Function
Loading to the control register side
Loading to the adjustment register side
D16 to D35 Electronic shutter mode
The CXD2452R's electronic shutter mode can be switched as follows by SMD D16 to D17 . Handling of the
data from D18 to D35 differs according to the mode, and is explained in detail below.
D17 D16 Description of operation
XSUB stopped mode
High-speed/low-speed shutter mode
HTSG control mode
0
1
1
X
0
1
The electronic shutter data is expressed as shown in the table below using Shut.HD as an example.
MSB LSB
D35 D34 D33 D32 D31 D30 D29 D28 D27 D26
0 1 1 1 0 0 0 0 1 1
↓ ↓ ↓
1 C 3
[XSUB stopped mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is 1/60s during monitoring drive
mode, and 1/30s during recording drive mode.
Shut.HD is expressed as 1C3h .
Note that when SEN is shared with other ICs and indentification is performed using CHIP-ID, the CXD2452R
data must be positioned immeditately before the load timing, that is to say at the very end.
Note that the CXD2452R cannot apply both categories simultaneously during the same vertical interval. Also,
care should be taken as the data is overwritten even if the same category is applied.
Page 14
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CXD2452R
The CXD2452R does not distinguish between the high-speed shutter and low-speed shutter modes. The
interval during which Shut.FRM and Shut.HD are specified together is the shutter speed. At this time,
Shut.FRM controls the XSG1, XSG2 output, and Shut.HD controls the XSUB output. Concretely, when
specifying high-speed shutter, Shut.FRM is set to 00h. (See the figure.) During low-speed shutter, or in other
words when Shut.FRM is set to 01h or higher, the serial interface data is not loaded until this interval is
finished.
However, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode
is monitoring drive mode and 1/30s units during recording drive mode.
For monitoring drive mode, care should be taken that shut.HD value is offset. This is because the same
exposure time can be obtained for the same shut.HD data without depending on drive mode basically for highspeed shutter.
Formula for calculating the electronic shutter speed: [Shut.FRM/Shut.HD] (unit: µs)
Monitoring drive mode:
T = Shut.FRM∗1.66834∗104+ {(20Ch – Shut.HD)∗780 + 447} ∗81.5∗10–3(107h ≤ Shut.HD ≤ 20Ch)
Shut.FRM
01 01 01
Shut.HD-106h
00h 01h 00h
1A6h
1DDh 1A6hShut. HD
WEN
SMD
Shut. FRM
XSUB
FRI
XSG1
During monitoring drive mode/low-speed shutter mode
Shut.FRM
01
Shut.HD
01h
01
00h
1A6h
1DDhShut. HD
WEN
SMD
Shut. FRM
XSUB
FRI
XSG1
During recording drive mode/low-speed shutter mode
Recording drive mode:
T = Shut.FRM∗3.33667∗104+ {(20Ch – Shut.HD)∗780 + 447} ∗81.5∗10–3(000h ≤ Shut.HD ≤ 20Ch)
[High-speed/low-speed shutter mode]
During this mode, the data has the following meanings.
Symbol Data Description
Shutter speed data (number of vertical intervals) specification
Shutter speed data (number of horizontal intervals) specification
D18 to D25
D26 to D35
Shut.FRM
Shut.HD
Page 15
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CXD2452R
Shut.FRM
00h
00h
00h
00h
00h
00h
00h
00h
00h
20Ch
20Bh
209h
205h
1FDh
1EDh
1CEh
18Fh
16Fh
1/27000
1/10000
1/4500
1/2000
1/1000
1/500
1/250
1/125
1/100
1/27450
1/10000
1/4403
1/2077
1/1010
1/498
1/251
1/125
1/100
00h
01h
01h
02h
07h
09h
00h
00h
00h
107h
∗1
20Ch
1D8h
20Ch
18Bh
109h
0D2h
083h
000h
1/60
1/60
∗2
1/50
∗2
1/30
∗2
1/8
∗2
1/6
∗2
1/50
∗3
1/40
∗3
1/30
∗3
1/60
1/60
1/50
1/30
1/8
1/6
1/50
1/40
1/30
Shut.HD
Calculation
results (s)
Shutter speed
(s)
Shut.FRM
Calculation
results (s)
Shutter speed
(s)
Shut.HD
Electronic shutter speed table [Shut.FRM/Shut.HD]
∗1
One XSUB pulse is generated for odd fields and two for even fields.
∗2
These are the settings during monitoring drive mode.
∗3
These can only be specified during recording drive mode.
Note) Input prohibited data:
Monitoring drive mode 000h to 106h
Recording drive mode and monitoring drive mode 20Dh to 3FFh
[HTSG control mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical interval to the vertical period during which XSG1 (and
XSG2) is stopped as shown in the figure.
XSUB
FRI
XSG1
WEN
01 11 01SMD
Vck
During HTSG control mode
Page 16
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CXD2452R
D51 PSMT
0: Driving is controlled in accordance with monitoring drive mode under the assumption that vertical/horizontal sync
signals are input.
1: Driving is controlled in accordance with recording drive mode under the assumption that vertical/horizontal sync
signals are input.
See the timing charts for the vertical/horizontal sync signals in accordance with each mode.
Note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be
cleaned.
Concretely, this operation is supported by generating XSUB, but the CXD2452R facilitates this control by
using D48 EXPOSE. (See the figure.)
FRI
XSG1
WEN
00 00SMD
XSUB
0000
0 0EXPOSE
10
1 0PSMT
00
Recording Monitoring
Monitoring
Exposure time
Mode
Monitoring
Image of switching from monitoring drive mode to recording drive mode
D52 SSGSEL
0: Internal SSG functions are stopped.
1: Internal SSG functions operate, and FRO and HRO are generated.
When generation is stopped, these pulses are fixed low.
D53 WENSEL
0: WEN is generated.
1: WEN generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
D48 EXPOSE
0: No operation
1: XSUB for recording exposure is generated.
This control specification is such that one XSUB pulse is always generated during the horizontal interval
immediately following the readout portion even if the electronic shutter speed is set to 1/60s (SMD = 00). This
mode is closely related to D51 PSMT, so see D51 regarding the control.
Page 17
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CXD2452R
No control performed
CCD pulse control
Sample-and-hold and analog/digital conversion IC pulse control
CCD pulse and sample-and-hold and analog/digital conversion IC pulse control
D60 to D61 DSG
The CXD2452R can stop control to the CCD pulses and pulses for the sample-and-hold and analog/digital
conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the controlled
pulses can be switched as follows using the serial interface data.
D61 D60 Operating mode
0
1
0
1
0
0
1
1
Here, CCD pulses refer to the H1, H2, RG, XV1, XV2, XV3, XSUB, XSG1 and XSG2 pulses. Sample-and-hold
and analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD
pulses.
See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each
pulse.
D54 CLPSEL
0: XCPOB generation is stopped.
1: XCPOB is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D55 IDSEL
0: ID generation is stopped.
1: ID is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D56 HMCKSEL
0: 1/2MCK generation is stopped.
1: 1/2MCK is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D57 TMCKSEL
0: 3/2MCK is generated.
1: 3/2MCK generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
D58 HMCKREV
0: 1/2MCK reset when positive polarity.
1: 1/2MCK reset when negative polarity.
D59 HMCKREV
0: 3/2MCK reset when negative polarity.
1: 3/2MCK reset when positive polarity.
Page 18
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CXD2452R
D62 to D63 STB
This switches the operating mode as shown below. However, the IC pin status control bit is loaded to the
CXD2452R and controlled immediately at the rise of the SEN input.
Normal operation mode
Sleep mode
∗1
Standby mode
D63 D62 Symbol
0
1
1
X
0
1
CAMERA
SLEEP
STNBY
Operating mode
∗1
Mode for the status which does not require CCD drive when playing back recorded data within the system.
The pin status during each mode is shown in the table below.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
3MCK
Vss1
WEN
ID
TEST
VDD1
XCLPOB
VDD2
RG
Vss2
Vss3
H1
H2
VDD3
XCLPDM
VDD4
XSHP
XSHD
XRS
Vss4
PBLK
1/2MCK
3/2MCK
VDD5
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
—
L
L
—
—
L
—
L
—
—
L
L
—
L
—
L
L
L
—
L
L
ACT
—
ACT
L
L
L
L
L
L
L
L
L
L
L
L
L
Symbol
CAMERA SLEEP
STNBY
Note) ACT means that the circuit is operating. L indicates a low output level in the controlled status.
Pin
Symbol
CAMERA
SLEEP
STNBY
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RST
VDD6
SSI
SSK
SEN
EBCKSM
FRO
HRO
HRI
FRI
CLD
VSS5
DSGAT
MCK
Vss6
XSUB
XV3
XSG2
XSG1
XV2
VDD7
XV1
OSCO
OSCI
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
—
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
—
ACT
ACT
—
L
L
L
L
L
—
L
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
L
ACT
ACT
L
ACT
L
L
L
L
L
L
L
ACT
ACT
Page 19
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CXD2452R
D64 to D71 CHKSUM
This is the check sum bit. Apply the data shown below.
MSB LSB
D07 D06 D05 D04 D03 D02 D01 D00
D15 D14 D13 D12 D11 D10 D09 D08
D23 D22 D21 D20 D19 D18 D17 D16
D31 D30 D29 D28 D27 D26 D25 D24
D39 D38 D37 D36 D35 D34 D33 D32
D47 D46 D45 D44 D43 D42 D41 D40
D55 D54 D53 D52 D51 D50 D49 D48
D63 D62 D61 D60 D59 D58 D57 D56
+) D71 D70 D69 D68 D67 D66 D65 D64 → CHKSUM
0 0 0 0 0 0 0 0 → Reflected when the total is 0.
Page 20
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CXD2452R
FRI
HRI
XSG1
XSG2
XSUB
XV1
XV2
XV3
CCD OUT
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 490491492493494 1 2 1 2 3 4 5 6 7 8 1
PBLK
XCLPOB
XCLPDM
WEN
ID
∗
The number of XSUB pulses is determined by the serial interface data. This chart shows the case where Shut.HD = 20Ch and XSUB pulses are generated over the entire horizontal interval.
∗
In addition to the phase relationship between FRI and HRI shown above, the phases may also be offset by 1/2 horizontal interval. In any case, the readout interval is the 9th HRI fall counted
from the fall of FRI.
∗
Note that R and B of CCDOUT indicate lines containing these components, and do not mean the lead pixel component of that line.
525 1 525 1
R R R RB B B B
R RB B B
R
Chart-1 Vertical Direction Timing Chart
MODE (Base oscillation frequency: 2340fH)
Recording drive mode
Applicable CCD image sensor
ICX098AK
Page 21
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CXD2452R
FRI
HRI
XSG1
XSG2
XSUB
XV1
XV2
XV3
CCD OUT
1 2 5 6 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 466469470473474 1 2 5 6 1 2 5 6 9 10 13 14
PBLK
XCLPOB
XCLPDM
WEN
ID
∗
The number of XSUB pulses is determined by the serial interface data. This chart shows the case where Shut.HD = 20Ch and XSUB pulses are generated over the entire horizontal interval.
∗
Note that R and B of CCDOUT indicate lines containing these component, and do not mean the lead pixel component of that line.
525 1 262
482485486489490493494 481482485486489477478 494490493
B B B BR R R R R R R R R R RB B B B B B B R B R R RB B BB B B B B B B BR R R R R R R
Chart-2 Vertical Direction Timing Chart
MODE (Base oscillation frequency: 2340fH)
Monitoring drive mode
Applicable CCD image sensor
ICX098AK
Page 22
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CXD2452R
∗
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗
The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
∗
The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗
XSUB is output at the timing shown above when specified by the serial interface data.
∗
The ID transition timing is synchronized with the fall of XV3.
∗
WEN is output during the horizontal interval shown in Chart-1. The transition timing is the same as that for ID.
∗
R, G and B of H1 indicate the output pixel color. In addition to the lines starting from R and G shown above, there are also lines starting from G and B.
0 50 100 550
HRI
MCK
H1
XV1
XV2
XV3
XSG1
XSG2
XSUB
RG
PBLK
XCLPOB
XCLPDM
ID
WEN
44 80
56 92
68 104
10481
129
129118
44
21 40
68
68
43 116
GGGGG
B B BB B B B B B
GGGG G
G
R
G
R R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R R
Chart-3 Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH)
Recording drive mode
Applicable CCD image sensor
ICX098AK
Page 23
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CXD2452R
0 50 100 550
HRI
MCK
H1
XV1
XV2
XV3
XSG1
XSG2
XSUB
RG
PBLK
XCLPOB
XCLPDM
ID
WEN
44 80
56 92
68 104
10481
129118
21 40
68
68
43 116
∗
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗
The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
∗
The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗
XSUB is output at the timing shown above when specified by the serial interface data.
∗
The ID transition timing is synchronized with the fall of XV3. ID is reset low at this timing during the readout horizontal interval.
∗
WEN is output during the horizontal interval shown in Chart-1. The transition timing is the same as that for ID.
116 521
520
551
520
551
Chart-4 Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH)
Recording drive mode (readout portion)
Applicable CCD image sensor
ICX098AK
Page 24
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CXD2452R
∗
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗
The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
∗
The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗
XSUB is output at the timing shown above when specified by the serial interface data.
∗
The ID transition timing is synchronized with the fall of XV3.
∗
WEN is output during the horizontal interval shown in Chart-2. The transition timing is the same as that for ID.
∗
R, G and B of H1 indicate the output pixel color. In addition to the lines starting from R and G shown above, there are also lines starting from G and B.
XV1
XV2
XV3
XSG1
XSG2
XSUB
RG
PBLK
XCLPOB
XCLPDM
ID
WEN
44 80
50
68
58 110
10481
129
129118
44
21 40
92
92
62 98
86
104
74 92
0 50 100 550
HRI
MCK
H1
43 116
GGGGG
B B BB B B B B B
GGGG G
G
R
G
R R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R R
Chart-5 Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH)
Monitoring drive mode
Applicable CCD image sensor
ICX098AK
Page 25
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CXD2452R
0 50 100 550
HRI
MCK
H1
XV1
XV2
XV3
XSG1
XSG2
XSUB
RG
PBLK
XCLPOB
XCLPDM
ID
WEN
44 80
50
68
58 110
10481
129118
21 40
92
92
43 116
∗
The HRI of this chart is equivalent to HRI' of Chart-7. This HRI indicates a timing that the CXD2452R takes in actually.
∗
The numbers at the output pulse transition points indicate the count at the MCK (780fH) rise from the fall of HRI.
∗
The HRI fall interval should be between 3.6 to 9.4µs. This chart shows an interval of 78ck (6.3µs).
∗
XSUB is output at the timing shown above when specified by the serial interface data.
∗
The ID transition timing is synchronized with the fall of XV3. ID is reset low at this timing during the readout horizontal interval.
∗
WEN is output during the horizontal interval shown in Chart-2. The transition timing is the same as that for ID.
62 98
86 104
74 92
116
521
551520
Chart-6 Horizontal Direction Timing Chart
MODE (Base oscillation frequency: 2340fH)
Monitoring drive mode (readout portion)
Applicable CCD image sensor
ICX098AK
Page 26
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CXD2452R
HRI
HRI'
∗
The phase relationship of each pulse indicates logical position. For actual output waveform, delay is added respectively.
∗
HRI' indicates the HRI, which is a timing that taken in actually.
∗
3/2MCK and 1/2MCK can inverse polarity according to each serial interface data. This chart indicates that 3/2 MCK is negative polarity; 1/2 MCK is positive polarity.
3MCK
3/2MCK
1/2MCK
CLD
MCK
H1
H2
RG
XSHP
XSHD
XRS
43 116
1
1 43
116
Chart-7 High-speed Phase Timing Chart
MODE (Base oscillation frequency: 2340fH)
Applicable CCD image sensor
ICX098AK
Page 27
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CXD2452R
Application Circuit Block Diagram
5
17
18
19
21
15
35
23
22
4
3
38
34
33
32
31
29
28
27
30
37
25
48
47
1
46
44
41
43
42
40
CLD
ID
1/2MCK
WEN
MCK
FRI
HRI
HRO
FRO
XSHP
XCLPOB
XCLPDM
PBLK
XRS
XSHD
V-Dr
CXD1267AN
XV1
XV3
XSG1
XSG2
XSUB
VSUB
V3
V2b
V2a
V1
12
13
9
H1
H2
RG
CCD
ICX098AK
CCD OUT
DRV OUT
VRT
VRB
A/D
CXD2311AR
D0 to 9
10
TG
CXD2452R
SSG
EBCKSM
TEST
DSGAT
RST
OSCI
OSCO
3MCK
Controller
SEN
SSK
SSI
XV2
7
3/2MCK
S/H
CXA2006Q
Signal Processing Block
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Note) When the CXD2311AR is used as A/D converter, CLD must be inversed.
Page 28
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CXD2452R
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗ 7.0 ± 0.1
1
12
13
24
25
36
37
48
(0.22)
0.18 – 0.03
+ 0.08
0.2g
LQFP-48P-L01
LQFP048-P-0707
(8.0)
0.5 ± 0.2
0.127 – 0.02
+ 0.05
A
1.5 – 0.1
+ 0.2
0.1
SOLDER/PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
DETAIL A
0.13
M
0.5
S
S
B
DETAIL B:SOLDER
(0.18)
(0.127)
DETAIL B:PALLADIUM
0.127 ± 0.04
0.18 – 0.03
+ 0.08
0.127 – 0.02
+0.05
0.18 ± 0.03
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