Datasheet CXD1812R, CXD1812Q Datasheet (Sony)

ATAPI I/F CD-ROM DECODER

For the availability of this product, please contact the sales office.

CXD1812Q/R

Description

The CXD1812Q/R is a CD-ROM decoder LSI with

a built-in ATAPI I/F.

Features

• Compatible with CD-ROM, CD-I and CD-ROM XA

formats

• Real time error correction

• Automatic multi-block transfer function

• Readable Subcode-Q data by byte from the Sub

CPU

• Capable of transferring up to double speed
playback and Mode2 when the 33.8688 MHz clock
is used
Transfer in Mode3 is possible when the decoder is
OFF (The transfer speed depends on playback
speed and clock frequency.)

• Supports PIO/single-word DMA/multiword DMA
data transfer mode

• IORDY support available

• Automatic reception of PACKET commands

CXD1812Q

100 pin QFP (Plastic)

CXD1812R

100 pin LQFP (Plastic)

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD –0.5 to +7.0 V

• Input voltage VI –0.5 to VDD +0.5 V

• Output voltage VO –0.5 to VDD +0.5 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage VDD 4.5 to 5.5 (+5.0 typ.) V

• Operating temperature Topr –20 to +75 °C

Applications

CD-ROM drives

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95233-ST

CXD1812Q/R

DD

V

XRST

MDB0 to 7

XMWR
XCAS

XRAS

HDB0 to F

69to72

95

3, 28, 53, 7843 to 46, 48 to 51

DMA FIFO

42
41
39

74to77

DMA

SEQUENCER

80to83

85to88

ATAPI REGISTERs

12 bytes PACKET FIFO

PRIORITY

RESOLVER

HCS0, 1

55

56

HA0 to 2

575860

XHRD

66

XHWR
67

HDRQ

XHAC

68

63

HOST I/F

HINT
62

XS16
61

REDY
64

XPDI

DASP

52

59

subCPU I/F

HRST
89

XINT

6

XWR

8

XRD

9

XCS

7

17 to 21, 23 to 25 10 to 14, 16

A0 to 5

D0 to 7

MA0 to 9

ADDRESS GEN

26, 27, 30 to 33, 35 to 38

4

1522293440475465737984

GND

Block Diagram -1 CXD1812Q (QFP)

90

DESCRAMBLER

SYNC CONTROL

2

1

100

BCLK

C2PO

MDAT

– 2 –

MAIN DATA

ERROR CORECTION

I/F

CD•DSP

5

96

LRCK

EXCK

97

SBIN

Subcode S/P

98

99

SCOR

WFCK

93

94

92

CLOCK GENERATOR

91

MCLK

HCLK

XTL1

XTL2

CXD1812Q/R

DD

XRST

V

XMWR
XCAS
XRAS

MDB0 to 7

HDB0 to F

67to70

93

1, 26, 51, 76

DMA FIFO

41 to 44, 46 to 49

40

39

37

72to75

DMA

SEQUENCER

78to81

83to86

ATAPI REGISTERs

12 bytes PACKET FIFO

PRIORITY

RESOLVER

HCS0, 1

53

54

HA0 to 2

555658

XHRD
64

XHWR
65

HDRQ

XHAC
61

66

HOST I/F

HINT
60

XS16
59

REDY
62

XPDI

DASP
50

57

subCPU I/F

HRST
87

XINT

4

XWR

6

XRD

7

XCS

5

15 to 19, 21 to 23 8 to 12, 14

A0 to 5

D0 to 7

MA0 to 9

ADDRESS GEN

24, 25, 28 to 31, 33 to 36

2

1320273238455263717782

GND

Block Diagram -2 CXD1812R (LQFP)

88

DESCRAMBLER

SYNC CONTROL

98

99

100

BCLK

C2PO

MDAT

– 3 –

MAIN DATA

ERROR CORECTION

I/F

CD•DSP

3

94

LRCK

EXCK

95

SBIN

Subcode S/P

96

97

SCOR

WFCK

91

92

90

CLOCK GENERATOR

89

MCLK

HCLK

XTL1

XTL2

Pin Description

CXD1812Q/R

Pin No.

QFP

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

LQFP

99

100

1
2
3
4
5
6
7
8

9
10
11
12
13

Symbol

BCLK
MDAT
VDD
GND
LRCK
XINT
XCS
XWR
XRD
A5
A4
A3
A2
A1
GND

I/O Description

I

Bit clock signal from CD DSP

I

Data signal from CD DSP

—

Power supply

—

Ground

I

LR clock signal from CD DSP

O

Interrupt request signal to CPU

I

Chip select negative logic signal from CPU

I

Strobe negative logic signal for writing data from CPU

I

Strobe negative logic signal for reading data from CPU

I

CPU address (MSB)

I

CPU address

I

CPU address

I

CPU address

I

CPU address

—

Ground
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

A0
D7
D6
D5
D4
D3
GND
D2
D1
D0
MA0
MA1
VDD
GND
MA2
MA3
MA4

I

CPU address (LSB)

I/O

CPU data bus (MSB)

I/O

CPU data bus

I/O

CPU data bus

I/O

CPU data bus

I/O

CPU data bus

—

Ground

I/O

CPU data bus

I/O

CPU data bus

I/O

CPU data bus (LSB)

O

DRAM address (LSB)

O

DRAM address

—

Power supply

—

Ground

O

DRAM address

O

DRAM address

O

DRAM address
33
34
35
36

31
32
33
34

MA5
GND
MA6
MA7

O

DRAM address

—

Ground

O

DRAM address

O

DRAM address

– 4 –

CXD1812Q/R

Pin No.

QFP

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

LQFP

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

Symbol

MA8
MA9
XRAS
GND
XCAS
XMWR
MDB0
MDB1
MDB2
MDB3
GND
MDB4
MDB5
MDB6
MDB7

I/O Description

O

DRAM address

O

DRAM address (MSB)

O

DRAM row address strobe negative logic signal

—

Ground

O

DRAM column address strobe negative logic signal

O

DRAM write enable negative logic signal

I/O

DRAM data bus (LSB)

I/O

DRAM data bus

I/O

DRAM data bus

I/O

DRAM data bus

—

Ground

I/O

DRAM data bus

I/O

DRAM data bus

I/O

DRAM data bus

I/O

DRAM data bus (MSB)
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

DASP
VDD
GND
HCS1
HCS0
HA2
HA0
XPDI
HA1
XS16
HINT
XHAC
REDY
GND
XHRD
XHWR
HDRQ

I/O

Drive active/slave present negative logic signal; open drain output

—

Power supply

—

Ground

I

Chip select negative logic signal from host

I

Chip select negative logic signal from host

I

Host address (MSB)

I

Host address (LSB)

I/O

Passed diagnostics negative logic signal; open drain output

I

Host address

O

16-bit I/O port select negative logic signal; open drain output

O

Interrupt request positive logic signal to host

I

DMA acknowledge negative logic signal from host

O

I/O channel ready positive logic signal; open drain output

—

Ground

I

Strobe negative logic signal for reading data from host

I

Strobe negative logic signal for writing data from host

O

DMA request positive logic signal to host
69
70
71
72

67
68
69
70

HDBF
HDB0
HDBE
HDB1

I/O

Host data bus (MSB)

I/O

Host data bus (LSB)

I/O

Host data bus

I/O

Host data bus

– 5 –

CXD1812Q/R

Pin NO.

QFP

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87

LQFP

71
72
73
74
75
76
77
78
79
80
81
82
83
84
85

Symbol

GND
HDBD
HDB2
HDBC
HDB3
VDD
GND
HDBB
HDB4
HDBA
HDB5
GND
HDB9
HDB6
HDB8

I/O Description

—

Ground

I/O

Host data bus

I/O

Host data bus

I/O

Host data bus

I/O

Host data bus

—

Power supply

—

Ground

I/O

Host data bus

I/O

Host data bus

I/O

Host data bus

I/O

Host data bus

—

Ground

I/O

Host data bus

I/O

Host data bus

I/O

Host data bus
88
89
90
91
92
93
94
95
96
97
98
99

100

86
87
88
89
90
91
92
93
94
95
96
97
98

HDB7
HRST
GND
XTL2
XTL1
MCLK
HCLK
XRST
EXCK
SBIN
SCOR
WFCK
C2PO

I/O

Host data bus

I

Chip reset negative logic signal from host

—

Ground

O

Crystal oscillation circuit output

I

Crystal oscillation circuit input

O

Master clock (XTL1) output

O

Clock output with 1/2 the frequency of XTL1

I

Chip reset negative logic signal

O

Subcode data read clock signal to CD DSP

I

Subcode data serial input signal from CD DSP

I

Subcode sync positive logic signal from CD DSP

I

Write frame clock signal from CD DSP

I

C2 pointer positive logic signal from CD DSP

– 6 –

CXD1812Q/R

Electrical Characteristics

1. DC Characteristics (VDD = 5V ±10%, VSS = 0V, Topr = –20 to +75°C)

Item Symbol Conditions Min. Typ. Max. Unit
High level input voltage (1)
Low level input voltage (1)
High level input voltage (2)
Low level input voltage (2)
High level input voltage (3)
Low level input voltage (3)
TTL Schmitt hysteresis
High level input voltage (4)
Low level input voltage (4)
CMOS Schmitt hysteresis
High level output voltage (6)
Low level output voltage (6)
High level output voltage (7)
Low level output voltage (7)
High level output voltage (8)
Low level output voltage (8)
Input leakage current
Input leakage current

∗1

VIH1
VIL1
VIH2
VIL2
Vt1+
Vt1–
Vt1+ – Vt1–
Vt2+
Vt2–
Vt2+ – Vt2–
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
IIL1
IIL2

IOH1 = –2mA
IOL1 = 4mA
IOH2 = –6mA
IOL2 = 12mA
IOH3 = –6mA
IOL3 = 4mA

2.2

0.7VDD

2.2

0.8VDD

VDD – 0.8

VDD – 0.8

VDD – 0.8

–10
–40

0.4

0.6

0.8

0.3VDD

0.8

0.2VDD

0.4

0.4

0.4
10
40

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
µA
µA

Input current of pull-up input
Input current of pull-up input

∗1

Output leakage current (9) (10)
Oscillation cell logic threshold value
Oscillation cell high level input voltage
Oscillation cell low level input voltage
Oscillation cell feedback resistance
Oscillation cell high level output voltage
Oscillation cell low level output voltage

∗1

Bidirectional pin

IIL3
IIL4
IIZ
LVth
VIH
VIL
RFB
VOH
VOL

VIN = 0V
VIN = 0V
High-impedance state

VIN = VSS or VDD
IOH = –12mA
IOL = 12mA

–40
–90
–40

0.7VDD

250k

0.5VDD

–100
–200

0.5VDD

1M

–240
–440

40

0.3VDD

2.5M

0.5VDD

µA
µA
µA

V

V

V

Ω

V

V

– 7 –

1-1. Categories of input pins

(1) TTL input level pin:

D0 to D7, MDB0 to MDB7, HDB0 to HDBF, DASP, XPDI

(2) CMOS input level pin:

MDAT, LRCK, SBIN, SCOR, WFCK, C2PO

(3) TTL Schmitt input level pin:

XCS, XWR, XRD, A0 to A5, HA0 to HA2, XHAC, XHRD, XHWR, HCS0 to HCS1, HRST

(4) CMOS Schmitt input level pin:

BCLK, XRST

(5) Input pin with pull-up resistor:

D0 to D7, MDB0 to MDB7, HCS0 to HCS1, HRST

1-2. Categories of output pins

(6) Normal output pin:

D0 to D7, MDB0 to MDB7, XINT, MA0 to MA9, XMWR, MCLK, HCLK, EXCK

(7) Powered output pin:

HINT, HDRQ, HDB0 to HDBF, DASP, XPDI, XS16, REDY

(8) Proportional output pin:

XRAS, XCAS

(9) Tristate output pin:

XINT, HINT, HDRQ

(10) Open drain output pin:

DASP, XPDI, XS16, REDY

CXD1812Q/R

1-3. Bidirectional pins

D0 to D7, MDB0 to MDB7, HDB0 to HDBF, DASP, XPDI

1-4. Oscillation cell

Input: XTL1
Output: XTL2

1-5. I/O Capacitance (VDD = VI = 0V, f = 1MHz)

Item Symbol Min. Typ. Max. Unit
Input capacitance
Output capacitance
I/O capacitance

CIN
COUT
CI/O

9
11
11

pF
pF
pF

– 8 –

2. AC Characteristics (VDD = 5V ±10%, VSS = 0V, Topr = –20 to +75°C, Output Load = 50pF)

2-1. CPU Interface

(1) Read

A0 to A5

XCS

Trdw

CXD1812Q/R

(2) Write

XRD

D0 to D7

A0 to A5

XCS

XWR

D0 to D7

Tas

Tas

Tdd

Twwr

Tds

Tah

Tdf

Tah

Tdh

Item Symbol Min. Typ. Max. Unit
Address setup time (for XCS & XRD/XWR ↓)
Address hold time (for XCS & XRD/XWR ↑)
XRD pulse width
Data delay time (for XCS & XRD ↓)
Data float time (for XCS & XRD ↑)
XWR pulse width
Address setup time (for XCS & XWR ↑)
Address hold time (for XCS & XWR ↑)

– 9 –

Tas
Tah
Trdw
Tdd
Tdf
Twwr
Tds
Tdh

43

21

0
0

ns
ns
ns

43

1

ns
ns

ns
7
0

ns

ns

2-2. DRAM Interface

(1) Read

XRAS

XCAS

Tasr

CXD1812Q/R

Tras Trp

Trcd Tcas Tpc

Tasc

(2) Write

MA0 to MA9

MDB0 to 7

XMWR

XRAS

XCAS

MA0 to MA9

MDB0 to 7

XMWR

Tasr

row

Trah

row

Trah

col

Trcd Tcas Tpc

col

Tids Tidh

col

Tcah

high

Tras Trp

Tasc

col

Tdos Tdof

col

Tcah

rowcol

row

Item Symbol Min. Typ. Max. Unit
RAS pulse width
RAS precharge width
RAS – CAS delay time
CAS pulse width
Page mode cycle time
Row address setup time (for RAS ↓)
Row address hold time (for RAS ↓)
Column address setup time (for CAS ↓)
Column address hold time (for CAS ↓)
Input data setup time (for CAS ↑)
Input data hold time (for CAS ↑)
Data output setup time (for CAS ↓)
Data output float time (for CAS ↓)

– 10 –

Tras
Trp
Trcd
Tcas
Tpc
Tasr
Trah
Tasc
Tcah
Tids
Tidh
Tdos
Tdof

3Tw

Tw – 7

Tw

Tw – 14

Tw + 2

7
0
0

Tw + 3

2Tw
2Tw

Tw

2Tw

(Tw = 1/f)

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2-3. HOST Interface

(1) PIO

HCS0, 1
HA0 to 2

XS16

CXD1812Q/R

Txsl

Trww

XHRD

XHWR

HDB0 to F

REDY

Tas

Tdd

Trel Trel

Item Symbol Min. Typ. Max. Unit
Address setup time (for XHRD/XHWR ↓)
Address hold time (for XHRD/XHWR ↑)
XHRD/XHWR pulse width
Data delay time (for XHRD ↓)
Data float time (for XHRD ↑)
Data setup time (for XHWR ↑)

Tah Tas Trww Tah

Tdf

Tas
Tah
Trww

Tds Tdh

20

5

50
Tdd
Tdf
Tds

5

20

26
21

ns
ns
ns
ns
ns

ns
Data hold time (for XHWR ↑)
XS16 fall time (for Address valid)
REDY fall time (for XHRD/XHWR ↓)

– 11 –

Tdh
Txsl
Trel

5

8

14

ns

ns

ns

(2) Single-word DMA

CXD1812Q/R

HDRQ

XHAC

XHRD/
XHWR

HDB0 to F
(READ)

HDB0 to F
(WRITE)

(3) Multiword DMA

HDRQ

XHAC

Trql

Tacs Trww Tach

Tdd

Tdf

TdhTds

Trql

TachTrwwThpwTrwwTacs

XHRD/
XHWR

Tdd

HDB0 to F
(READ)

HDB0 to F
(WRITE)

Item Symbol Min. Typ. Max. Unit
HDRQ fall time (for XHAC/XHRD/XHWR ↓)
XHRD/XHWR Low pulse width
Data delay time (for XHRD ↓)
Data float time (for XHRD ↑)
Data setup time (for XHWR ↑)
Data hold time (for XHWR ↑)
XHAC setup time (for XHRD/XHWR ↓)

Tdf

Tdd Tdf

TdhTds

Tds Tdh

(Tw = 1/f)

Trql
Trww
Tdd
Tdf
Tds
Tdh
Tacs

50

5

20

5
0

Tw +11

26
19

ns
ns
ns
ns
ns
ns

ns
XHAC hold time (for XHRD/XHWR ↑)
XHRD/XHWR high pulse width

– 12 –

Tach
Thpw

0

25

ns

ns

2-4. CD DSP Interface

(1) BCKRED = "H"

BCLK

MDAT

LRCK
C2PO

(2) BCKRED = "L"

CXD1812Q/R

Tbck Tbck

Tsb1 Thb1

Tsb2 Thb2

BCLK

MDAT

LRCK
C2PO

Item Symbol Min. Typ. Max. Unit
BCLK frequency
BCLK pulse width
MDAT setup time (for BCLK)
MDAT hold time (for BCLK)
LRCK, C2PO setup time (for BCLK)

Tbck Tbck

Tsb1 Thb1

Tsb2 Thb2

Fbck
Tbck
Tsb1
Thb1
Tsb2

25
12
12
12

20 MHz

ns
ns
ns
ns

LRCK, C2PO hold time (for BCLK)

– 13 –

Thb2

12

ns

2-5. Subcode Interface

CXD1812Q/R

Subcode Frame

WFCK

SCOR

SBIN

EXCK

EXCK

SF97 SF0 SF1 SF2 SF3

Twed

Teck Teck

SBIN

Item Symbol Min. Typ. Max. Unit
WFCK – EXCK delay time
EXCK pulse width
SBIN setup time (for EXCK ↑)
SBIN hold time (for EXCK ↑)

a = 48: When EXCKSL (CONFIG0 register bit 3) = High
a = 32: When EXCKSL (CONFIG0 register bit 3) = Low

Tds Tdh

Twed
Teck
Tds
Tdh

2aTw

1/2aTw – 2

12
12

(Tw = 1/f)

3aTw ns

ns
ns
ns

– 14 –

CXD1812Q/R

2-6. XTL1 and XTL2 Pins

(1) When using self-excited oscillation

Item Symbol Min. Typ. Max. Unit

Oscillation frequency f 33.8688 40 MHz

(2) When inputting a pulse to the XTL1 pin

Tw

Twhx Twlx

Vihx

DD/2

V

High level pulse width
Low level pulse width
Pulse cycle

Vilx

Item Symbol Min. Typ. Max. Unit

Twhx
Twlx
Tw

10
10

29

ns
ns
ns

– 15 –

CXD1812Q/R

Description of Functions

1. Pin Description

The pin description by function is given below.

1-1. CD player interface (8 pins)

This enables direct connection with the Sony's digital signal processor LSI for CD players. Digital signal
processor LSI for CD applications are hereafter called "CD DSP."
(1) MDAT (medium data: input)

Serial data stream from CD DSP.

(2) BCLK (bit clock: input)

Bit clock signal; MDAT signal strobe.

(3) LRCK (LR clock: input)

LR clock signal; indicates left and right channels of MDAT signals.

(4) C2PO (C2 pointer: input)

C2 pointer signal; indicates that an error is contained in MDAT input.

(5) WFCK (write frame clock: input)

Write frame clock input signal.

(6) SCOR (subcode sync OR: input)

Subcode sync signal.

(7) SBIN (subcode serial input: input)

Subcode serial signal.

(8) EXCK (external clock: output)

Clock output for reading SBIN signals.

1-2. Buffer memory interface (21 pins)

This can be connected with up to a 512K-byte DRAM (4M bits).
(1) XMWR (DRAM write enable: output)

DRAM write enable negative logic output signal.

(2) XCAS (column address strobe: output)

Negative logic output signal to indicate that column addresses are valid.

(3) XRAS (row address strobe: output)

Negative logic output signal to indicate that row addresses are valid.

(4) MA0 to MA9 (DRAM address: output)

DRAM address output.

(5) MDB0 to MDB7 (DRAM data bus: input/output)

DRAM data bus signal; pulled up by a standard 25kΩ resistor.

1-3. Sub CPU interface (18 pins)

(1) XWR (sub CPU write: input)

Strobe negative logic signal for writing internal registers.

(2) XRD (sub CPU read: input)

Strobe negative logic signal for reading internal registers status.

(3) D0 to D7 (sub CPU data bus: input/output)

8-bit data bus; pulled up by a standard 25kΩ resistor.

(4) A0 to A5 (sub CPU address: input)

Address signal for selecting internal registers from sub CPU.

(5) XINT (sub CPU interrupt: output)

Interrupt request signal to sub CPU. Polarity can be controlled by sub CPU.

(6) XCS (chip select: input)

Chip select negative logic signal from sub CPU.

– 16 –

1-4. HOST interface (31 pins)

(1) HCS0 (host chip select: input)

Chip select negative logic signal from host; pulled up by a standard 50kΩ resistor. This is connected with
the CS1FX pin of ATAPI I/F.

(2) HCS1 (host chip select: input)

Chip select negative logic signal from host; pulled up by a standard 50kΩ resistor. This is connected with
the CS3FX pin of ATAPI I/F.

(3) HA0 to HA2 (host address: input)

Address signal for selecting internal registers from host.

(4) DASP (drive active/slave present: input/output)

Negative logic signal to indicate that slave drive is present or drive is active; open drain signal.

(5) HDB0 to HDBF (host data bus: input/output)

16-bit host data bus signal.

(6) XHRD (host read: input)

Data read strobe negative logic signal from host.

(7) XHWR (host write: input)

Data write strobe negative logic signal from host.

(8) XHAC (host DMA acknowledge: input)

DMA data request acknowledge negative logic signal from host.

(9) HDRQ (host DMA request: output)

DMA data request positive logic signal to host; tristate output.

(10) HINT (host interrupt: output)

Interrupt request positive logic signal to host; tristate output.

(11) XS16 (16-bit data transfer: output)

Negative logic signal to indicate that the 16-bit data port has been selected; open drain signal. This is
connected with the IOCS16 pin of ATAPI I/F.

(12) REDY (I/O channel ready: output)

Positive logic signal to be negated when the drive is not ready to respond to a data transfer reguest; open
drain signal. This is connected with the IORDY pin of ATAPI I/F.

(13) XPDI (passed diagnostics: input/output)

Negative logic signal that indicates diagnostics of the slave drive has been completed; open drain signal.
This is connected with the PDIAG pin of ATAPI I/F.

(14) HRST (host reset: input)

Reset negative logic signal from host; pulled up by a standard 50kΩ resistor.

CXD1812Q/R

1-5. Others (5 pins)

(1) XRST (reset: input)

Chip reset negative logic input signal.
(2) XTL1 (crystal 1: input)
(3) XTL2 (crystal 2: output)

A crystal oscillator is connected between XTL1 and XTL2. (The capacitor value depends on the crystal

oscillator.)
(4) MCLK (clock: output)

Outputs a clock signal of the same frequency as that of XTL1. The output can be set at low when this

clock signal is not used.
(5) HCLK (half clock: output)

Outputs a clock signal with 1/2 the frequency of XTL1. The output can be set at low when this signal is

not used.

1-6. Power supply (17 pins)

VDD: 4 pins, GND: 13 pins.

– 17 –

2. Sub CPU Write Registers

Normally set at low for reserved registers and bits.

2-1. CONFIG0 (configuration 0) register (address 00HEX)

bit 7: CINTPOL (sub CPU interrupt polarity)

High: The XINT pin becomes high-active. When the register is inactive, the low state is

established.

Low: The XINT pin becomes low-active. When the register is inactive, high impedance is

established.

bit 6: M/S SEL (master/slave select)

This bit is valid only when M/S EN (bit 5) is high.
High: Set this bit high when a slave drive is used.
Low: Set this bit low when a master drive is used.

bit 5: M/S EN (master/slave mode enable)

Set this bit as follows according to the number of drives connected to ATAPI I/F.
High: Set this bit high when two drives are connected to ATAPI I/F. One is used as the master

drive and the other is the slave drive.

Low: Set this bit low when only one drive is connected to ATAPI I/F.
bit 4: RESERVED
bit 3: EXCKSL (EXCK select)

The frequency of EXCK clock signal for picking up subcodes from CD DSP is determined by this

bit. The sub CPU sets this register according to the clock frequency and the playback speed of the

XTL1 pin. (Max. frequency of EXCK clock signal is 1MHz.)

High: The EXCK frequency is 1/48 the frequency of XTL1. When the frequency of the XTL1 pin is

more than 32MHz, this bit is set high.

Low: The EXCK frequency is determined to be 1/32 the frequency of XTL1. When the frequency

of the XTL1 pin is not more than 32MHz, this bit is set low.

bit 2: DISMCLK (disable MCLK output)

High: The MCLK pin is fixed at low.

Low: The clock signal of the same frequency as that of the XTL1 pin is output from the MCLK pin.
bit 1: DISHCLK (disable HCLK output)

High: HCLK pin is fixed at low.

Low: The frequency divider clock signal of half the frequency of XTL1 pin is output from HCLK pin.
bit 0: RAMSIZE (RAM size)

High: When a 4M-bit DRAM is connected, set this bit high.

Low: When a DRAM of up to 2M bits is connected, set this bit low.

CXD1812Q/R

2-2. CONFIG1 (configuration 1) register (address 01HEX)

bit 7: SWOPEN (sync window open)

High: A window for Sync mark detection is opened. In this case, the internal Sync protection circuit

is disabled.

Low: A window for Sync mark detection is controlled by the internal Sync protection circuit.
bit 6 to 4: SYCNGC2 to 0 (sync NG count 2 to 0)

Set "010" for these bits.
bit 3: RESERVED

– 18 –

bit 2, 1: RFRSCTL1, 0 (refresh control 1, 0)

The refresh interval of the DRAM can be controlled by these bits. Set these bits according to the

clock frequency of XTL1. The refresh interval is designed as 512 cycle/8ms.

RFRSCTL1 RFRSCTL0

CXD1812Q/R

"L"
"L"
"H"
"H"

"L"

"H"

"L"

"H"

XTL1 frequency: less than 24MHz
XTL1 frequency: 24MHz or more
XTL1 frequency: 32MHz or more
XTL1 frequency: 33.8688MHz or more

bit0 RESERVED

2-3. LSTARA (last area) register (address 02HEX)

The last area is assigned by this register.
The following table shows the set values of LASTARA when the buffer memory is fully used.

ENBYTFBT RAM size

"L"

LASTARAHEX

0C

32KB

"H"
"L"

0A

19

64KB

"H"
"L"

16
34

128KB

"H"

2E

"L"

69

256KB

"H"
"L"

5E
D3

512KB

"H"

BD

2-4. LHADR (last HADRC) register (address 03HEX)

Assigns the upper limit (upper 8 bits) of HADRC when the automatic transfer mode to the host is disabled, or
the upper limit (upper 8 bits) of the address when the row subcode buffering command is executed. The lower
11 bits are assigned to 7FFHEX.

2-5. DRVIF (drive interface) register (address 04HEX)

This register controls the connection mode with the CD DSP. After the IC is reset, the sub CPU sets this
register according to the CD DSP to be connected.
Any change of each bit in this register must be made in the decoder disable status. (After the IC is reset, the
address is set 28HEX.)
Figs. 1-1 and 1-2 are input timing charts for Sony's typical CD DSP.

– 19 –

CXD1812Q/R

L0L1L2L3L4L5L6L7L8L9L10L11L12L13L14L15

R15R14R13R12R11R10R9R8R7R6R5R4R3R2R1R0L14

Lch LSBLch MSBRch LSB

C2 Pointer for Lower byte

LRCK

123456789101112131415161718192021222324

BCLK

R0R1

MDAT

Fig. 1-1. CDL40 and 50 Series Timing Chart (48-bit slot mode)

C2 Pointer for Upper byte

C2PO

– 20 –

LRCK

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

BCLK

L15

MDAT

Fig. 1-2. CDL40 and 50 Series Timing Chart (64-bit slot mode)

C2 Pointer for Upper byte C2 Pointer for Lower byte

Lch MSB Rch LSB Rch MSB

C2PO

bit 7: C2PL1ST (C2PO lower byte first)

High: When 2 bytes of MDAT are input, C2PO inputs the lower byte first followed by the upper

byte.
Low: When 2 bytes of MDAT are input, C2PO inputs the upper byte first followed by the lower byte.
Here, "upper byte" means the upper 8 bits including MSB from the CD DSP and "lower byte"
means the lower 8 bits including LSB from the CD DSP. For example, the Header minute byte is
the lower byte and the second byte, the upper byte.

bit 6: LCHLOW (Lch low)

High: When LRCK is low, determined to be the left channel data.
Low: When LRCK is high, determined to be the left channel data.

bit 5: BCKRED (BCLK rising edge)

High: MDAT is strobed at the rising edge of BCLK.
Low: MDAT is strobed at the falling edge of BCLK.

bit 4, 3: BCKMD1, 0 (BCLK mode 1, 0)

These bits are set according to the number of clocks output for BCLK during one WCLK cycle by
the CD DSP.

CXD1812Q/R

BCKMD1 BCKMD0

"L"

"L"

"H"

"L"
"H"
"X"

16BCLKs/WCLK
24BCLKs/WCLK
32BCLKs/WCLK

bit 2: LSB1ST (LSB first)

High: Connected with the CD DSP which outputs MDAT with LSB first.
Low: Connected with the CD DSP which outputs MDAT with MSB first.

bit 1, 0: RESERVED

2-6. XFRFMT0 (transfer format 0) register (address 05HEX)

The transfer format for automatic data transfer is determined by this register. This IC transfers the buffer
memory data to the host according to the Mode/Form value written by SCTINF register (address 1EHEX) into
the internal RAM by sector and the values of XFRFMT1 and 0 registers.
The Mode/Form of bits 3 to 1 depends on the values of bits 2 and 1 of SCTINF register.
Regarding Mode 2 in Yellow Book, don't care the Form2 (bit 2) of SCTINF register.
Set bits 3 to 1 of XFRFMT0 register high to transfer 2336 bytes of user data.

bit 7, 6: RESERVED
bit 5: SYNC

High: The Sync mark is transferred to the host.
Low: The Sync mark is not transferred to the host.

bit 4: HEADER

High: The Header's 4 bytes are transferred to the host.
Low: The Header's 4 bytes are not transferred to the host.

bit 3: SUBHEADER

High: Mode1: This bit has no meaning.

Mode 2: The Sub Header's 8 bytes are transferred to the host.

Low: The bytes above are not transferred to the host.

– 21 –

bit 2: USERDATA (user data)

High: Mode1 and Mode2/Form1: User data (2048 bytes) are transferred to the host.

Mode2/Form2: User data (2324 bytes) are transferred to the host.

Low: The bytes above are not transferred to the host.

bit 1: PARITY

High: Mode1: The EDC, ECC parity and eight 00HEX bytes, for a total of 288 bytes, are

transferred to the host.
Mode2/Form1: The EDC and ECC parity (280 bytes) are transferred to the host.
Mode2/Form2: RESERVED bytes (4 bytes) (the final ones in the sector concerned) are
transferred to the host.

Low: The bytes above are not transferred to the host.

bit 0: RESERVED

Regarding CD-DA data, set bits 5 to 1 high.

2-7. XFRFMT1 (transfer format 1) register (address 06HEX)

bit 7: ENBLKEFL (enable block error flag)

High: Block error flag (1 byte + 00HEX) is transferred to the host.

Here, block error flag means operating OR by bit of the byte error flag.

Low: The bytes above are not transferred to the host.
bit 6: RESERVED
bit 5: ENBYTFBT (enable byte error flag buffering and transfer)

When this bit is set high, the following operations are performed. When this bit is set low, the

following operations are not performed. This bit is valid only when the USERDATA bit (bit 2) of

XFRFMT0 register is set high.

(1) When write-only, real-time correction, or CD-DA command is being executed, byte error flag is

buffered.

(2) When the automatic transfer mode to the host is enabled (that is, the AUTOXFR bit of XFRCTL

register (bit 7) is high), byte error flag is transferred to the host.
bit 4: RESERVED
bit 3: ENSBCBT (enable subcode buffering and transfer)

When this bit is set high, the following operations are performed. When this bit is set low, the
following operations are not performed.
(1) When CD-DA command is being executed, all the subcodes or the subcode-Q are buffered.
(2) When the automatic transfer mode to the host is enabled (that is, the AUTOXFR bit of XFRCTL

register (bit 7) is high), all the subcodes or the subcode-Q are transferred to the host.
bit 2: ALLSBC (all subcodes/subcode-Q)

When ENSBCBT is set high, whether all the subcodes or the subcode-Q are to be buffered or
transferred to the host is determined.
High: All the subcodes

Low: Subcode-Q
bit 1: RESERVED
bit 0: ZASUBQ (zero after sub-Q)

This bit is valid only when ENSBCBT is high and ALLSBC is low.

High: 6-byte 00HEX in addition to the subcode-Q are transferred to the host.

Low: 2-byte CRC and 4-byte 00HEX in addition to the subcode-Q are transferred to the host.

CXD1812Q/R

– 22 –

2-8. DECCTL0 (decoder control 0) register (address 07HEX)

bit 7: AUTODIST (auto distinction)

High: Errors are corrected according to the Mode byte and the Form bit read by the drive.

Low: Errors are corrected according to the MODESEL and FORMSEL bits (bits 6 and 5).
bit 6: MODESEL (mode select)
bit 5: FORMSEL (form select)

When AUTODIST is set low, the sector is corrected in the Mode or Form indicated below.

MODESEL FORMSEL

CXD1812Q/R

"L"
"H"
"H"

"L"
"L"

"H"

MODE1
MODE2, FORM1
MODE2, FORM2

bit 4: RESERVED
bit 3: ENFM2EDC (enable form 2 EDC check)

High: EDC check for Form2 is enabled.
Low: EDC check for Form2 is disabled. The EDCNG bit of DECSTS0 register is set low.

bit 2: MDBYTCTL (mode byte control)

High: Even if there are data other than 0 in the upper 6 bits of the Header's Mode byte, it is not

determined to be an error. Set this bit high when a CD-DA command is executed or the disc
such as CD-R is played back.

Low: If the upper 6 bits of the Header's Mode byte are not "000000," it is determined to be an

error.

bit 1: ENDLA (enable drive last area (address))

High: DLAR (drive last area)/SLADR (subcode last address) is enabled. When buffering of the

buffer memory area assigned by DLAR is completed while the decoder is executing the
write-only, real-time correction, or CD-DA command, the DRVOVRN (drive over run) status
is established. When buffering to the address assigned by SLADR is completed while the
subcode buffering command is being executed, the DRVOVRN status is established. In the
DRVOVRN status,data writing into the buffer is stopped.

Low: DLAR (drive last area)/SLADR (subcode last address) is disabled.

bit 0: ATDLRNEW (Auto DLARA renewal)

High: When the data transfer to host is completed for one sector, DLARA is renewed in the written

area of the sector.

Low: Renewal of DLARA is executed by the sub CPU.

– 23 –

2-9. DECCTL1 (decoder control 1) register (address 08HEX)

bit 7: ENSBQRD (enable subcode-Q read)

CRC of subcode-Q is checked by taking in the subcode from DSP. Sub CPU can read subcode-Q

data from the SUBQ register.
bit 6: RESERVED
bit 5 to 3: DECCMD2 to 0 (decoder commands 2 to 0)

CXD1812Q/R

DECCMD2 DECCMD1 Decoder command

"L"
"L"
"L"

"L"
"H"
"H"

"L"

"L"
"H"
"H"

"L"
"H"

DECCMD0

"L"

"H"

"L"
"H"
"H"
"H"

Decoder disable
Monitor only
Write only
Real-time correction
Raw subcode buffer
CD-DA

bit 2 to 0: RESERVED

2-10. XFRMOD (transfer mode) register (address 09HEX)

bit 7: ENHINTCT (enable auto HINT upon start of packet command transfer)

High: When packet command transfer starts, there is an interrupt request to the host.
Low: When the transfer above starts, there is no interrupt request to the host.

bit 6: ENHINTDT (enable auto HINT upon start of data transfer)

High: When data transfer with the host starts, there is an interrupt request to the host.
Low: When the transfer above starts, there is no interrupt request to the host.

bit 5: ENMDMA (enable multiword DMA)

This bit is valid for DMA transfer.
High: DMA transfer is executed in the multiword mode.

Low: DMA transfer is executed in the single-word mode.
bit 4: ENDMABIT (enable ATAPI feature register DMA bit)
bit 3: PIOSEL (PIO transfer mode select)

Transfer mode is determined as shown below from the combination of these bits and the DMA bit

(bit 0) of ATAPI feature register.

PIOSEL ENDMABIT Transfer Mode

"H"

"L"
"L"
"L"

"X"
"H"
"H"

"L"

bit 2: AUTOWAIT (enable auto wait state)

This bit is valid for PIO transfer.
High: In the cases below, the REDY pin is set low and a wait is automatically applied to the host.

Transfer to host: When the host asserts the XHRD signal while the data FIFO is empty.
Transfer from host: When the host asserts the XHWR signal while the data FIFO is full.

Low: The wait state above does not occur.

DMA

"X"

"H"

"L"
"X"

PIO

DMA

PIO

DMA

– 24 –

bit 1, 0: WAITCYCL1, 0

These bits are valid for PIO transfer.
If the host asserts XHRD/XHWR during data transfer, the REDY pin is set low by the cycle number
set with these bits, and a wait is applied. One cycle is XTL1 cycle.
00: Wait state does not occur.
01: Wait state of 4 to 8 cycles occurs.
10: Wait state of 8 to 12 cycles occurs.
11: Wait state of 12 to 16 cycles occurs.

2-11. XFRCTL0 (transfer control 0) register (address 0AHEX)

bit 7: AUTOXFR (auto transfer)

High: The automatic transfer mode to the host described later is enabled.
Low: The automatic transfer mode to the host above is disabled. Transfer to the host is executed

by setting HADRC and HXFRC.
bit 6 to 4: RESERVED
bit 3: CPUDMAEN (sub CPU DMA enable)

The buffer memory access by sub CPU is enabled by setting this bit high. The sub CPU sets this
bit high after the head addresses of buffer access have been set on the CADRC.

bit 2: CPUSRC (sub CPU source)

High: Data are transferred from sub CPU to buffer memory.
Low: Data are transferred from buffer memory to sub CPU.

bit 1 to 0: RESERVED

CXD1812Q/R

2-12. XFRCTL1 (transfer control 1) register (address 0BHEX)

bit 7: PFIFOCL (packet FIFO clear)

When this bit is set high, the packet FIFO is cleared. This bit is automatically set low after FIFO

has been cleared.
bit 6: RESERVED
bit 5: AUTOEND (enable auto transfer termination)

The following settings are automatically made upon completion of data transfer.

High: ATAPI status register - bit 7/bit 6/bit 3: BUSY/DRDY/DRQ = Low/High/Low

ATAPI interrupt reason register - bit 1/bit 0: IO/CoD = High/High
Interrupt request signal to host: HINT = High

Low: ATAPI status register - bit 7/bit 3: BUSY/DRQ = High/Low

Interrupt request signal to host: HINT = Low

bit 4: HSTXFREN (host transfer enable)

When this bit is set high, transfer starts between the host and buffer memory. This bit is

automatically set low when transfer is completed.

The following settings are automatically operated by setting this bit high.

ATAPI status register -bit 3: DRQ = High
ATAPI status register -bit 7: BUSY = Low (in the PIO mode)

bit 3, 2: RESERVED

– 25 –

bit 1: IO (host transfer direction)

To set this bit, the ATAPI status register -bit 7: BUSY bit must be high.
High: Data are transferred from the buffer memory to the host.
Low: Data are transferred from the host to the buffer memory.

bit 0: CoD (command or data)

To set this bit, the ATAPI status register -bit 7: BUSY bit must be high.
High: Indicates that data transferred are Command.
Low: Indicates that the data transferred are user data.

2-13. RESERVED (address 0CHEX)

2-14. CHPCTL0 (chip control 0) register (address 0DHEX)

bit 7: CHIPRST (chip reset)

This IC is reset by setting this bit high.

bit 6: TGTMET (target met)

(1) If the target sector is found while the write-only or real-time correction command is being

executed, the sub CPU sets TGTMET high.

(2) TGTMET bit is sampled at the 3/4 sector (variable depending on playback speed) after the

decoder interrupt. Therefore, if the target sector has been found, the sub CPU must set the

TGTMET bit high within this time after DECINT.
(3) Once the TGTMET bit is set high, the high state is held until the decoder is disabled.
(4) When the sampled TGTMET is low, while write-only or real-time correction is executed,

•the buffering area of main data or subcode is not renewed.

• main data are not corrected.

bit 5: INCTGT (increment target register)

When this bit is set high, TARGET registers (TGTMIN, TGTSEC, TGTBLK) are incremented.
TARGET registers use the BCD code.
TGTMIN, TGTSEC, and TGTBLK are connected in cascading fashion, and are incremented as
follows:
(1) The TGTBLK register value is always incremented by this bit. The address number 0 follows

74.

(2) The TGTSEC register value is incremented when this bit is high while the TGTBLK register

value is 74. The address number 0 follows 59.
(3) The TGTMIN register value is incremented when this bit is high, while the TGTBLK register

value is 74 and the TGTSEC register value 59. The address number 0 follows 99.

bit 4: RPCORTRG (repeat correction trigger)

When this bit is set high with the decoder disabled, error correction for the CD-ROM sector starts.
The sector to be corrected is assigned by the BFARA# register.

bit 3 to 0: RESERVED

CXD1812Q/R

– 26 –

CXD1812Q/R

2-15. CHPCTL1 (chip control 1) register (address 0EHEX)

bit 7 to 3: RESERVED
bit 2: DASP (DASP pin control)

When this bit is set high, the DASP signal is asserted.

bit 1: PDIAG (XPDI pin control)

When this bit is set high, the XPDI signal is asserted.

bit 0: CLRHINT (clear HINT)

HINT is cleared by setting this bit high. This bit is automatically set low when HINT has been
cleared.

2-16. Diskette change/drive address register (address 0FHEX)

bit 7: RESERVED
bit 6 to 2: Optional values can be set by sub CPU.

These values can be read from bits 6 to 2 of the diskette change/drive address register of the host.

bit 1 to 0: RESERVED

2-17. ATAPI error register (address 10HEX)

This register corresponds to the ATAPI error register of the host. The sub CPU can set any optional values.
bit 7 to 4: SENSE KEY
bit 3: MCR (Media Change Requested)
bit 2: ABRT (Aborted Command)
bit 1: EOM (End Of Media Detected)
bit 0: ILI (Illegal Length Indication)

2-18. ATAPI feature register (address 11HEX)

This register corresponds to the ATAPI feature register of the host.
The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is
high.
bit 0: DMA

2-19. ATAPI interrupt reason register (address 12HEX)

This register corresponds to the ATAPI interrupt reason register of the host.
The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is
high.
bit 1: IO

This bit is equivalent to the XFRCTL1 (address 0BHEX) register -bit 1.

bit 0: CoD

This bit is equivalent to the XFRCTL1 (address 0BHEX) register -bit 0.

2-20. ATA sector number register (address 13HEX)

This register corresponds to the ATA sector number register of the host.
The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is
high.

2-21. ATAPI byte count high/low register (address 14, 15HEX)

This register corresponds to the ATAPI byte count high/low register of the host.
The number of bytes to be transferred is set.
The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is
high.

– 27 –

CXD1812Q/R

2-22. ATAPI drive select register (address 16HEX)

This register corresponds to the ATAPI drive select register of the host.
The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is
high.
bit 4: DRV

2-23. ATA command register (address 17HEX)

This register corresponds to the ATA command register of the host.
The sub CPU can set any optional values in this register when the ATAPI status register -bit 7: BUSY bit is
high. However, the ATAPI soft reset command (08HEX) can be set regardless of the value of the BUSY bit.

2-24. RESERVED (address 18HEX)

2-25. ATAPI status 1 register (address 19HEX)

bit 7, 6: RESERVED
bit 5: DRDY1 (drive 1 ready)

This bit corresponds to the ATAPI status register -bit 6: DRDY bit of the host.
The DRDY status of the slave drive is set.

bit 4: DSC1 (drive 1 seek complete)

This bit corresponds to the ATAPI status register -bit 4: DSC bit of the host.
The DSC status of the slave drive is set.

bit 3: HST5

This bit corresponds to the ATAPI status register -bit 5 of the host.

bit 2: HST1

This bit corresponds to the ATAPI status register -bit 1 of the host.

bit 1: DRDY0 (drive 0 ready)

This bit corresponds to the ATAPI status register -bit 6: DRDY bit of the host. The DRDY status of
the master drive is set.

bit 0: DSC0 (drive 0 seek complete)

This bit corresponds to the ATAPI status register -bit 4: DSC bit of the host.
The DSC status of the master drive is set.

2-26. ATAPI status 2/drive control register (address 1AHEX)

bit 7: BUSY

This bit corresponds to the ATAPI status register -bit 7 of the host.

This bit must be set high when the sub CPU accesses the group of command block registers.
bit 6: RESERVED
bit 5: CORR

This bit corresponds to the ATAPI status register -bit 2 of the host.
bit 4: ENHINT (enable HINT)

An interrupt to the host can be made by setting this bit high.
bit 3 to 1: RESERVED
bit 0: CHECK

This bit corresponds to the ATAPI status register -bit 0 of the host.

– 28 –

CXD1812Q/R

2-27. UNLOCK (release lock mode) register (address 1BHEX)

The bits 5 to 0 of ATAPI status 1 register (address 19HEX), the bits 1 and 0 of XFRCTL1 register (address
0BHEX), and ATAPI interrupt reason register (address 12HEX) are locked in the cases below, making setting
from sub CPU impossible.

• When an ATAPI packet command (A0HEX) is detected.

• When data transfer with the host is completed while the XFRCTL1 register (address 0BHEX) bit
5: AUTOEND is high.

The sub CPU can release the lock mode above by accessing this register.

2-28. CPUBWDT (CPU buffer write data) register (address 1CHEX)

The sub CPU writes data to be written in the buffer memory into this register.

2-29. RESERVED (address 1DHEX)

2-30. SCTINF (sector information) register (address 1EHEX)

The current sector information is written into this register at DECINT. For automatic transfer of information to
the host, make sure this register is set for each DECINT. The value of this register is written into the internal
RAM.
bit 7 to 3: RESERVED
bit 2: Mode2

High: This sector is in Mode2.
Low: This sector is in Mode1 or CD-DA.

bit 1: Form2

This bit is valid only when the Mode2 bit is high.
High: This sector is in Form2.
Low: This sector is in Form1.

Both low and high are available for this bit in the Mode2 for Yellow Book.

MODE2 FORM2

"L"
"H"
"H"

"L"

"L"
"L"

"H"

"X"

MODE1
MODE2/FORM1
MODE2/FORM2
CD-DA

bit 0: RESERVED

2-31. RESERVED register (address 1F, 20HEX)

2-32. TGTMIN (target minute) register (address 21HEX)

0 to 99

2-33. TGTSEC (target sector ) register (address 22HEX)

0 to 59

– 29 –

CXD1812Q/R

2-34. TGTBLK (target block) register (address 23HEX)

0 to 74
When the monitor-only, write-only, or real-time correction command is executed, set the addresses of the
target sector in three target registers. This address is compared with the read sector address, and if they do
not match, the TGTNTMET (target not met) status (DECSTS0 register: bit 0) is established.

2-35. XFRCNT (transfer block counter) register (address 24HEX)

This 8-bit register indicates the remaining number of blocks to be transferred. The sub CPU sets the total
number of blocks to be transferred before transfer starts. This register value is decremented after one block
has been transferred.
The sub CPU can read the value of XFRCNT at any time. However, take care over ±1 error between the read
value and actual one, because the reading from sub CPU does not synchronize with variations of XFRCNT.

2-36. BFARA# (buffering area number) register (address 25HEX)

The buffer area is indicated by this register when write-only, real-time correction, or CD-DA command is
executed. The sub CPU, first assigns the area to start buffering before any of these commands is executed.
The register value is incremented after one sector is buffered.

Buffering starts from the address 0 when the subcode buffering command is executed.

2-37. DLARA (drive last area) register (address 26HEX)

While the decoder is executing the write-only, real-time correction, or CD-DA command, the last area for
buffering is assigned by this register. When the ENDLA (bit 1) of the DECCTL0 register is set high and data
from the drive (CD DSP) are written into the area assigned by DLARA while the decoder is executing any of
the above commands, all subsequent buffering is prohibited.

2-38. XFRARA (transfer area) register (address 27HEX)

The first area for starting transfer is assigned in the automatic transfer mode. The register value is incremented
after one block is transferred.

The sub CPU can read the value of XFRARA at any time. However, take care over ±1 error between the read
value and actual one, because the reading from sub CPU does not synchronize with the variation of XFRARA.

2-39. RESERVED (address 28HEX)

2-40. HXFRC-H, M, L (host transfer counter - high, middle, low) register (address 29 to 2BHEX)

The number of bytes to be transferred is set in the manual transfer mode. (19 bits)

2-41. RESERVED (address 2CHEX)

2-42. HADRC-H, M, L (host address counter - high, middle, low) register (address 2D to 2FHEX)

The head address to start transfer is assigned in the manual transfer mode.

2-43. RESERVED (address 30HEX)

2-44. SLADR-H, M, L (subcode last address - high, middle, low) register (address 31 to 33HEX)

While the subcode buffering command is being executed, the last address for buffering is set. When the
ENDLA (bit 1) of the DECCTL0 register is set high and data are written into the buffer address assigned by
SLADR while the decoder is executing the subcode buffering command, all subsequent buffering is prohibited.

– 30 –

CXD1812Q/R

2-45. RESERVED (address 34HEX)

2-46. CADRC-H, M, L (sub CPU address counter - high, middle, low) register (address 35 to 37HEX)

The addresses are set by this register when the sub CPU accesses the buffer memory. The register value is
incremented if the data concerned are read from the buffer memory or are written into it.

2-47. RESERVED (address 38 to 3BHEX)

2-48. CLRINT0 (clear interrupt status 0) register (address 3CHEX)

When each bit of this register is set high, the corresponding interrupt status is cleared. The bit is automatically
set low after its interrupt status has been cleared. Therefore, there is no need for the sub CPU to reset to low.
bit 7: DECINT (Decoder Interrupt)
bit 6: DECTOUT (Decoder Timeout)
bit 5: DRVOVRN (Drive Overrun)
bit 4: SUBCSYNC (Subcode Sync)
bit 3, 2: RESERVED
bit 1: SOFTRST (SRST Detected)
bit 0: HARDRST (HRST Detected)

2-49. CLRINT1 (clear interrupt status 1) register (address 3DHEX)

When each bit of this register is set high, the corresponding interrupt status is cleared. The bit is automatically
set low after its interrupt status has been cleared. Therefore, there is no need for the sub CPU to reset to low.
bit 7: PFIFOFUL (Packet FIFO Full)
bit 6: RESERVED
bit 5: RSTCMD (Reset Command)
bit 4: STSREAD (Host Status Read)
bit 3: HSTCMD (Host Command)
bit 2: PIONG (PIO Transfer NG)
bit 1: XFRSTOP (Transfer Stop)
bit 0: BLXFRCMP (Block Transfer Complete)

2-50. INTEN0 (interrupt enable 0) register (address 3EHEX)

When each bit of this register is set high, the interrupt request to the sub CPU by the corresponding interrupt
status is enabled. (That is, the XINT pin becomes active in the interrupt status.) Each bit value of this register
has no effect on the corresponding interrupt status.
bit 7: DECINT (Decoder Interrupt)
bit 6: DECTOUT (Decoder Timeout)
bit 5: DRVOVRN (Drive Overrun)
bit 4: SUBCSYNC (Subcode Sync)
bit 3, 2: RESERVED
bit 1: SOFTRST (SRST Detected)
bit 0: HARDRST (HRST Detected)

– 31 –

CXD1812Q/R

2-51. INTEN1 (interrupt enable 1) register (address 3FHEX)

When each bit of this register is set high, the interrupt request to the sub CPU by the corresponding interrupt
status is enabled. (That is, the XINT pin becomes active in the interrupt status.) Each bit value of this register
has no effect on the corresponding interrupt status.
bit 7: PFIFOFUL (Packet FIFO Full)
bit 6: RESERVED
bit 5: RSTCMD (Reset Command)
bit 4: STSREAD (Host Status Read)
bit 3: HSTCMD (Host Command)
bit 2: PIONG (PIO Transfer NG)
bit 1: XFRSTOP (Transfer Stop)
bit 0: BLXFRCMP (Block Transfer Complete)

– 32 –

CXD1812Q/R

3. Sub CPU Read Registers

Descriptions that are identical with those for the write registers are omitted here.

3-1. DRVSTS (drive status) register (address 00HEX)

The values set by the sub CPU can be read by this register.
bit 7: CINTPOL (subCPU Interrupt Polarity)
bit 6: M/S SEL (Master/Slave select)
bit 5: M/S EN (Master/Slave mode Enable)
bit 4, 3: RESERVED
bit 2, 1: RFRSCTL1, 0 (Refresh Control1, 0)
bit 1: RESERVED

3-2. RAWHDR (raw header) register (address 01HEX)

The Header bytes of the sector sent from the CD DSP can be read by this register at DECINT.

3-3. BFHDR (buffer header) register (address 02HEX)

The Header bytes of the current sector can be read when the write-only or real-time correction command is
executed, or after repeat correction has been executed. This register is invalid when the decoder is executing
the disable or the monitor-only command.

3-4. BFSHDR (buffer sub header) register (address 03HEX)

The Sub Header bytes of the current sector can be read when the write-only or real-time correction command
is executed, or after repeat correction has been executed. This register is invalid when the decoder is
executing the disable or the monitor-only command.

3-5. RAWHDRFLG (raw header flag) register (address 04HEX)

Indicates the C2PO value in the RAWHDR register.
bit 7: Minute
bit 6: Second
bit 5: Block
bit 4: Mode
bit 3 to 0: RESERVED

3-6. BFHDRFLG (buffer header flag) (address 05HEX)

Indicates the error state of each byte of BFHDR and BFSHDR registers. High means an error.
bit 7: Minute
bit 6: Second
bit 5: Block
bit 4: Mode
bit 3: File
bit 2: Channel
bit 1: Submode
bit 0: Data Type

– 33 –

3-7. RESERVED (address 06HEX)

3-8. DECSTS0 (decoder status 0) register (address 07HEX)

bit 7: SHRTSCT (short sector)

Indicates that the Sync mark interval was not more than 2351 bytes. This sector does not remain in
the buffer memory.

bit 6: NOSYNC

Indicates that the Sync mark was inserted, because one was not detected at the prescribed
position.

bit 5: CORINH (correction inhibit)

This is high if the current sector Mode and Form cannot be determined when the AUTODIST bit of
the DECCTL register is set high. ECC or EDC is not executed in this sector. The CORINH bit is
invalid when AUTODIST is set low. It is high under any of the conditions below when the
AUTODIST bit is set high.
(1) When there is an error in the Mode byte.
(2) When the Mode byte is a value other than 01HEX or 02HEX.
(3) When the Mode byte is 02HEX and the C2 pointer is high in the submode byte.

bit 4: ERINBLK (erasure in block)

When the decoder is operating in the monitor-only, write-only, or real-time correction mode, this
indicates that at least a 1-byte error flag (C2PO) has been raised in the data, excluding the Sync
mark from the current sector CD DSP.
When the decoder is operating in the CD-DA mode, this indicates that at least a 1-byte error flag
(C2PO) has been raised in the data from one sector (2352 bytes).

bit 3: CORDONE (correction done)

Indicates that there is an error-corrected byte in the current sector.

bit 2: EDCNG

Indicates that an error was found by the EDC check in the current sector.

bit 1: ECCNG

Indicates that there was an uncorrectable error from the Header byte to the P parity byte in the
current sector. (ECCNG = don't care in the Mode2, Form2 sectors.)

bit 0: TGTNTMET (target not met)

Indicates that the target addresses in the TGTMNT, TGTSEC, and TGTBLK registers do not
correspond with that of the read sector.

CXD1812Q/R

3-9. DECSTS1 (decoder status 1) register (address 08HEX)

bit 7 to 3: RESERVED
bit 2: EDCALL0 (EDC all 0)

This bit is high if there are no errors in the 4-EDC parity bytes of the current sector and the value is

00HEX.
bit 1: CMODE (correction mode)
bit 0: CFORM (correction form)

Indicates the Mode and Form the decoder has discriminated to correct errors of the current sector

when the decoder is operating in the real-time correction or repeat correction mode.

CMODE

"L"
"H"
"H"

CFORM

"X"
"L"

"H"

MODE1
MODE2, FORM1
MODE2, FORM2

– 34 –

3-10. XFRMOD (transfer mode) register (address 09HEX)

The values set by sub CPU can be read by this register.
bit 7: ENHINTCT (Enable Auto HINT upon Start of Packet Command Transfer)
bit 6: ENHINTDT (Enable Auto HINT upon Start of Data Transfer)
bit 5: ENMDMA (Enable Multiword DMA)
bit 4: ENDMABIT (Enable ATAPI Feature resister DMA bit)
bit 3: PIOSEL (PIO Transfer Mode Select)
bit 2: AUTOWAIT (Enable Auto Wait State)
bit 1, 0: WAITCYCL1, 0 (Wait Cycle 1, 0)

3-11. XFRSTS0 (data transfer status 0) register (address 0AHEX)

bit 7 to 2: RESERVED
bit 1: CBFWRRDY (sub CPU buffer write ready)

The sub CPU can write in the CPUBWDT register when this bit is high.

bit 0: CBFRDRDY (sub CPU buffer read ready)

The sub CPU can read the CPUBWDT register when this bit is high.

CXD1812Q/R

3-12. XFRSTS1 (data transfer status 1) register (address 0BHEX)

bit 7, 6: RESERVED
bit 5: AUTOEND (enable auto transfer termination)

Value set by sub CPU can be read.
bit 4: RESERVED
bit 3: PFIFOFUL (packet FIFO full status)

When a 12-byte packet command is written to the packet FIFO from the host, this bit is set high.
bit 2: PFIFOEMP (packet FIFO empty status)

When 12-byte data are read by sub CPU from the packet FIFO, this bit is set high.

These bits are automatically cleared when an ATAPI packet command (A0HEX) or an ATAPI soft

reset command (08HEX) is issued.

bit 1: IO (HOST transfer direction)

This bit can be set by both sub CPU and host.

In the cases below, the bit is automatically set.

High: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer has

been completed.

Low: When an ATAPI packet command (A0HEX) is issued.
bit 0: CoD (command or data)

This bit can be set by both sub CPU and host.

In the cases below, this bit is automatically set.

High: When an ATAPI packet command (A0HEX) is issued.

Low: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer has

been completed.

– 35 –

CXD1812Q/R

3-13. RESERVED (address 0C, 0DHEX)

3-14. CHPSTS (chip status) register (address 0EHEX)

bit 7 to 3: RESERVED
bit 2: DASP
bit 1: PDIAG

The DASP and XPDI pins can be monitored from these bits.

Positive logic.
bit 0: RESERVED

3-15. REV (revision number) register (address 0FHEX)

The revision number of this IC is 83HEX.

3-16. ATAPI error register (address 10HEX)

This register corresponds to the ATAPI error register of the host. The values set by sub CPU can be read.
bit 7 to 4: SENSE KEY
bit 3: MCR (Media Change Requested)
bit 2: ABRT (Aborted Command)
bit 1: EOM (End Of Media Detected)
bit 0: ILI (Illegal Length Indication)

3-17. ATAPI feature register (address 11HEX)

This register corresponds to the ATAPI feature register of the host. The values set by sub CPU or host can be
read.
bit 0: DMA

3-18. ATA sector count register (address 12HEX)

This register corresponds to the ATA sector count/ATAPI interrupt reason register of the host.
The values set by sub CPU or host can be read.

3-19. ATAPI sector number register (address 13HEX)

This register corresponds to the ATA sector number register of the host. The values set by sub CPU or host
can be read.

3-20. ATAPI byte count high/low register (address 14, 15HEX)

This register corresponds to the byte count high/low register of the host. The values set by sub CPU or host
can be read.

3-21. ATAPI drive select register (address 16HEX)

This register corresponds to the ATAPI drive select register of the host. The values set by sub CPU or host
can be read.
bit 4: DRV

3-22. ATA command register (address 17HEX)

This register corresponds to the ATA command register of the host. The values set by sub CPU or host can be
read.

– 36 –

3-23. ATAPI packet command register (address 18HEX)

This register is a 12-bytes FIFO.
The ATAPI packet command issued from the host can be read by reading this register 12 times.

3-24. ATAPI status 1 register (address 19HEX)

The values set by sub CPU can be read.
bit 7, 6: RESERVED
bit 5: DRDY1 (Drive1 Ready)
bit 4: DSC1 (Drive1 Seek Complete)
bit 3: HST5
bit 2: HST1
bit 1: DRDY0 (Drive0 Ready)
bit 0: DSC0 (Drive0 Seek Complete)

3-25. ATAPI status 2 register (address 1AHEX)

bit 7: BUSY

In the cases below, the bit is set automatically. The bit can also be set directly by the sub CPU.

High: When the host writes a command into the ATAPI command register.

High: When the transfer of a 6-words (12-bytes) packet command from the host has been

completed.

High: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is low and the data transfer with the

host has been completed.
High: When various reset signals have been asserted.
Low: When an ATAPI packet command (A0HEX) is issued and the setting of packet command

transfer has been completed.
Low: When the data transfer with the host is activated in the PIO mode.
Low: When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer with the

host has been completed.

bit 6: RESERVED
bit 5: CORR

The values set by sub CPU can be read.

bit 4: HINT

The HINT signal can be monitored.
In the cases below, this bit is set automatically.

• When the XFRMOD register (09HEX) -bit 7: ENHINTCT is high and the setting of packet command

transfer is completed.

• When the XFRMOD register (09HEX) -bit 6: ENHINTDT is high and the data transfer with the host

is activated.

• When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is high and the data transfer with the host

is completed.

The bit is reset in the cases below.

• When the host has read the ATAPI status register.

• When the transfer of 12-bytes packet command has been completed before the host reads

the ATAPI status register.

• When the XFRCTL1 register (0BHEX) -bit 5: AUTOEND is low and the data transfer with the host

has been completed before the host reads the ATAPI status register.

bit 3: HRST

The HRST pin can be monitored.

bit 2: SRST
bit 1: XHINEN

This bit corresponds to the ATAPI device control register - bit 2, 1 of the host.
The values set by the host can be read.

bit 0: CHECK

The values set by sub CPU can be read.

CXD1812Q/R

– 37 –

CXD1812Q/R

3-26. CSCTARA (current sector area) (address 1BHEX)

Indicates the area number being written in the current sector.

3-27. CPUBRDT (CPU buffer read data) register (address 1CHEX)

The sub CPU reads data from the buffer memory via this register.

3-28. SBCSTS (subcode status) register (address 1DHEX)

The error status of the subcode written to the buffer while the CD-DA command is executed is indicated by this
register.
The period of validity is from a DECINT to the next DECINT.
bit 7: SBCOVRN (subcode overrun)

The SBCOVRN status is established when the ENSBCBT (bit 3) of the XFRFMT1 register is set
high and subcode buffering to the area assigned by DLARA is completed while the decoder is
executing the CD-DA command. Establishment of DRVOVRN and SBCOVRN states involves a
time difference.

bit 6: OVERFLOW

Indicates that the FIFO of SBCSTS has overflowed with frequent occurrences of the subcode short
sync. Subcode buffering is stopped by this overflow. Subcode has not been buffered in sectors
obtained by subsequent interrupts of the decoder.

bit 5: BFNTVAL (buffer not valid)

Indicates that valid data have not been written to the buffer due to the short subcode sector.

bit 4: NOSYNC0

Indicates that the Sync mark was inserted because subcode Sync mark was not detected at the
prescribed position.

bit 3 to 1: RESERVED
bit 0: SUBQERR0 (subcode-Q error 0)

Indicates that the subcode-Q was determined to be an error by the CRC check when ALLSBC is
low.

3-29. SBQSTS (subcode-Q status) register (address 1EHEX)

This register indicates the error status of the subcode-Q taken from CD DSP.
The period of validity is from a SBCSYNC to the next SBCSYNC.
bit 7 to 3: RESERVED
bit 2: SHTSBCS1 (short subcode sector 1)

Indicates that the subcode Sync mark interval after the previous SBCSYNC interrupt occurred was
less than 98WFCK.

bit 1: NOSYNC1

Indicates that the Sync mark was inserted because subcode Sync mark was not detected at the
prescribed position.

bit 0: SUBQERR1 (subcode-Q error 1)

Indicates that the subcode-Q was determined to be an error by the CRC check.

3-30. SBQDT (subcode-Q DATA) register (address 1FHEX)

The subcode-Q value can be read by reading this register 10 times. The read subcode-Q is data just before
the SBCSYNC interrupt.

3-31. RESERVED (address 20HEX)

3-32. TGTMIN (target minute) register (address 21HEX)

3-33. TGTSEC (target second) register (address 22HEX)

– 38 –

3-34. TGTBLK (target block) register (address 23HEX)

3-35. XFRCNT (transfer block counter) register (address 24HEX)

3-36. BFARA# (buffering area number) register (address 25HEX)

3-37. DLARA (drive last area) register (address 26HEX)

3-38. XFRARA (transfer area) register (address 27HEX)

3-39. RESERVED (address 28HEX)

3-40. HXFRC-H, M, L (host transfer counter - high, middle, low) register (address 29 to 2BHEX)

3-41. RESERVED (address 2CHEX)

3-42. HADRC-H, M, L (host address counter - high, middle, low) register (address 2D to 2FHEX)

CXD1812Q/R

3-43. RESERVED (address 30HEX)

3-44. SLDR-H, M, L (subcode last address - high, middle, low) register (address 31 to 33HEX)

3-45. RESERVED (address 34HEX)

3-46. CADRC-H, M, L (sub CPU address counter - high, middle, low) register (address 35 to 37HEX)

3-47. RESERVED (address 38HEX)

3-48. SADRC-H, M, L (subcode address counter - high, middle, low) register (address 39 to 3BHEX)

The buffer address can be read in the subcode buffering command.

– 39 –

CXD1812Q/R

3-49. INTSTS0 (interrupt status 0) register (address 3CHEX)

The value of each bit in this register is the value of corresponding interrupt status. These bits are not affected
by the values of the INTEN0 register bits.
bit 7: DECINT (decoder interrupt)

This interrupt occurs when the decoder is operating a command.
(1) The DECINT status is established if the Header byte is received from CD DSP when the Sync

mark is detected or inserted while the decoder is executing the write-only, monitor-only, or real­time correction command. However, it is not established if the Sync mark interval is less than
2352 bytes when its detection window is open.

(2) The DECINT status is established each time one correction is completed when the decoder is

in the repeat correction mode.

(3) The DECINT status is established each time 2352 bytes of data are written while the decoder

is executing the CD-DA command.

(4) The DECINT status is established when the subcode Sync mark is detected or is inserted

when the decoder is executing subcode buffering. However, it is not established if the interval
from the DECINT to the next subcode Sync mark detected is less than 98WFCK.

bit 6: DECTOUT (decoder timeout)

The DECTOUT status is established when the Sync mark is not detected even after the time it
takes to search three sectors (40.6ms at normal speed playback) has elapsed after the decoder
has been set to the monitor-only, write-only or real-time correction mode.

bit 5: DRVOVRN (drive overrun)

The DRVOVRN status is established when the buffering into the area assigned by DLARA is
completed while the decoder is executing the write-only, real-time correction or CD-DA command.
The DRVOVRN status is also established when the buffering into the address assigned by SLADR
is completed while the decoder is executing the subcode buffering command.

bit 4: SUBCSYNC (subcode sync)

The SUBCSYNC status is established when the subcode Sync mark is detected or inserted while
taking-in of subcode is enabled. However, it is not established if the interval from the SUBCSYNC
to the next subcode Sync mark detected is less than 98WFCK.
If the SUBCSYNC interrupt is not cleared within 95WFCK from the interrupt, the SUBCSYNC
status is not established when the next subcode Sync mark is detected or inserted. In this case,
the subcode-Q read from the SBQDT register is not renewed.

bit 3, 2: RESERVED
bit 1: SOFTRST (SRST detected)

The SOFTRST status is established when the host asserts the ATAPI device control register -bit 2:
SRST.

bit 0: HARDRST (HRST detected)

The HARDRST status is established when the host asserts the HRST pin.

– 40 –

CXD1812Q/R

3-50. INSTS1 (interrupt status 1) register (address 3DHEX)

The value of each bit in this register is that of the corresponding interrupt status. These bits are not affected by
the values of the INTEN1 register bits.
bit 7: PFIFOFUL (packet FIFO full)

The PFIFOFUL status is established when the transfer of a 6-words (12 bytes) packet command
from the host is completed.

bit 6: RESERVED
bit 5: RSTCMD (reset command)

The RSTCMD status is established when an ATAPI soft reset command (08HEX) is issued from the
host.

bit 4: STSREAD (HOST status read)

The STSREAD status is established when the ATAPI status register is read by the host after data
transfer with the host has been completed.

bit 3: HSTCMD (host command)

The HSTCMD status is established when the command is written into the ATA command register
from the host.

bit 2: PIONG (PIO transfer NG)

The PIONG status is established if a read/write operation is executed by the host when the IO
channel ready signal: REDY is low (not ready) during data transfer in the PIO mode.

bit 1: XFRSTOP (transfer stop)

The XFRSTOP status is established when all transfers are completed when the automatic transfer
mode to the host is enabled.
The XFRSTOP status is also established after transfer to the host is completed by HXFRC when
the automatic transfer mode to the host is disabled.

bit 0: BLXFRCMP (block transfer complete)

The BLXFRCMP status is established after one block transfer is completed when the automatic
transfer mode to the host is enabled.

3-51. INTEN0 (interrupt enable 0) register (address 3EHEX)

The values written to the INTEN0 register can be read as they are.

3-52. INTEN1 (interrupt enable 1) register (address 3FHEX)

The values written to the INTEN1 register can be read as they are.

– 41 –

CXD1812Q/R

REG ADR

CONFIG0

CONFIG1

LSTARA

LHADR

DRVIF

XFRFMT0

XFRFMT1

DECCTL0

DECCTL1

XFRMOD

00

01

02

03

04

05

06

07

08

09

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CINT
POL

SW
OPEN

b7

b7
C2PO

L1st
"L"
BLKE

FLAG
AUTO

DIST
ENSB

QRD
ENHI

NTCT

M/S
SEL

"L"

b6

b6
LCH

LOW
"L"

"L"
MODE

SEL
"L"
ENHI

NTDT

M/S
EN

"H"

b5

b5
BCLK

RED
SYNC
ENBY

TFBT
FORM

SEL
DEC

CMD2
EN

MDMA

"L"

"L"

b4

b4
BCLK

MD1
HEAD

ER
"L"

"L"
DEC

CMD1
ENDM

ABIT

EXCK
SEL

"L"

b3

b3
BCLK

MD0
SBHE

ADER
ENSB

CBT
ENFM

2EDC
DEC

CMD0
PIO

SEL

DIS
MCLK

RFRS
CTL1

b2

b2
LSB

1st
USER

DATA
ALL

SBC
MDBY

TCTL
"L"
AUTO

WAIT

DIS
HCLK

RFRS
CTL0

b1

b1

"L"
PARI

TY
"L"
EN

DLA
"L"
WAIT

CYCL1

RAM
SIZE

"L"

b0

b0

"L"

"L"
ZA

SUBQ
ATDL

RNEW
"L"
WAIT

CYCL0

XFRCTL0

XFRCTL1

CHPCTL0

CHPCTL1
DISCHG

DRVADR
ERROR

FEATUR
INT

REASON
SECTOR

NUMBER

0A

0B

0C

0D

0E

0F

10

11

12

13

AUTO
XFR

PFIF
O CL

"L"
CHIP

RST
"L"

"L"

b7

b7

b7

"L"

"L"

"L"
TGT

MET
"L"

b6

SENSE KEY

b6

b6

b6

"L"
AUTO

END
"L"
INC

TGT
"L"

b5

b5

b5

b5

"L"
HSTX

FREN
"L"
RPCO

RTRG
"L"

b4

b4

b4

b4

CPUD
MAEN

"L"

"L"

"L"

"L"

b3

MCR

b3

b3

b3

CPU
SRC

"L"

"L"

"L"

DASP

b2

ABRT

b2

b2

b2

"L"

IO

"L"

"L"

PDIAG

"L"

EOM

b1

IO

b1

"L"

CoD

"L"

"L"
CLR

HINT
"L"

ILI

DMA

CoD

b0

BYTE
CNT-H

BYTE
CNT-L

14

15

b15

b7

b14

b6

b13

b5

b12

b4

Sub CPU write registers (1)

– 42 –

b11

b3

b10

b2

b9

b1

b8

b0

CXD1812Q/R

REG ADR

DRIVE
SELECT

HOST
CMD

ATAPI
STS 1

ATAPI
STS 2

UN
LOCK

CPUBW
DT

SCTINF

16

17

18

19

1A

1B

1C

1D

1E

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

b7

b7

"L"

"L"

BUSY

b7

"L"

"L"

b6

b6

"L"

"L"

"L"

b6

"L"

"L"

b5

b5

"L"

DRDY1

CORR

b5

"L"

"L"

DRV

b4

"L"

DSC1
EN

HINT

b4

"L"

"L"

b3

b3

"L"

HST5

"L"

b3

"L"

"L"

b2

b2

"L"

HST1

"L"

b2

"L"

MODE2

b1

b1

"L"

DRDY0

"L"

b1

"L"

FORM2

b0

b0

"L"

DSC0

CHECK

b0

"L"

"L"

TGTMIN

TGTSEC

TGTBLK

XFRCNT

BFARA#

DLARA

XFRARA

1F

20

21

22

23

24

25

26

27

28

"L"

"L"

b7

b7

b7

b7

b7

b7

b7

"L"

"L"

"L"

b6

b6

b6

b6

b6

b6

b6

"L"

"L"

"L"

b5

b5

b5

b5

b5

b5

b5

"L"

"L"

"L"

b4

b4

b4

b4

b4

b4

b4

"L"

"L"

"L"

b3

b3

b3

b3

b3

b3

b3

"L"

"L"

"L"

b2

b2

b2

b2

b2

b2

b2

"L"

"L"

"L"

b1

b1

b1

b1

b1

b1

b1

"L"

"L"

"L"

b0

b0

b0

b0

b0

b0

b0

"L"

HXFRC

-H
HXFRC

-M
HXFRC

-L

29

2A

2B

"L"

b15

b7

"L"

b14

b6

"L"

b13

b5

"L"

b12

b4

Sub CPU write registers (2)

– 43 –

"L"

b11

b3

b18

b10

b2

b17

b9

b1

b16

b8

b0

CXD1812Q/R

REG ADR

HADRC

-H
HADRC

-M
HADRC

-L

SLADR

-H
SLADR

-M
SLADR

-L

CADRC

-H

2C

2D

2E

2F

30

31

32

33

34

35

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

"L"

"L"

b15

b7

"L"

"L"

b15

b7

"L"

"L"

"L"

"L"

b14

b6

"L"

"L"

b14

b6

"L"

"L"

"L"

"L"

b13

b5

"L"

"L"

b13

b5

"L"

"L"

"L"

"L"

b12

b4

"L"

"L"

b12

b4

"L"

"L"

"L"

"L"

b11

b3

"L"

"L"

b11

b3

"L"

"L"

"L"

b18

b10

b2

"L"

b18

b10

b2

"L"

b18

"L"

b17

b9

b1

"L"

b17

b9

b1

"L"

b17

"L"

b16

b8

b0

"L"

b16

b8

b0

"L"

b16

CADRC

-M
CADRC

-L

CLRINT0

CLRINT1

INTEN0

INTEN1

36

37

38

39

3A

3B

3C

3D

3E

3F

b15

b7

"L"

"L"

"L"

"L"
DEC

INT
PFIF

OFUL
DEC

INT
PFIF

OFUL

b14

b6

"L"

"L"

"L"

"L"
DEC

TOUT
"L"
DEC

TOUT
"L"

b13

b5

"L"

"L"

"L"

"L"
DRV

OVRN
RST

CMD
DRV

OVRN
RST

CMD

b12

b4

"L"

"L"

"L"

"L"
SUBC

SYNC
STS

READ
SUBC

SYNC
STS

READ

b11

b3

"L"

"L"

"L"

"L"

"L"
HST

CMD
"L"
HST

CMD

b10

b2

"L"

"L"

"L"

"L"

"L"
PIO

NG
"L"
PIO

NG

b9

b1

"L"

"L"

"L"

"L"
SOFT

RST
XFR

STOP
SOFT

RST
XFR

STOP

b8

b0

"L"

"L"

"L"

"L"
HARD

RST
BLXF

RCMP
HARD

RST
BLXF

RCMP

Sub CPU write registers (3)

– 44 –

CXD1812Q/R

REG ADR

DRVSTS

RAWHDR

BFHDR

BFSHDR
RAWHDR

FLG
BFHDR

FLG

DECSTS0

DECSTS1

XFRMOD

00

01

02

03

04

05

06

07

08

09

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CINT
POL

b7

b7

b7
MIN

UTE
MIN

UTE

SHRT
SCT

"Z"
ENHI

NTCT

M/S
SEL

b6

b6

b6
SEC

OND
SEC

OND

NO
SYNC

"Z"
ENHI

NTDT

M/S
EN

b5

b5

b5
BLO

CK
BLO

CK

COR
INH

"Z"
EN

MDMA

"L"

b4

b4

b4

MODE

MODE

ERIN
BLK

"Z"
ENDM

ABIT

"L"

b3

b3

b3

"H"

FILE

COR
DONE

"Z"
PIO

SEL

RFRS
CTL1

b2

b2

b2

"H"
CHAN

NEL

EDC
NG

EDC
ALL0

AUTO
WAIT

RFRS
CTL0

b1

b1

b1

"H"
SUB

MODE

ECC
NG

C
MODE

WAIT
CYCL1

"L"

b0

b0

b0

"H"
DATA

TYPE

TGTN
TMET

C
FORM

WAIT
CYCL0

XFRSTS0

XFRSTS1

CHPSTS

REV

ERROR

FEATUR
SECTOR

COUNT
SECTOR

NUMBER

0A

0B

0C

0D

0E

0F

10

11

12

13

"H"

"L"

"L"

"H"

b7

b7

b7

"H"

"L"

"L"

"L"

SENSE KEY

b6

b6

b6

"H"
AUTO

END

"L"

"L"

b5

b5

b5

"H"

"L"

"L"

"L"

b4

b4

b4

"H"
PFIF

OFUL

"L"

"L"

MCR

b3

b3

b3

"H"
PFIF

OEMP

DASP

"L"

ABRT

b2

b2

b2

CBFW
RRDY

IO

PDIAG

"H"

EOM

b1

b1

b1

CBFR
DRDY

CoD

"L"

"H"

ILI

DMA

b0

b0

BYTE
CNT-H

BYTE
CNT-L

14

15

b15

b7

b14

b6

b13

b5

b12

b4

Sub CPU read registers (1)

– 45 –

b11

b3

b10

b2

b9

b1

b8

b0

CXD1812Q/R

REG ADR

DRIVE
SELECT

HOST
CMD

PACKET
CMD

ATAPI
STS 1

ATAPI
STS 2

CSCT
ARA

CPUBR
DT

SBCSTS

SBQSTS

16

17

18

19

1A

1B

1C

1D

1E

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

b7

b7

b7

"L"

BUSY

b7

b7
SBC

OVRN
"H"

LBA

b6

b6

"L"

"L"

b6

b6
OVER

FLOW
"H"

b5

b5

b5

DRDY1

CORR

b5

b5
BFNT

VAL
"H"

DRV

b4

b4

DSC1

HINT

b4

b4
NOSY

NC0
"H"

b3

b3

b3

HST5

HRST

b3

b3

"H"

"H"

b2

b2

b2

HST1

SRST

b2

b2

"H"
SHTS

BCS1

b1

b1

b1

DRDY0
XHIN

TEN
b1

b1

"H"
NOSY

NC1

b0

b0

b0

DSC0

CHECK

b0

b0
SUBQ

ERR0
SUBQ

ERR1

SUBQDT

TGTMIN

TGTSEC

TGTBLK

XFRCNT

BFARA#

DLARA

XFRARA

1F

20

21

22

23

24

25

26

27

28

b7

b7

"L"

"L"

b7

b7

b7

b7

b6

b6

b6

b6

b6

b6

b6

b6

b5

b5

b5

b5

b5

b5

b5

b5

b4

b4

b4

b4

b4

b4

b4

b4

b3

b3

b3

b3

b3

b3

b3

b3

b2

b2

b2

b2

b2

b2

b2

b2

b1

b1

b1

b1

b1

b1

b1

b1

b0

b0

b0

b0

b0

b0

b0

b0

HXFRC

-H
HXFRC

-M
HXFRC

-L

29

2A

2B

"Z"

b15

b7

"Z"

b14

b6

"Z"

b13

b5

"Z"

b12

b12

Sub CPU read registers (2)

– 46 –

"Z"

b11

b3

b18

b10

b2

b17

b9

b1

b16

b8

b0

CXD1812Q/R

REG ADR

HADRC

-H
HADRC

-M
HADRC

-L

SLADR

-H
SLADR

-M
SLADR

-L

CADRC

-H

2C

2D

2E

2F

30

31

32

33

34

35

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

"L"

b15

b7

"L"

b15

b7

"H"

"L"

b14

b6

"L"

b14

b6

"H"

"L"

b13

b5

"L"

b13

b5

"H"

"L"

b12

b4

"L"

b12

b4

"H"

"L"

b11

b3

"L"

b11

b3

"H"

b18

b10

b2

b18

b10

b2

b18

b17

b9

b1

b17

b9

b1

b17

b16

b8

b0

b16

b8

b0

b16

CADRC

-M
CADRC

-L

SADRC

-H
SADRC

-M
SADRC

-L
INTSTS0

INTSTS1

INTEN0

INTEN1

36

37

38

39

3A

3B

3C

3D

3E

3F

b15

b7

"L"

b15

b7
DEC

INT
PFIF

OFUL
DEC

INT
PFIF

OFUL

b14

b6

"L"

b14

b6
DEC

TOUT
"L"
DEC

TOUT
"L"

b13

b5

"L"

b13

b6
DRV

OVRN
RST

CMD
DRV

OVRN
RST

CMD

b12

b4

"L"

b12

b4
SUBC

SYNC
STS

READ
SUBC

SYNC
STS

READ

b11

b3

"L"

b11

b3

"L"
HST

CMD
"L"
HST

CMD

b10

b2

b18

b10

b2

"L"
PIO

NG
"L"
PIO

NG

b9

b1

b17

b9

b1
SOFT

RST
XFR

STOP
SOFT

RST
XFR

STOP

b8

b0

b16

b8

b0
HARD

RST
BLXF

RCMP
HARD

RST
BLXF

RCMP

Sub CPU read registers (3)

– 47 –

4. HOST Interface

The following ATAPI registers are supported.

Address Register

HCS0 HCS1 HA2 HA1 HA0 Read (XHRD) Write (XHWR)

Control block registers

CXD1812Q/R

1
1

0
0

1
1

1
1

0
1

Alternate ATAPI Status

Diskette Change/Drive Address

ATAPI Device Control

Unused

Command block registers
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

ATAPI Error

ATAPI Interrupt Reason

ATA Sector Number

ATAPI Byte Count Low

ATAPI Byte Count High

ATAPI Drive Select

ATAPI Status ATA Command

Data

ATAPI Feature

ATA Sector Count

The bit width of all registers excluding the data register is 8 bits. The bit width of the data register is 16 bits.

Command block registers

The host can read/write to the command block registers only when the BUSY bit (ATAPI status register -bit 7)
is low. When the BUSY bit is high, the value of the alternate ATAPI status register is read.

4-1. Data register (read/write)

This register is valid only when the DRQ bit (ATAPI status register -bit 3) is high.
The bit width of this register is 16 bits.

4-2. ATAPI error register (read)

The error status of the command finally executed by the drive is read by this register.
bit 7 to 4: SENSE KEY
bit 3: MCR (Media Change Requested)
bit 2: ABRT (Aborted Command)
bit 1: EOM (End Of Media Detected)
bit 0: ILI (Illegal Length Indication)

4-3. ATAPI feature register (write)

bit 7 to 1: Optional values can be set.
bit 0: DMA (optional)

Set this bit high for data transfer in the DMA mode.
However, the transfer mode is determined by the combination of this bit and the ENDMABIT (bit 4)
and PIOSEL (bit 3) bits of the sub CPU transfer mode register (address 09HEX).

– 48 –

CXD1812Q/R

4-4. ATAPI interrupt reason (read)/ATA sector count (write) register

This 8-bytes register can be read/written by both host and sub CPU.
bit 1: IO (In or Out)
bit 0: CoD (Command or Data)
The direction and type of data transfer are determined by the three bits: IO, CoD, and DRQ (ATAPI status
register -bit 3).

DRQ IO Status of transfer

"H"
"H"
"H"
"H"

"L"

"L"

"L"
"H"
"H"
"H"

CoD

"L"
"H"
"L"
"H"
"H"

Data transfer from host
Packet command transfer from host
Data transfer to host
RESERVED
Data transfer termination status

4-5. ATA sector number register (read/write)

This 8-bytes register can be read/written by both host and sub CPU.

4-6. ATAPI byte count low/high register (read/write)

This register sets the number of bytes transferred by one data transfer request (DRQ). (16 bits)
This register can be read/written by both host and sub CPU.

4-7. ATAPI drive select register (read/write)

This 8-bytes register can be read/written by both host and sub CPU.
bit 4: DRV

This bit allows the host to select the drive.
High: Selects the slave drive.
Low: Selects the master drive.

4-8. ATAPI status register (read)

This register allows the host to read the drive status. The interrupt request signal: HINT to the host is cleared
by reading this register.
bit 7 BUSY
bit 6 DRDY (Drive Ready)
bit 4 DSC (Drive Seek Complete)
bit 3 DRQ (Data Request)
bit 2 CORR (Corrected Data)
bit 0 CHECK
bit 5, 1: The values set by sub CPU can be read.

4-9. ATA command register (write)

This register allows the host to write the ATA command.
The interrupt request is applied to sub CPU by writing a command to this register.

– 49 –

Control Block Registers

4-10. Alternate ATAPI status register (read)

This register is identical to the ATAPI status register.
However, the interrupt request signal: HINT to the host is not cleared by reading this register.

4-11. ATAPI device control register (write)

bit 7 to 3: RESERVED
bit 2: SRST

This bit is the ATA soft reset bit. (See appendix.)

bit 1: nIEN

When this bit is set low while a drive is selected, the interrupt request signal: HINT to the host is
enabled. When this bit is high or the drive is not selected, the HINT pin generates a high
impedance.

bit 0: RESERVED

4-12. Diskette change/drive address register (read)

bit 7: Hi-Z
bit 6 to 2: The values set by sub CPU can be read.
bit 1: nDS1

This is low when the slave drive is selected.

bit 0: nDS0

This is low when the master drive is selected.

CXD1812Q/R

– 50 –

Appendix: Reset Condition

XRST: XRST pin
CRST: CHPCTL0 register (0DHEX) -bit 7
HRST: HRST pin
RCMD: ATAPI soft reset command (08HEX)
SRST: ATAPI software reset

1. Sub CPU write registers

CXD1812Q/R

Bit76543210REG ADR XRST CRST HRST RCMD SRST

CONFIG0

CONFIG1

LSTARA
LHADR
DRVIF
XFRFMT0
XFRFMT1
DECCTL0
DECCTL1

XFRMOD

XFRCTL0

XFRCTL1

CHPCTL0
CHPCTL1

00h

01h

02h
03h
04h
05h
06h
07h
08h

09h

0Ah

0Bh

0Dh

0Eh

O

O

O

O
O
O

O

O
O
O
O
O
O
O

O
O

O

O

O

O

O

O

O
O
O

O

O

O
O

O

O

O

O

000X0000
0010X01X
XXXXX01X
00000000
00000000
001010X0
XX00000X
0X0X00X0
100X0101
0X000XXX
01001000
XX0XXXXX
1XXX00XX
0X00XX00
XX00XX00
0000XXXX

XXXXX10X
DISCHG
ERROR
FEATUR
IREASON
SECTNO.
BYTCNT-H
BYTCNT-L
DRVSEL
HSTCMD
ASTS1

ASTS2

UNLOCK
CPUBWDT
SCTINF

0Fh

10h
11h
12h
13h
14h
15h
16h
17h
19h

1Ah

1Bh

1Ch

1Eh

O
O
O
O
O
O
O
O
O
O
O

O
O
O
O

O

O
O
O
O
O

O

O

O
O
O
O

O

O

O

O
O

O
O

X00000XX
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
XX000000
1X00XXX0
1XXXXXXX

00000000
XXXXX00X

– 51 –

CXD1812Q/R

Bit76543210REG ADR XRST CRST HRST RCMD SRST
TGTMIN
TGTSEC
TGTBLK
XFRCNT
BFARA
DLARA
XFRARA
HXFRC-H
HXFRC-M
HXFRC-L
HADRC-H
HADRC-M
HADRC-L
SLADR-H
SLADR-M
SLADR-L
CADRC-H

21h
22h
23h
24h
25h
26h
27h
29h
2Ah
2Bh

2Dh

2Eh
2Fh
31h
32h
33h
35h

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

00000000
00000000
00000000
00000000
00000000
00000000
00000000
XXXXX000
00000000
00000000
XXXXX000
00000000
00000000
XXXXX000
00000000
00000000

XXXXX000
CADRC-M
CADRC-L
CLRINT0
CLRINT1
INTEN0
INTEN1

36h

37h
3Ch
3Dh

3Eh

3Fh

O
O
O
O
O
O

O
O
O
O
O
O

00000000
00000000
0000XX00
0X000000
0000XX00
0X000000

– 52 –

2. Sub CPU read registers

CXD1812Q/R

Bit76543210REG ADR XRST CRST HRST RCMD SRST
DRVSTS
RAWHDR
BFHDR
BFSHDR
RAWHDFG
BFHDRFG
DECSTS0
DECSTS1

XFRMOD

XFRSTS0
XFRSTS1
CHPSTS
REV
ERROR
FEATUR
IREASON

00h
01h
02h
03h
04h
05h
07h
08h

09h

0Ah
0Bh
0Eh

0Fh
10h
11h
12h

O
O
O
O
O
O
O
O
O

O
O
O

O
O
O
O
O
O
O
O
O

O

O
O
O
O

O
O

O

O

O

00000010
00000000
00000000
00000000
00001111
00000000
00000100

XXXXX000

01001000

XX0XXXXX

11111100
00000100
000001X0

10000011
O
O
O

O
O
O

O

O

00000000

00000000

00000000

SECTNO.
BYTCNT-H
BYTCNT-L
DRVSEL
HSTCMD
PACCMD
ASTS1

ASTS2

CSCTARA
CPUBRDT
SBCSTS
SBQSTS
SBQDT
TGTMIN

13h
14h
15h
16h
17h
18h
19h

1Ah

1Bh
1Ch
1Dh
1Eh

1Fh
21h

O
O
O
O
O
O
O
O

O
O
O
O

O

O

O
O
O

O

O
O
O

O

O

O
O
O

O
O

00000000
00000000
00000000
00000000
00000000
00000000
00000000
1000X010
10001010
1000XXX0
10XXX1XX
00000000
00000000

XXXXXXXX

O

O

11111000

XXXXXXXX

O

O

00000000
TGTSEC
TGTBLK
XFRCNT

22h
23h
24h

O
O
O

O
O
O

00000000

00000000

00000000

– 53 –

CXD1812Q/R

Bit76543210REG ADR XRST CRST HRST RCMD SRST
BFARA
DLARA
XFRARA
HXFRC-H
HXFRC-M
HXFRC-L
HADRC-H
HADRC-M
HADRC-L
SLADR-H
SLADR-M
SLADR-L
CADRC-H
CADRC-M
CADRC-L
SADRC-H
SADRC-M

25h
26h
27h

29h
2Ah
2Bh

2Dh

2Eh
2Fh

31h

32h

33h

35h

36h

37h

39h
3Ah

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

00000000
00000000
00000000

XXXXX000

00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
11111000
00000000
00000000
00000000
00000000

SADRC-L

INTSTS0

INTSTS1

INTEN0
INTEN1

3Bh

3Ch

3Dh

3Eh
3Fh

O
O

O
O

O

O

O

O

O

O
O
O

O
O

00000000

00000000
XXXX00X1
XXXX001X

00000000

00X000XX

001000XX

00000000

00000000

– 54 –

ATAPI bus

CXD1812Q/R

10kΩ

DRAM

80 to 83

85 to 88

MDB0 to 7

55

69 to 72

74 to 77

HDB0 to F

43 to 46, 48 to 51

MA0 to 9

26, 27, 30 to 33, 35 to 38

42

41

39

XMWR

XCAS

XRAS

56

HCS0, 1

575860

HA0 to 2

66

XHRD

CXD1812Q

67

63

XHAC

XHWR

68

HDRQ

62

HINT

61

XS16

64

REDY

52

DASP

59

XPDI

89

HRST

D0 to 7

A0 to 5

XRD
XWR
XCS
XINT

XTL1

XTL2

XRST

10 to 14, 16 17 to 21, 23 to 25
9

8
7
6

92

91

95

subCPU

33.8688MHz

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Application Circuit

LRCK

5

32

LRCK

MDAT

2

34

DA16

BCLK
1

35

DA15

C2PO
100

44

C2PO

EXCK
96

65

EXCK

CXD2500

SBIN
97

64

SBSO

– 55 –

SCOR
98

63

SCOR

WFCK
99

62

WFCK

XTAI

XTSL

PSSL

MCLK
93

53

55

30

HCLK
94

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

CXD1812Q/R

A

SONY CODE
EIAJ CODE

JEDEC CODE

75

76

0.65

0° to 15°

∗ 14.0 ± 0.1

±0.12

M

0.15

(16.3)

DETAIL A

QFP-100P-L01
∗QFP100-P-1420-A

0.8 ± 0.2

100PIN LQFP (PLASTIC)

16.0 ± 0.2

51

50

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT

LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

+ 0.35

2.75 – 0.15

100

0.5 ± 0.08

SONY CODE
EIAJ CODE
JEDEC CODE

(15.0)

A

26

(0.22)

1

+ 0.08

0.18 – 0.03

25

+ 0.2

1.5 – 0.1

+ 0.05

0.127 – 0.02

0.5 ± 0.2

0.1

0.1 ± 0.1

NOTE: Dimension “∗” does not include mold protrusion.

0° to 10°

DETAIL A

0.5 ± 0.2

LQFP-100P-L01

∗QFP100-P-1414-A

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT

LEAD MATERIAL
PACKAGE WEIGHT

EPOXY/PHENOL RESIN
SOLDER PLATING
42 ALLOY

– 56 –