Datasheet CXD2508AR, CXD2508AQ Datasheet (Sony)

CD Digital Signal Processor

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CXD2508AQ/AR

Description

The CXD2508AQ/AR is a digital signal processor for CD players and is equipped with built-in digital filters, no-sound data detection circuit, and 1-bit DAC.

Features

DSP block

• Digital PLL

• EFM frame sync protection

• SEC strategy-based error correction

• Subcode demodulation, CRC checking

• Digital spindle servo

• Servo auto sequencer

• Asymmetry compensation circuit

• Digital audio interface output

• 16K RAM

• Double-speed playback capability

• New microcomputer interface circuit

Digital filter, DAC block

• Double-speed playback capability

• Digital de-emphasis

• Digital attenuation

• No-sound data detection circuit

• 4 Fs oversampling filter

• Secondary ∆∑ noise shaper

• PWM-system pulse conversion output Recommended Operating Conditions

• Supply voltage VDD

• Operating temperature Note) VDD (min.) is varied by the playback speed and built-in

VCO in the CXD2508AQ/AR. 4.5V is the value using the VCO which generates the slower frequency in doublespeed playback. The table below shows the VDD (min.) for each condition.

Note)

4.5 to 5.5V (double-speed playback)

3.5 to 5.5V (normal-speed playback)

3.4 to 5.5V (low power consumption or special playback mode)

Topr –20 (min.) 75 (max.) °C

80 pin QFP (Plastic)

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.3 to 7.0 V

• Input voltage VI –0.3 to 7.0 V

• Input voltage

• Output voltage VO –0.3 to 7.0 V

• Storage temperature

• Supply voltage variation

CXD2508AQ

80 pin QFP (Plastic)

CXD2508AR

80 pin LQFP (Plastic)

VIN Vss–0.3V (min.) VDD+0.3 (max.) V

Tstg –40 to 125 °C

VSS–AVSS –0.3V (min.) +0.3V (max.) VDD–AVDD –0.3V (min.) +0.3V (max.)

Playback

speed

× 2 × 1

∗

× 1

∗

When the internal operation of the LSI is set to doublespeed mode and the crystal oscillation frequency is halved, normal-speed playback results.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

VCO

high-speed

3.40 4.50 3.40

3.40

3.40 3.40 3.40

VDD (min.) [V]

VCO

normal-speed

3.50

DAC block

3.40

– 1 –

E94602A54-ST

Pin Configuration

DTS1

V

XTAI

DTS2 DTS3

65 66 67 68

DD

69 70 71 72

73

74 75 76 77 78 79 80

ZEROL

ZEROR

NLPWM

LPWM AVDD2 AVDD3

XTAO AVss3 AVss2

NRPWM

RPWM

64

EMPHI

WFCK

63

62

DOUT

EMPH

61

60

C4M

59

FSTT

58

MNT0

57

MNT1

56

MNT3

55

C2PO

XROF

53

54

CXD2508AQ

Vss

52

RFCK

51

GFS

50

XPCK

49

XUGF

48

GTOP

47

BCKI

46

BCK

45

PCMD

PCMDI

44

LRCKI

43

42

LRCK

41

WDCK

CXD2508AQ/AR

ASYE

40

ASYO

39

ASYI

38

BIAS

37

RF

36

AVDD1

35

CLTV

34

AVss1

33

VDD

32

PCO

31

FILI

30

FILO

29

TEST

28

LOCK

27

MDS

26

MDP

25

EMPHI

WFCK

ZEROL

ZEROR

DTS1

V

NLPWM

LPWM AV

DD2

AVDD3

XTAI

XTAO AVss3 AVss2

NRPWM

RPWM

DTS2 DTS3

SCOR

SBSO

17

18

16

Vss

13

50

14

SEIN

RFCK

49

15

CNIN

GFS

48

DATO

XPCK

47

XLTO

6

5

7

MUTE

FSTT

57

SENS

56

8

XRST

MNT0

55

9

DATA

MNT1

54

10

XLAT

MNT3

53

12

11

CLOK

C2PO

XROF

52

51

CXD2508AR

2

1

SCOR

61 62 63

64

65

66

DD

67 68

69

70

71

72

73

74

75 76

77 78

79

80

3

SBSO

60

4

EXCK

EMPH

59

SQCK

SQSO

DOUT

58

C4M

CLKO

XUGF

46

SPOA

GTOP

45

19

BCKI

44

20

SPOB

BCK

43

21

XTSL

SPOC

PCMDI

42

22

XLON

LRCKI

PCMD

41

23

24

FOK

40 39 38

35

32

30 29 28

26

37 36

34 33

31

27

25 24

23 22 21

MON

LRCK WDCK ASYE ASYO ASYI BIAS RF AVdd1 CLTV AVss1 Vdd PCO FILI FILO TEST LOCK MDS MDP MON FOK

1

EXCK

2

SQSO

3

SQCK

4

MUTE

5

SENS

6

7

XRST

8

DATA

9

XLAT

10

CLOK

– 2 –

Vss

11

12

SEIN

13

CNIN

14

DATO

15

XLTO

16

CLKO

17

SPOA

18

SPOB

19

SPOC

20

XTSL

XLON

Block Diagram

63

EMPHI

LRCKI

PCMDI

BCKI

47

MUTE

BCK

PCMD

LRCK

WDCK

C2PO RFCK

MNT0 MNT1 MNT3

WFCK EMPH

62

GFS XUGF GTOP

43 45

46 44 42 41

52

58 57 56

64

51 49 48

54

CXD2508AQ/AR

ZEROR

ZEROL

XTAO

XTAI

65

66

74

73

NLPWM

69

LPWM

Digital Filter

+

1bit DAC

6

digital

OUT

digital

CLV

CPU

interface

SUB code Processor

error

corrector

D/A

Interface

16K RAM

EFM

demodulator

70 78 77

61

55 27 26

25 24

5 4 3

2 1

22 19 11 10

9 7

RPWM NRPWM

DOUT

XROF LOCK MDS MDP MON

SQCK SQSO EXCK SBSO SCOR XLON SPOA to C CLOK XLAT DATA SENS

Servo auto sequencer

23

FOK

13

SEIN

14

CNIN

XTSL

18

clock

generator

60

59

FSTT

C4M

36

RF

asymmetry

corrector

39

38

ASYI

ASYO

40

37

ASYE

BIAS

50

29

XPCK

digital

PLL

30

FILO

FILI

31

PCO

34

CLTV

Note) The pin numbers are for QFP. Refer to the Pin Description for those of LQFP.

– 3 –

17

16

15

CLKO

XLTO

DATO

Pin Description

CXD2508AQ/AR

Pin No.

RQ 79 80

10 11 12 13

1 2

1

3

2

4

3

5

4

6

5

7

6

8

7

9

8

10

9

11 12 13 14 15

Symbol

SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT CLOK VSS SEIN CNIN DATO

I/O

Outputs a high signal when either subcode sync S0 or S1 is detected.

O

Sub P to W serial output.

O

SBSO readout clock input.

I

Sub Q 80-bit serial output.

O

SQSO readout clock input.

I

High: mute; low: release

I

SENS output to CPU.

O

System reset. Reset when low.

I

Serial data input from CPU.

I

Latch input from CPU. Serial data is latched at the falling edge.

I

Serial data transfer clock input from CPU.

I

Description

GND. Sense input from SSP.

I

Track jump count signal input.

I

Serial data output to SSP.

O 14 15 16 17 18 19 20 21 22 23 24

25 26

27 28 29

16 17 18 19 20 21 22 23 24 25 26

27 28

29 30 31

XLTO CLKO SPOA SPOB SPOC XTSL XLON FOK MON MDP MDS

LOCK TEST

FILO FILI PCO

Serial data latch output to SSP. Latched at the falling edge.

O

Serial data transfer clock output to SSP.

O

Microcomputer extended interface (input A).

I

Microcomputer extended interface (input B).

I

Microcomputer extended interface (input C).

I

Crystal selection input. Low for 16.9344MHz; high for 33.8688MHz

I

Microcomputer extended interface (output).

O

Focus OK input. Used for SENS output and the servo auto sequencer.

I

Spindle motor on/off control output.

O

Spindle motor servo control.

O

Spindle motor servo control.

O

GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.

O

If GFS is low eight consecutive samples, this pin outputs low. TEST pin. Normally GND.

I

Master PLL (slave = digital PLL) filter output.

O

Master PLL filter input.

I

Master PLL charge pump output.

O 30 31 32

32 33 34

VDD AVSS1 CLTV

Digital power supply for DSP. Analog GND for DSP. Master PLL VCO control voltage input.

I

– 4 –

CXD2508AQ/AR

Pin No.

RQ

33

35

34

36

35

37

36

38

37

39

38

40

39

41

40

42

41

43

42

44

43

45

44

46

45

47

46

48

47

49

Symbol

AVDD1 RF BIAS ASYI ASYO ASYE WDCK LRCK LRCKI PCMD PCMDI BCK BCKI GTOP XUGF

I/O

Description

Analog power supply for DSP.

I

EFM signal input.

I

Constant current input of asymmetry compensation circuit.

I

Comparator voltage input of asymmetry compensation circuit.

O

EFM full-swing output (low = Vss, high = VDD).

I

Low: asymmetry compensation off; high: asymmetry compensation on.

O

D/A interface for 48-bit slot. Word clock (2Fs).

O

D/A interface for 48-bit slot. LR clock (Fs).

I

LR clock input for DAC. (48-bit slot)

O

D/A interface. Serial data (two's complement, MSB first).

I

Audio data input for DAC. (48-bit slot)

O

D/A interface. Bit clock.

I

Bit clock input for DAC. (48-bit slot)

O

GTOP output.

O

XUGF output. 48 49 50 51 52 53 54 55 56 57 58 59

60 61

62 63

50 51 52 53 54 55 56 57 58 59 60 61

62 63

64 65

XPCK GFS RFCK VSS C2PO XROF MNT3 MNT1 MNT0 FSTT C4M DOUT

EMPH EMPHI

WFCK ZEROL

O

XPLCK output.

O

GFS output.

O

RFCK output.

GND.

O

C2PO output.

O

XRAOF output.

O

MNT3 output.

O

MNT1 output.

O

MNT0 output.

O

2/3 frequency-divider output for Pins 73 and 74.

O

4.2336MHz output.

O

Digital Out output.

Outputs high signal when the playback disc has emphasis, low signal when no

O

emphasis.

I

DAC de-emphasis on/off. High: on; low: off.

O

WFCK (write frame clock) output.

No-sound data detection output; high when no sound data is detected.

O

(Left channel) 64 65

66

66 67

68

ZEROR DTS1

VDD

No-sound data detection output; high when no sound data is detected.

O

(Right channel)

I

Test pin 1 for DAC; normally low. Digital power supply for DAC.

– 5 –

CXD2508AQ/AR

Pin No.

Symbol

I/O

Description

RQ

67

69 68 69 70 71 72 73 74 75 76 77 78

70

71

72

73

74

75

76

77

78

79

80

NLPWM LPWM AVDD2 AVDD3 XTAI XTAO AVSS3 AVSS2 NRPWM RPWM DTS2 DTS3

O

Left channel PWM output. (Reverse phase)

O

Left channel PWM output. (Forward phase) Power supply for PWM driver. Power supply for crystal.

I

33.8688MHz crystal oscillation circuit input.

O

33.8688MHz crystal oscillation circuit output. GND for crystal. GND for PWM driver.

O

Right channel PWM output. (Reverse phase)

O

Right channel PWM output. (Forward phase)

I

DAC test pin 2; normally low.

I

DAC test pin 3; normally low.

Note)

• PCMD is an MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync

protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.

• GFS goes high when the frame sync and the insertion protection timing match.

• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µ.

• C2PO represents the data error status.

• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

– 6 –

CXD2508AQ/AR

Electrical Characteristics DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

NOTE)

Item

High level input voltage

Low level input voltage

Input voltage (1)Input voltage (2)Input voltage (3)Output voltage (1)Output voltage (2)Output voltage (3)Output voltage (4)

High level input voltage

Low level input voltage

Input voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

VIH (1)

VIL (1)

VIH (2)

VIL (2)

VIN (3)

VOH (1)

VOL (1)

VOH (2)

VOL (2)

Conditions

Schmitt input

Analog input

IOH = –4mA

IOL = 4mA

IOH = –2mA

IOL = 4mA

Min.

0.7VDD

0.8VDD

VSS

VDD–0.8

0

VDD–0.8

0

Typ.

Max.

0.3VDD

0.2VDD

VDD

0.4

VDD

0.4

Unit

V

Applicable

pins

∗1

∗2

∗3

∗4

∗5

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

Input leak current Tri-state pin output leak

current

VOH (3)

VOL (3)

VOH (4)

VOL (4)

ILI

ILO

IOH = –0.28mA

IOL = 0.36mA

IOH = –10mA

IOL = 10mA VI = 0 to 5.25V VO = 0 to 5.25V

VDD–0.5

0

VDD–0.4

0

VDD

0.4

VDD

0.4 ±5 ±5

V

V µA µA

∗1, ∗2, ∗3

Applicable pins

∗1

XTSL, DATA, XLAT, PCMDI, EMPHI, DTS1, DTS2, DTS3, SPOA, SPOB, SPOC

∗2

CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE, LRCKI, BCKI

∗3

CLTV, FILI, RF, BIAS, ASYI

∗4

MDP, PCO

∗5

ASYO, DOUT, FSTT, C4M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1, MNT3, ZEROL, ZEROR

∗6

FILO

∗7

LPWM, NLPWM, RPWM, NRPWM

∗8

SENS, MDS, MDP Note) "AVDD" refers to AVDD1, AVDD2, and AVDD3. In addition, "AVss" refers to AVss1, AVss2, and AVss3.

∗6

∗7

∗8

– 7 –

AC Characteristics

1) XTAI pin

(1) When using self-oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. Max. Unit

Oscillation frequency fMAX 15 34 MHz

(2) When inputting pulses to XTAI

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. Max. Unit

CXD2508AQ/AR

High level pulse width

Low level pulse width

Pulse cycle

Input high level

Input low level Rise time,

fall time

tWHX

tWLX

tCK

13 500

26 1,000

VIHX VDD – 1.0

VILX 0.8

tR, tF

tCX

tWHX

10

tWLX

ns

V

ns

IHX

V V

IHX × 0.9

XTAI

tr

(3) When inputting sine waves to XTAI via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. Max. Unit

Input amplitude V1 2.0 VDD + 0.3 Vp-p

– 8 –

V

DD/2

VIHX × 0.1

VILX

2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

CXD2508AQ/AR

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width

fCK

tWCK tSU tH tD tWL

fT fWT

CLK

DATA

XLT

EXCK

CNIN

SQCK

SUBQ SQCK

750 300 300 300 750

750

tSU

∗

1/fCX

tWCK tWCK

tH

tWT tWT

1/fr

tH

0.65

tD

MHz

ns ns ns ns ns

∗

MHz

ns

tWL

∗

In pseudo double-speed playback mode, when SL0 = SL1 = 1, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.

3) BCKI, LRCKI, and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol

BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time

BCKI

PCMDI

tW tSU tH tSU

Conditions

tW(BCKI)tW(BCKI)

VDD/2 VDD/2

tSU

(PCMDI)

Min.

94 18 18 18

tH

Typ.

Max. Unit

118 141 nsec

tsu

(LRCKI)

nsec nsec nsec

LRCKI

– 9 –

CXD2508AQ/AR

1-bit DAC Block Analog Characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)

Item

Total harmonic distortion

S/N ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

1kHz, 0dB data (using filter A)

Playback mode Normal speed Pseudo double-speed playback Normal speed Pseudo double-speed playback

Min.

87

83 For both items, Fs=44.1kHz The circuits for measuring the total harmonic distortion and S/N ratio are shown below.

4.7k

RPWM

NRPWM

11k

470p 470p

11k

4.7k

820p

4.7k

2700p

4.7k 560p

22µ

100

330k

Analog LPF Circuit

Typ.

Max.

0.015

0.025

SHIBASOKU (AM51A)

Audio Analyzer

Unit

%

dB

EFM

Signal

Generater

768Fs/384Fs (Normal speed/Pseudo double-speed playback)

RF

CXD2508AQ/AR

RPWM NRPWM NLPWM LPWM

Analog

Circuit

Rch A

Lch B

Block Diagram for Measuring Analog Characteristics

SHIBASOKU (AM51A)

Audio

Analyzer

– 10 –

CXD2508AQ/AR

Description of Functions

1. CPU Interface and Instructions

• CPU interface

This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.

750ns or more

CLOK

D1

DATA

D2 D3 D0 D1 D2 D3

750ns or more

Valid

300ns max

XLAT

Registers 4 to E

Data

Address

• Information on each address and the data is provided in Table 1-1.

• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2. Note) When XLAT is low, EXCK and SQCK must be set high.

– 11 –

CXD2508AQ/AR

Data 4

Data 3

Data 2

D0D3 D2 D1

D3 D2 D1

D0

D2 D1

D0 D3

—

17

—

2

4

8

16

32

64

128

256

512

1024

—

VCO

SEL

—

FSTT

SEL

0

AD0

AD1

AD2

AD3

AD4

AD5

AD6

—

DADS

—

Address Data 1

D3 D2 D1

D0

D1

D3 D2

D0

—

AS1 AS0

AS3 AS2

0

1

0

—

0.05ms 0.02ms

0.18ms 0.09ms 1

0

1

0

0.18ms 0.09ms 0.05ms

0.36ms

—

5.8ms 2.9ms 1.45ms

11.6ms

0

1

0

2048

16384 8192 4096

32768 1

1

0

—

WSEL

DOUT

ON/OFF

DOUT

MUTE

CD-

ROM

0

1

0

DSPB

ON/OFF

0 0 0

1

0

1

—

Mute ATT

0 0

0

1

0

1

—

SL 0 CPUSR 0

SL 1

1

0

1

—

Gain

MDS0

Gain

MDS1

Gain

MDP0

Gain

MDP1

0

1

—

Gain

CLVS

TB TP

DCLV

PWMmod

1

0

1

—

CM1 CM0

CM3 CM2

0

1

—

Table 1-1

Don't Use

1

Command

Auto sequence

name

Register

4

Command Table

Blind (A, E), Overflow (C)

Brake (B)

KICK (D)

Auto sequence (N)

track jump count setting

6

5

MODE specification

Function specification

Audio CTRL

Serial bus CTRL

8

9

A

B

– 12 –

Servo coefficient setting

CLV CTRL

CLV mode

TEST mode

F

C

E

D

CXD2508AQ/AR

Data 4

Data 3

Data 2

D0D3 D2 D1

D3 D2 D1

D0

D2 D1

D0 D3

—

07

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

1

0

—

0

—

1

—

0

—

1

—

1

—

1

—

1

—

1

—

1

—

0

—

Address Data 1

D3 D2 D1

D0

D1

D3 D2

D0

—

0

1

0

—

1

0

—

0

—

0

1

0

Table 1-2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Don't Use

0

1

0

1

0

1

Command

Auto sequence

name

4

Register

Reset Initialization

Blind (A, E), Overflow (C)

Brake (B)

KICK (D)

Auto sequence (N)

track jump count setting

5 0

6

MODE specification

Function specification

Audio CTRL

Serial bus CTRL

8

9

A

B

– 13 –

Servo coefficient setting

CLV CTRL

CLV mode

TEST mode

F

C

E

D

1-1. The meaning of the data for each address is explained below. $4X commands

CXD2508AQ/AR

Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE

AS3

0 0 1 1 1 1

AS2

0 1 0 0 1 1

AS1

0 1 0 1 0 1

AS0

0

1 RXF RXF RXF RXF

RXF = 0 FORWARD RXF = 0 REVERSE

• When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting Setting timers: A, E, C, B

Command

Blind (A, E), Over flow (C)

D3

0.18ms

D2

0.09ms

D1

0.05ms

D0

0.02ms

Brake (B)

0.36ms

0.18ms

0.09ms

Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)

A = E = C = 0.11ms B = 0.23ms

$6X commands

Auto sequence timer setting Setting timer: D

Command

KICK (D)

D3

11.6ms

D2

5.8ms

2.9ms

Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms

$7X commands

Auto sequence TRACK JUMP/MOVE count setting (N)

Data 1 Data 2

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Auto sequence track jump number setting

2152142132122112102928272625242322212

D1

0.05ms

D0

1.45ms

Data 3 Data 4

0

This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto sequence.

• The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is determined by the mechanical limitations of the optical system.

• The number of track jump is counted according to the signals input from CNIN pin.

– 14 –

$8X commands

CXD2508AQ/AR

Command

MODE specification

CDROM

Command bit

CDROM = 1

CDROM = 0

Command bit DOUT MUTE = 1 DOUT MUTE = 0

Command bit

DOUT ON-OFF = 1 DOUT ON-OFF = 0

Data 1

D3 D2 D1 D0

DOUT MUTE

DOUT

ON-OFF

WSEL

C2PO timing

1-3

CDROM mode; average value interpolation and pre-value hold are not performed.

Audio mode; average value interpolation and pre-value hold are performed.

D3 D2

000

Processing

Data 2

D1

Processing Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.

Processing Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin.

D0

VCO

SEL

Command bit

WSEL = 1 WSEL = 0

Command bit

VCOSEL = 1

VCOSEL = 0

$9X commands

Command

Function

specifications

Command bit

DSPB = 0

Sync protection window width ±26 channel clock

∗

±6 channel clock

∗

In normal-speed playback, channel clock = 4.3218MHz.

Processing

VCO for double-speed playback is selected.

VCO for normal-speed playback is selected.

Data 1

D3 D2 D1 D0

0

DSPB

ON-OFF

00

Normal-speed playback

Application Anti-rolling is enhanced. Sync window protection is enhanced.

Application Double-speed playback or low voltage

operation is possible. The selection is made for the normal

speed playback.

Data 2

D3 D2 D1 D0

000

FSTT

SEL

Processing

DSPB = 1

Command bit FSTTSEL = 0 FSTTSEL = 1

Double-speed playback

The clock with two-thirds frequency of crystal is output to FSTT pin. The clock with the sixth frequency of crystal is output to FSTT pin.

– 15 –

$AX commands

CXD2508AQ/AR

Data 1

Data 2

Command

D3 D2 D1 D0

Audio CTRL 0 0 Mute ATT

Command bit

Mute = 0 Mute = 1

Command bit

DADS = 0 DADS = 1

Mute off. Mute on. 0 data is output

from DSP.

Normal-speed playback for DAC block Double-speed playback for DAC block

Meaning

Processing

D3 D2 D1 D0

— — DADS —

Command bit

ATT = 0 ATT = 1

Attenuation off. –12dB

Meaning

In the case of using the crystal of 768Fs (Fs = 44.1kHz)

Digital Attenuation

The audio output level from DAC can be attenuated by setting AD6 to AC0 of register A. (with a built-in primary noise shaper)

Data 3

Data 4

Command

D2 D1 D0

D3 D2 D1 D0

Audio CTRL AD6 AD5 AD4

Command bit

AD6 to AD0

7F (H) 7E (H)

to

01 (H) 00 (H)

Audio output

0dB

–0.13dB

to

–42.144dB

–∞

AD3 AD2 AD1 AD0

The attenuation data consists of seven bits (AD6 to AC0), and 127 settings are possible. Audio output from 01 (H) to 7E (H) is determined according to the following formula:

Audio output = 20 log ( ) dB

attenuation data

128

Ex.) When the attenuation data is 7A(H)

Audio output=20 log ( ) dB = –0.417dB

122 128

Soft Mute

With soft mute function, when the attenuation data goes from 7F (H) (0dB) to 00 (H) (–∞) or vice versa, muting is turned on/off with a muting time of 1024/Fs [s] = 23.2 [ms] (Fs = 44.1kHz).

– 16 –

CXD2508AQ/AR

Attenuation Operation

Assume attenuation data X1, X2, and X3, where X1 > X3 > X2, and audio output Y1, Y2, and Y3, where Y1 > Y3 > Y2. First, assume X1 is transferred and then X2 is transferred. If X2 is transferred before Y1 is reached (state "A" in the diagram), then the value continues approaching Y2. Next, if X3 is transferred before Y2 is reached (either state "B" or "C" in the diagram), the value begins approaching Y3 from the current value at that point.

0dB

7F (H)

A

Y1

B

Y3

C

Y2

–∞

23.2 [ms]

00(H)

$BX commands

Command

Serial bus CTRL

D3

SL1

D2

SL0

D1

CPUSR

D0

0

This command switches the method of interfacing with the CPU. With the CDL500 series, the number of signal lines between the CPU and the DSP can be reduced in comparison with the CDL40 series. Also, the error rate can be measured with the CPU.

Command bits

Processing

SL1

0 0 1

SL0

0 1 0

Same interface mode as the CDL40 series. SBSO is output from SQSO pin. In other words, subcodes P to W are

read out from SQSO. Input the readout clock to SQCK. SENS is output from SQSO pin. Each output signal is output from SQSO pin.

1

Input the readout clock to SQCK. (See the Timing Chart 1-2.)

Command bits

Processing CPUSR = 1 CPUSR = 0

XLON pin is high. XLON pin is low.

– 17 –

$CX commands

CXD2508AQ/AR

Command

Servo coefficient setting

D3

Gain

MDP1

CLV CTRL ($DX)

• CLVS mode gain setting: GCLVS Gain

MDS1

0 0 0 0 1 1

Gain

MDS0

0 0 1 1 0 0

Gain

CLVS

0 1 0 1 0 1

GCLVS

–12dB

–6dB –6dB

0dB 0dB

+6dB

• CLVP mode gain setting: GMDP, GMDS

Gain

MDP1

Gain

MDP0

GMDP

D2

Gain

MDP0

D1

Gain

MDS1

Gain

MDS1

D0

Gain

MDS0

Gain

CLVS

Gain

MDS0

GMDS

0 0 1

0 1 0

–6dB

0dB

+6dB

0 0 1

0 1 0

–6dB

0dB

+6dB

– 18 –

$DX commands

CXD2508AQ/AR

Command

CLV CTRL

Command bit DCLV PWM MD = 1 DCLV PWM MD = 0

Command bit

TB = 0 TB = 1 TP = 0 TP = 1

$EX commands

D3

DCLV

PWM MD

D2

TB

D1 TP

D0

CLVS

Gain

See the $CX command.

Explanation (See the Timing Chart 1-3.) CLV PWM mode specified. Both MDS and MDP are used. CLV PWM mode specified. Ternary MDP values are output.

Explanation Bottom hold in CLVS mode at cycle of RFCK/32 Bottom hold in CLVS mode at cycle of RFCK/16 Peak hold in CLVS mode at cycle of RFCK/4 Peak hold in CLVS mode at cycle of RFCK/2

Command

CLV mode

CM3

0 1 1 1 1 0

CM2

0 0 0 1 1 1

CM1

0 0 1 1 1 1

D3

CM3

CM0

D2

CM2

D1

CM1

Mode 0 0 0 0 1 0

STOP

KICK

BRAKE

CLVS

CLVP

CLVA

D0

CM10

Explanation See the Timing Chart 1-4. See the Timing Chart 1-5. See the Timing Chart 1-6.

STOP : Spindle motor stop mode KICK : Spindle motor forward rotation mode BRAKE : Spindle motor reverse rotation mode CLVS : Rough servo mode. When RF-PLL circuit lock is disengaged, this mode is used to pull the disc

rotations within the RF-PLL capture range. CLVP : PLL servo mode. CLVA : Automatic CLVS/CLVP switching mode. This mode is normally used during playback.

– 19 –

If C2 Pointer = 1,

data is NG

CXD2508AQ/AR

Rch 16bit C1 Pointer Rch 16bit C2 Pointer

Lch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Rch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Timing Chart 1-1

LRCK

WDCK

C2P0

CDROM = 0

– 20 –

C2P0

CDROM = 1

C1F1 C1F2 C2F1 C2F2

CXD2508AQ/AR

XRAOF

750ns or more

(1500ns or more in low power consumption mode)

C2 correction status

No Error

Single error correction

Irretrievable error

0

1

C2F2

0

1

C2F1

C1 correction status

No Error

Single error correction

Irretrievable error

0

1

C1F2

0

1

C1F1

$BC latch

Timing Chart 1-2

Set SQCK and EXCK high during this interval.

XLAT

Internal signal latch

SPOA SPOB SPOC XTSL WFCK SCOR GFS GTOP EMPH FOK LOCK RFCK

SQCK

SQSO

– 21 –

Timing Chart 1-3

DCLV PWM MD = 0

CXD2508AQ/AR

MDS

MDP

DCLV PWM MD = 0

MDS

MDP

Acceleration

132kHz

7.6µs

n • 236 (ns) n = 0 to 31

Acceleration

Z

Deceleration

n • 236 (ns) n = 0 to 31

Timing Chart 1-4

DCLV PWM MD = 0

MDS

MDP

MON

DCLV PWM MD = 1

MDS

MDP

STOP

Z

L

STOP

L

MON

L

– 22 –

Timing Chart 1-5

DCLV PWM MD = 0

CXD2508AQ/AR

KICK

MDS

MDP

MON

DCLV PWM MD = 1

MDS

MDP

MON

Z

H

Z

7.6µs

H

KICK

H

L

H

– 23 –

Timing Chart 1-6

DCLV PWM MD = 0

CXD2508AQ/AR

BRAKE

MDS

MDP

MON

DCLV PWM MD = 1

MDS

MDP

MON

Z

H

Z

H

– 24 –

CXD2508AQ/AR

1-2. Description of SENS Output

The following signals are output from SENS, depending on the microcomputer serial register value (latching not required).

Microcomputer serial register

value (latching not required)

SENS

output

Meaning

$0X, 1X, 2X, 3X $4X

$5X $6X $AX

$EX $7X, 8X, 9X, BX, CX,

DX, FX

SEIN XBUSY

FOK SEIN GFS

OV64

"L"

SEIN, a signal input to the this IC from the SSP, is output. Low while the auto sequencer is in operation, high when operation terminates. Outputs the signal input to the FOK pin. Normally, FOK (from RF) is

input. High for "focus OK". SEIN, a signal input to this IC from the SSP, is output. High when the played back frame sync is obtained with the correct

timing. Low when the EFM signal, after passing through the sync detection filter,

is lengthened by 64 channel clock pulses or more. SENS pin is fixed low.

Note that the SENS output can be read from SQSO pin when SL1 = 1 and SL0 = 0. (See the $BX commands.)

2. Subcode Interface

This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2508AQ/AR. Sub Q can be read out after the CRC check of the 80 bits data in the subcode frame. This accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from SQSO pin.

2-1. P to W Subcode Read

Data can be read out by inputting EXCK immediately after WFCK falls. (See Fig. 2-1.) Also, SBSO can be read out from SQSO pin when SL1 = 0 and SL0 = 1. (See the $BX commands.)

2-2. 80-bit Sub Q Read

Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.

• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.

• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high 400µs or more later (monostable multivibrator time constant) after the subcode is read out, the CPU determines that new data (which passed the CRC check) has been loaded.

• In the CXD2508AQ/AR, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In the CXD2508AQ/AR, the SQCK input is detected, and when it is low the retriggerable monostable multivibrator is reset.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration of SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register.

• While the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by CRCOK and others.

• Fig. 2-3 shows Timing Chart.

• Although a clock is input from SQCK pin to actually perform these operations, the high and low intervals for

this clock should be between 750ns and 120µs.

– 25 –

Timing Chart 2-1

Interrel PLL clock

4.3218 ±∆MHz

WFCK

SCOR

EXCK

CXD2508AQ/AR

400ns max

SBSO

WFCK

SCOR

EXCK

SBSO

S0 • S1 Q R

S0•S1 Q R S T U V W

Same Same

S0•S1 P1 Q R S T U V W P1 P2 P3

Subcode P.Q.R.S.T.U.V.W Read Timing

– 26 –

ADDRS CTRL

CXD2508AQ/AR

SO

SQCK

8

SQSO

LD

(AMIN)

8

80bit S/P Register

8

LD

80bit S/P Register

LD

SHIFT

Mono/Multi

CRCF

Mix

(ASEC)

(AFRAM)

Block Diagram 2-2

8

A B C D E F G H

SIN

SUBQ

Order

Inversion

CRCC

SUBQ

LD

H G F E D C B A

SI

– 27 –

CTL3

CXD2508AQ/AR

98

95 96 97

91 92 93 94

CRCF2

CTL2

CTL1

L

CTL0

3

ADR3

2

1

Determined by mode

270 to 400µs for SQCK = High

ADR2

80 Clock

Order

Inversion

3

2

1

CRCF1

WFCK

SCOR

SQSO

Registere load forbidder

SQCK

750ns to 120µs

Mono/multi (Interral)

SQCK

ADR1

ADR0

CRCF

SQSO

300ns max

Timing Chart 2-3

– 28 –

CXD2508AQ/AR

3. Description of Other Functions

3-1. Channel Clock Regeneration by Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is demodulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is channel clock, is required. In an actual player, the fluctuation in the spindle rotation alters the width of the EFM signal pulses, making a PLL necessary for regenerating channel clock.

The block diagram of this PLL is shown in Fig. 3-1. The CXD2508AQ/AR has a built-in two-stage PLL as shown in the diagram.

• The first-stage PLL generates a high-frequency clock needed by the second-stage digital PLL.

• The second-stage PLL is a digital PLL that regenerates the actual channel clock, and has a ±250kHz (normal

state) or more capture range.

Block Diagram 3-1

X'tal

OSC

Digital PLL

I/N

I/M

VCO

RFPLL

Phase

comparator

PCO

FILI

FILO

CLTV

V

DD

– 29 –

CXD2508AQ/AR

3-2. Frame Sync Protection

• In a CD player operating at normal speed, a frame sync is recorded approximately every 136µs (7.35kHz).

This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame sync can not be recognized, the data is processed as error data because it can not be recognized what the data is. As a result, recognizing the frame sync properly is extremely important for improving playability.

• In the CXD2508AQ/AR, window protection and forward protection/backward protection have been adopted

for frame sync protection. The adoption of these functions achieves very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter is fixed to 3. In other words, when the frame sync is being played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted. If frame sync can not be detected for 13 frames or more, the window is released and the frame sync is resynchronized. In addition, immediately after the window is released and resynchronization is executed, if a proper frame sync can not be detected within 3 frames, the window is released immediately.

3-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.

• The CXD2508AQ/AR SEC strategy provides excellent playability through powerful frame sync protection and

C1 and C2 error corrections.

• The correction status can be monitored outside the LSI.

See Table 3-1.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held for that

data, or an average value interpolation was made.

MNT3

0 0 0 1 1 1

MNT1

0 0 1 0 0 1

MNT0

0 1 1 0 1 1

Table 3-1.

Description No C1 errors One C1 errors corrected C1 correction impossible No C2 errors One C2 errors corrected C2 correction impossible

– 30 –

Timing Chart 3-2

Normal-speed PB

RFCK

MNT3

MNT1

MNT0

CXD2508AQ/AR

400 to 500ns

t = Dependent on error

condition

C1 correction C2 correction

C4M

MNTO, 1, 3

Strobe

Valid

Invalid

Strobe

3-4. DA Interface

• The CXD2508AQ/AR DA interface is as described below.

This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.

– 31 –

24

CXD2508AQ/AR

23456789101112

Rch MSB

24

LO

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB

Lch MSB (15)

Timing Chart 3-3

1

LRCK

(44.1k)

BCK

(2.12M)

WDCK

48bit slot Normal-Speed Playback

RO

PCMD

– 32 –

12

48bit slot Double-Speed Playback

LRCK

(88.2k)

BCK

(4.23M)

WDCK

RO

PCMD

CXD2508AQ/AR

3-5. Digital Out

There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2508AQ/AR supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3) of channel status.

Digital Out C bit

0

12 34 56 78 9101112131415

0

16

32

48

From sub Q

COPY

Emph

ID1

ID0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 0 0 0

0

176

bit0 to 3 – Sub Q control bits that matched twice with CRCOK

Table 3-2.

3-6. Servo Auto Sequencer

This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and N track move are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but they can be sent to the CXD2508AQ/AR. Connect the CPU, RF and SSP as shown in Fig. 3-4. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).

– 33 –

CXD2508AQ/AR

(a) Auto Focus ($47)

Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-5. The auto focus starts with focus search up, and the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E.

Connection diagram for using auto sequencer (example)

RF

SSP

FOK

C. out SENS DATA

CLK

XLT

FOK

CXD2508A

CNIN SEIN DATO CLKO XLTO

Fig. 3-4.

Auto focus

Focus search up

DATA CLOK

XLAT

SENS

Micro-computer

FOK = H

YES

FZC = H

YES

FZC = L

YES

Focus servo ON

END

NO

(Checks whether FZC is continuously high or not for the period of time E set in register 5)

NO

Fig. 3-5-(a). Auto Focus Flow Chart

– 34 –

XLT

FOK

SEIN (FZC)

BUSY

CXD2508AQ/AR

$47latch

Command

for SSP

$03

Blind E

$08

Fig. 3-5-(b). Auto Focus Timing Chart

(b) Track Jump

1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and the sled servo are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed.

• 1-track jump When $48 ($49 for REV) is received from the CPU, an FWD (REV) 1-track jump is performed in accordance with Fig. 3-6. Set blind A and brake B with register 5.

• 10-track jump When $4A ($4B for REV) is received from the CPU, an FWD (REV) 10-track jump is performed in accordance with Fig. 3-7. The principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. In addition, after kicking the actuator, 5 tracks have been counted through CNIN, and the brake is applied to the actuator. Then, the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set in register 5), and the tracking and sled servos are turned on.

• 2N-track jump When $4C ($4D for REV) is received from the CPU, an FWD (REV) 2N-track jump is performed in accordance with Fig. 3-8. The track jump count "N" is set in register 7. Although N can be set to 216tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6.

• N-track move When $4E ($4F for REV) is received from the CPU, an FWD (REV) N-track move is performed in accordance with Fig. 3-9. N can be set to a maximum of 216tracks. CNIN is used for counting the number of jumps. This N-track move uses a method in which only the sled is moved, and is suited for moves over thousands of tracks.

– 35 –

Track

CXD2508AQ/AR

Track kick sled servo

WAIT

(Blind A)

CNIN =

YES

Track REV

kick

WAIT

(Brake B)

Track sled

servo ON

END

(REV kick for REV jump)

NO

(FWD kick for REV jump)

Fig. 3-6-(a). 1-Track Jump Flow Chart

XLT

CNIN

BUSY

Command

for SSP

$48 (REV = $49) latch

Blind A

$28 ($2C)

Brake B

$2C ($28)

Fig. 3-6-(b). 1-Track Jump Timing Chart

$25

– 36 –

10 Track

Track, sled

FWD kick

CXD2508AQ/AR

WAIT

(Blind A)

CNIN=5 ?

YES

Track, REV

kick

C = Overflow ?

YES

Track sled

servo ON

END

(Counts CNIN × 5)

NO

(Checks whether the CNIN

NO

cycle is longer than overflow C)

Fig. 3-7-(a). 10-Track Jump Flow Chart

XLT

CNIN

BUSY

Command

for SSP

$4A (REV = $4B) latch

Blind A

$2A ($2F)

Fig. 3-7-(b). 10-Track Jump Timing Chart

CNIN 5count

$2E ($2B)

Overflow C

$25

– 37 –

2N Track

Track, sled

FWD kick

WAIT

(Blind A)

CXD2508AQ/AR

CNIN = N

Track REV

kick

C = Overflow

Track servo

ON

WAIT

(Kick D)

Sled servo

ON

END

NO

YES

NO

YES

Fig. 3-8-(a). 2N-Track Jump Flow Chart

XLT

CNIN

BUSY

Command

for SSP

$4C (REV = $4D) latch

Blind A

$2A ($2F)

CNIN

N count

$2E ($2B)

Overflow

$26 ($27)

Fig. 3-8-(b). 2N-Track Jump Timing Chart

– 38 –

Kick D

$25

N Track move

Track servo OFF

Sled FWD kick

WAIT

(Blind A)

CXD2508AQ/AR

XLT

CNIN

$4E (REV = $4F) latch

CNIN = N

YES

Track, sled

servo ON

END

NO

Fig. 3-9-(a). N-Track Move Flow Chart

BUSY

Command

for SSP

$22 ($23)

Blind A

CNIN N count

$25

Fig. 3-9-(b). N-Track Move Timing Chart

– 39 –

CXD2508AQ/AR

3-7. Digital CLV

Fig. 3-10 shows the Block Diagram. Digital CLV makes PWM output in CLVS and CLVP with the MDS error and MDP error signal sampling frequency increased to 130kHz during normal-speed operation. In addition, the digital spindle servo can set the gain.

Digital CLV

CLVS U/D

MDS Error

MDP Error

Gain

0, –6dB

CLVS P/S

KICK, BRAKE STOP

2/1 MUX

Measure

GS (Gain)

Over Sampling

Filter-2

Noise Shape

Modulation

1/2

Mux

CLV-P/S

Measure

Over Sampling

Filter-1

GP (Gain)

CLV P

CLV S

Mode Select

Fig. 3-10. Block Diagram

– 40 –

DCLVMD

MDP

MDS

3-8. Asymmetry Compensation

Fig. 3-11 shows the Block Diagram and Circuit Example.

ASYE

CXD2508AQ/AR

ASYO

ASYI

R2 2

=

R1 5

RF

BIAS

R1

R2

R1

Fig. 3-11. Example of Asymmetry Compensation Application Circuit

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 41 –

CXD2508AQ/AR

3-9. Setting Method of the CXD2508AQ/AR Playback Speed

(a) Signal processing block (DSP block)

The playback mode shown below can be selected by the combination of crystal, XTSL pin and doublespeed command (DSPB) in the CXD2508AQ/AR.

Playback mode at DSP block

Mode

1 2 3 4

∗1

5

Crystal

768Fs 768Fs 384Fs 384Fs 384Fs

XTSL

1 1 0 0 1

DSPB

0 1 0 1 1

Speed at DSP block

× 1 × 2 × 1 × 2 × 1

Fs = 44.1kHz

∗1

Low power consumption mode. The processing speed is halved in the LSI so that the power consumption can be decreased.

(b) DAC block

The operating speed at DAC block is determined by the crystal and the double-speed command DADS in DAC block in spite of the operating conditions of DSP block mentioned above. Then, the playback mode for DAC block and DSP block can be determined independently. (For example, normal-speed playback for DSP block; low power consumption playback for DAC block.) The DAC block supports the normal speed and double speed.

∗

DADS is controlled by sending the command to DSP block.

Playback mode at DAC block

Mode

1 2

∗2

3

∗2

Low power consumption mode. The processing speed is halved in the LSI so that the power consumption

Crystal

768Fs 768Fs 384Fs

DADS

0 1 1

Speed at DAC block

× 1 × 2 × 1

can be decreased.

– 42 –

CXD2508AQ/AR

4. 1-bit DAC Block

4-1. PWM Output Pattern

In the CXD2508AQ/AR, PWM outputs from the DAC include forward phase PWM (RPWM, LPWM) and inverted PWM (NRPWM, NLPWM). By determining the difference between these PWM outputs in the subsequent analog LPF, the noise and others can be canceled in the digital block. In addition, this method also yields improvements in the analog characteristics. The PWM output waveforms differ for each of the CXD2508AQ/AR three playback modes (normal, doublespeed, and pseudo double-speed). (In the following explanation, Fs = 44.1kHz.) During normal speed playback (DSPB = 0, crystal = 768Fs), eleven values (integers from –5 to 5) are taken within the 32Fs cycle. The minimum pulse width is –5, and the maximum pulse width is +5. The minimum variation width of change for PWM is the 384 Fs cycle. (See Fig. 4-3.)

LPWM

(RPWM)

Noise shaper output value

NLPWM

(NRPWM)

5 4 3 • • • • • •

33.8688 [MHZ] (768Fs)

–3 –4 –5

1.4112 [MHZ] (32Fs)

–5 –4 –3 • • • • • • 3 4 5

Fig. 4-1.

In double-speed playback (DSPB = 1, crystal = 768Fs), five values (–4, –2, 0, 2, 4) are taken within the 64Fs cycle. (See Fig. 4-4.)

4 2 0 –2 –4

LPWM

(PRWM)

–4 –2 0 2 4

2.8224 [MHz] (64Fs)

33.8688 [MHz] (768Fs)

Fig. 4-2.

In pseudo double-speed playback (DSPB = 1, crystal = 384Fs), five values (–4, –2, 0, 2, 4) are taken within the 32Fs cycle. (See Fig. 4-5.)

16.9344 [MHz]

4 2 0 –2 –4

LPWM

(RPWM)

(384Fs)

–4 –2 0 2 4

1.4112 [MHz] (32Fs)

Fig. 4-3.

4-2. Input Timing for DAC Block

Fig. 4-4 shows the input timing for DAC section. In the CXD2508AQ/AR, there is no internal transfer of sound data from the CD signal processing block to DAC block. Therefore, data can be transferred to DAC block through an audio DSP and others. When data is input to DAC block without passing through an audio DSP or similar device, data should be connected externally. In that case, EMPH, LRCK, and PCMD can be connected directly with EMPHI, LRCKI, and PCMDI respectively. (See the Application Circuit.)

– 43 –

24

CXD2508AQ/AR

RMSB

23456789101112

1

Rch MSB

24

LO

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0

Fig. 4-4. Input Timing for DAC Block

Lch MSB (15)

2 1

BCKI

LRCKI

(44.1k)

Normal-Speed Playback

(2.12M)

RO

PCMDI

LRCKI

Double-Speed Playback

(88.2k)

– 44 –

BCKI

(4.23M)

RO

PCMDI

CXD2508AQ/AR

4-4. Description of Functions

No-Sound Data Detection The no-sound data detection function detects low-level data on both the left and right channels in audio data from the 1Fs 48-bit slot and outputs a zero detection signal when that data continues unchanged for a certain period of time. The audio data is in two's complement format and data in which the upper 12 bits are all "0" or all "1" is regarded as low level data. When this data continues unchanged for 32,768 samples (743ms when Fs =

44.1kHz), the zero detection signal is output. In other words, once a certain period of time during which lowlevel data is detected elapses, the signal is regarded to be in the no-sound state. The zero detection signal is output from ZEROL (left channel) and ZEROR (right channel) pins. The zero detection output timing is shown in Fig. 4-5.

Lch Rch

LRCK

32,768th sample of

low-level data

32,768th sample of

low-level data

ZEROR and ZEROL

LRCK

ZEROL

ZEROR

Lch Rch Lch Rch Lch Rch Lch Rch Lch

Low-level dataLow-level dataLow-level dataLow-level dataLow-level dataSound dataSound dataLow-level dataLow-level data

Fig. 4-5. Zero Detection Output Timing

– 45 –

CXD2508AQ/AR

Forced Mute

The forced mute can be executed independently for DSP block and DAC block. DSP can be forcibly muted by setting "1" in MUTE for D1 of register A. This mute can be released by setting "0" in MUTE for D1 of register A. Also, the both of left and right channels can be forcibly muted by inputting a high signal to MUTE pin for DAC block (in this event, a soft mute is not performed). In this instance, a fixed pattern is output for the PWM output. To release the mute, input a low signal to MUTE pin.

Digital De-emphasis

When EMPHI pin (Pin 63) is set high, de-emphasis can be applied by using the IIR filter. However, in normalplayback mode the time constants are as follows:

τ1 = 50µs, τ2 = 15µs.

– 46 –

Application Circuit

GND

ZEROR

ZEROL

CXD2508AQ/AR

to CPU

LDON

FOK

SENS

XRST DATA XLAT

CLK

GFS SQSO SQCK SCOR MUTE COUT

V

DD

GND

79

80

78

76

75

77

DTS2

DTS3

SCOR

1

SBSO

2

EXCK

3

SQSO

4

SQCK

5

6

MUTE SENS

7

XRST

8

DATA

9

XLAT

10

CLOK

11

Vss

12

SEIN

13

CNIN

14

DATO

15

XLTO

16

CLKO

17

SPOA

18

SPOB

19

SPOC

20

XTSL

21

XLON

22

FOK

23

MON

24

MDS

MDP

26

25

27

RPWM

TEST

LOCK

28

AVss2

NRPWM

FILO

29

30

74

AVss3

FILI

31

PCO

72

73

3

DD

XTAI

XTA0

AV

CXD2508AQ

1

SS

AV

VDO

32

33

71

34

70

2

DD

AV

CLTV

35

69

LPWM

1

DD

AV

36

68

DD

V

NLPWM

BIAS

RF

37

67

38

66

DTS1

ASYI

39

65

ZEROL

ZEROR

ASYE

ASYO

40

WFCK

EMPHI

EMPH DOUT

C4M

FSTT MNT0 MNT1 MNT3

XROF

C2PO

Vss

RFCK

GFS

XPCK

XUGF GTOP

BCKI

BCK

PCMDI

PCMD LRCKI

LRCK

WDCK

64

WFCK

63 62

61

DOUT

60 59

GND

MNT0 MNT1 MNT2 MNT3

GND

to error rate counter

58 57

56 55

XROF

54 53 52

RFCK

51

GFS

50

XPCK

49

XUGF

48

GTOP

47 46 45

44 43 42

41

WDCK

LDON

SSP

GND

RF

DR IVER

GND

RF

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 47 –

Package Outline Unit: mm

CXD2508AQ

CXD2508AQ/AR

80PIN QFP (PLASTIC)

65

80

64

1

SONY CODE EIAJ CODE JEDEC CODE

0.8

23.9 ± 0.4

20.0 – 0.1

0° to 10°

DETAIL A

+ 0.4

0.12

QFP-80P-L01

∗QFP080-P-1420-A

41

40

25

24

+ 0.15

0.35 – 0.1

M

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

+ 0.4

14.0 – 0.1

17.9 ± 0.4

2.75 – 0.15

+ 0.1

0.15 – 0.05

+ 0.35

EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY

1.6g

A

+ 0.2

0.1 – 0.05

0.15

16.3

0.8 ± 0.2

CXD2508AQ

65

80

SONY CODE EIAJ CODE JEDEC CODE

80PIN QFP (PLASTIC)

24.0 ± 0.3 + 0.4

20.0 – 0.1

4164

40

+ 0.4

14.0 – 0.1

25

1

0.8 ± 0.12

22.6

24

+ 0.15

0.35 – 0.1

M

PACKAGE STRUCTURE

PACKAGE MATERIAL

QFP-80P-L121

∗QFP080-P-1420-AX

LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT

0.15 – 0.05

18.0 ± 0.3

2.7 ± 0.1

3.1 MAX

+ 0.1

0.7 ± 0.1

+ 0.2

0.1 – 0.05

0° to 10°

EPOXY RESIN

SOLDER PLATING

42 ALLOY

1.6g

16.6

0.15

– 48 –

CXD2508AQ

CXD2508AQ/AR

QFP 80PIN (PLASTIC)

23.9 ± 0.2

∗20.0 ± 0.2

64

65

41

40

0.8

0.15 ± 0.05

CXD2508AR

17.9 ± 0.2

∗14.0 ± 0.2

80

1

0.35 ± 0.1

C1.2

15°

NOTE: Dimension “∗” does not include mold protrusion.

SONY CODE EIAJ CODE JEDEC CODE

0.15

QFP-80P-L051

∗QFP080-P-1420-AH

M

80PIN LQFP (PLASTIC)

14.0 ± 0.2

∗ 12.0 ± 0.1

60

61

41

4 – 1.0

25

24

4 – 0.8

+ 0.20

2.7 – 0.16

2.94 ± 0.15

0.24 ± 0.15

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

40

15°

1.45

0° to 10°

DETAIL A

EPOXY RESIN SOLDER PLATING

42 ALLOY

1.6g

A

15°

0.8 ± 0.15

1.95 ± 0.15

0.5 ± 0.08

SONY CODE EIAJ CODE JEDEC CODE

80

1

0.1 ± 0.1

0° to 10°

0.18 – 0.03

DETAIL A

LQFP-80P-L01

∗QFP080-P-1212-A

+ 0.08

0.5 ± 0.2

A

21

(0.22)

20

+ 0.2

1.5 – 0.1

NOTE: Dimension “∗” does not include mold protrusion.

+ 0.05

0.127 – 0.02

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY / PHENOL RESIN

SOLDER PLATING

42 ALLOY

0.5g

– 49 –

(13.0)

0.5 ± 0.2

0.1