Datasheet CXD2093Q Datasheet (Sony)

Digital Comb Filter (NTSC)

Description

The CXD2093Q is an adaptive intra-field three lines comb filter for NTSC systems, and can provide high-precision Y/C separation with a single chip.

Features

• Adaptive intra-field three lines comb filter

• For NTSC

• Vertical enhancer

• Horizontal aperture correction

• 8-bit A/D converter (1-channel)

• 8-bit D/A converter (2-channel)

• 4× PLL

• Sync tip clamp

Applications

Y/C separation for color TVs and VCRs

Structure

Silicon gate CMOS ICStructure

Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)

• Supply voltage DVDD VSS – 0.5 to +7.0 V

DAVD VSS – 0.5 to +7.0 V ADVD VSS – 0.5 to +7.0 V PLVD VSS – 0.5 to +7.0 V CLVD VSS – 0.5 to +7.0 V

• Input voltage VI VSS – 0.5 to VDD + 0.5 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Storage temperature

Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage DVDD 5.0 ± 0.25 V

DAVD 5.0 ± 0.25 V ADVD 5.0 ± 0.25 V PLVD 5.0 ± 0.25 V CLVD 5.0 ±0.25 V

• Analog input ADIN 1.75 Vp-p

• Operating temperature

Topr –20 to +70 °C

– 1 –

E99537-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2093Q

48 pin QFP (Plastic)

– 2 –

CXD2093Q

Pin Configuration

Block Diagram

FIN

CKSL

PLSL

MCKO

ADCK

CPO

PLVS

VCV

PLVD

CLVD

CLPEN

CLVS

DV

SS

DVSS

VEH1

VEH2

VEH3

MOD1

DV

SS

MOD2

DV

DD

TEST

VB

IRF

DV

SS

TEST

DV

DD

TEST

TRAP

APCN

DV

SS

TEST

DV

DD

DV

SS

DV

SS

CLPO

ADIN

RB

ADVS

ADVD

RT

ACO

DAVD

AYO

DAVS

VG

VRF

2

3

4

5

6

9

10

11

121

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

8

7

A/D

Clamp

1H DL

Logical operation

Adaptive

filter

operation

DL D/A

ADIN

D/A

CLPO

AYO

ACO

VCO 1/4

SW

Phase

comparator

1/2

SW

4fsc

CPO VCV PLSL FIN CKSL

Vertical

enhancement circuit

2

1

7

9

39

38

37

44

42

1H DL

– 3 –

CXD2093Q

Pin Description

CLPO

ADIN RB ADVS ADVD RT

ACO

DAVD

AYO

DAVS VG VRF

IRF VB TEST

DVDD DVSS

VEH3 VEH2 VEH1 DVSS DVSS DVSS DVSS DVDD

O

I

O — —

O

—

O

—

O

I

O

I — —

I

I — — — — —

1

2 3 4 5 6

7

8

9

10 11 12

13 14 15

16 18

20 21 22 23 24 25 26 27

Internal clamp circuit current output. Connect to ADIN when using the internal clamp. Leave this pin open when not in use.

Comb filter analog input (A/D converter input). Reference bottom voltage for the A/D converter (0.52V typ.). A/D converter analog ground. A/D converter analog power supply. (5.0V) Reference top voltage for the A/D converter (2.60V typ.). Analog chroma signal output.

Output can be obtained by connecting a resistor between this pin and the analog ground.

D/A converter analog power supply. (5.0V) Analog luminance signal output.

Output can be obtained by connecting a resistor between this pin and the analog ground.

D/A converter analog ground. D/A converter related pin. Connect a capacitor of approximately 0.1µF between

this pin and the analog power supply (DAVD). Sets the full-scale value of the Y and C-channel D/A converter output signal. Connect a resistor of “16R” (16 times the output resistor “R” of the D/A converter). D/A converter related pin.

Connect to the analog ground (DAVS) via a capacitor of approximately 0.1µF. Test pin. Normally fix to “Low”. Digital power supply. (5.0V) Digital ground. Y/C separation mode setting. MOD2 MOD1

L L Adaptive processing mode H L BPF separation mode H H Through mode

Vertical enhancement setting. Can be set in 8 stages from VEH3 VEH2 VEH1: LLL (off) to HHH (max.)

Digital ground. Digital ground. Digital ground. Digital ground. Digital power supply. (5.0V)

No.

Symbol I/O Description

17

19

MOD2

MOD1

I

– 4 –

CXD2093Q

28 29 30 31 32 33 34 35 36

37

38

39

40 41 42 43 44 45 46 47 48

Test pin. Normally fix to “Low”. Digital ground. Horizontal aperture correction circuit setting. Low: Off, High: On. Trap filter setting. Low: Off, High: On. Test pin. Normally open or fix to “Low”. Test pin. Normally open or fix to “Low”. Digital power supply. (5.0V) Test pin. Normally open or fix to “Low”. Digital ground. Clock input. Input the burst-locked fsc (2fsc) when using the internal PLL.

Input the burst-locked 4fsc when not using the internal PLL. PLL control.

Low: The internal PLL is not used. The clock (4fsc) which is input to FIN is

supplied internally.

High: The internal PLL is used. VCO oscillation output 4fsc clock is supplied

internally.

Selects the clock input to FIN. Low: fsc, High: 2fsc. When inputting 4fsc to FIN (when not using the internal PLL), this pin may be set to either “Low” or “High”.

Clock (4fsc) output. Clock input for A/D converter. Normally connect to MCKO. PLL phase comparator output. Leave open when not using the PLL. PLL analog ground. VCO control voltage input. Connect to PLVS when not using the PLL. PLL analog power supply. (5.0V) Clamp D/A converter analog power supply. (5.0V) Clamp circuit enable pin. Low: Clamp on, High: Clamp off. Clamp D/A converter analog ground.

Pin No.

Symbol I/O Description

I

—

I I I I

—

I

—

I

O

I

O

—

I — —

I —

TEST DVSS APCN TRAP TEST TEST DVDD TEST DVSS

FIN

CKSL

PLSL

MCKO ADCK CPO PLVS VCV PLVD CLVD CLPEN CLVS

– 5 –

CXD2093Q

Electrical Characteristics

DC Characteristics (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +70°C)

∗1

All pins

∗2

All pins other than

∗6

∗3

All input pins other than

∗6

∗4

All output pins other than

∗5

CPO (Pin 42)

∗6

FIN (Pin 37)

∗7

All input pins other than

∗8

Pins 32, 33 and 35

∗9

MCKO (Pin 40)

Supply voltage —

4.75

–20

—

Vss

0.7VDD

0

VDD – 0.8

0.5

250k

–10

40

3.0

DVDD DAVD ADVD PLVD CLVD Topr IDD VI, VO VIH VIL

tr, tf

VOH

VOL

VIN RFB IIL, IIH IIH

—

5.0

85

1M

100

9.0

5.25

+70 120 VDD

0.3VDD 500

0.4

2.5M 10

240

18.0

V

°C

mA

V

ns

V

Vp-p

Ω

µA

ns

∗1

—

∗2

∗3

∗1 ∗4 ∗5 ∗4 ∗5

∗6

∗7 ∗8 ∗9

Operating temperature Supply current Input/output voltage

Input voltage

Input rise/fall time

Output voltage

Clock input amplitude Feedback resistance value

Input leak current

Clock amplifier output delay

—

Clock 14.3MHz

—

CMOS level input

— IOH = –2mA IOH = –3mA IOL = 4mA IOL = 1.5mA fmax = 50MHz sine wave VIN = Vss or VDD VIN = Vss or VDD VIH = VDD

—

Applicable pins

Item

Symbol

Measurement

conditions

Min. Typ. Max. Unit

– 6 –

CXD2093Q

I/O Pin Capacitance

(Ta = 25°C, f = 1MHz, VIN = VOUT = 0V)

Internal 8-bit A/D Converter Characteristics

(VDD = 5V, Ta = 25°C, f = 10MHz)

Item Input pin capacitance Output pin capacitance

Symbol CIN COUT

Min.

— —

Min.

— —

Max.

9

11

Unit

pF

Item Resolution Max. conversion speed Analog input bandwidth

Self bias

Output data delay Differential linearity error Integral linearity error

Symbol n fmax BW VRB VRT – VRB tpd ED EL

Conditions

–3dB

Min.

—

14.3 —

0.48

1.96 —

–1.0 –2.0

Typ.

8

—

18

0.52

2.08 — — —

Max.

— — —

0.56

2.22 45

+1.0 +2.0

Unit

bit

MSPS

MHz

V V

ns LSB LSB

Internal Clamp

(VDD = 5V, Ta = 25°C, f = 10MHz)

Item

Clamp level

∗1

Symbol

CLV

Conditions Min.

—

Typ.

0.67

Max.

—

Unit

V

Internal 8-bit D/A Converter Characteristics

(VDD = 5V, VRF = 2V, RIRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz)

Item Resolution Max. conversion speed Differential linearity error Integral linearity error Output full-scale voltage Output full-scale current Output offset voltage

Glitch energy

Conditions

R = 75Ω,

1Vp-p output

Min.

—

14.3 –0.8 –2.0

1.805 — —

—

Typ.

8 — — —

1.90

9.5 —

30

Max.

—

— +0.8 +2.0

1.995 15

1.0 —

Unit

bit

MSPS

LSB LSB

V mA mV

pV-s

∗1

Sync tip clamp

Symbol n fmax ED EL VFS IFS VOS

GE

– 7 –

CXD2093Q

Description of Functions

• Y/C separation mode

The Y/C separation mode can be switched by the following pin settings.

Adaptive processing mode: Y/C separation is performed by detecting the correlation between three lines and switching between comb filter and BPF processing.

BPF separation mode: Y/C separation is performed only by BPF processing.

Through mode: The composite video signal input from ADIN (Pin 2) is A/D converted and then D/A converted without modification. D/A outputs are AYO (Pin 9) and ACO (Pin 7).

• Horizontal aperture correction circuit This circuit corrects the frequency response degradation caused by the aperture effects accompanying D/A conversion. This circuit is valid in the adaptive processing and BPF separation modes noted above.

• Trap filter circuit A trap filter is applied to remove the frequency components near fsc in the luminance signal after Y/C separation. This reduces the fsc frequency component gain by approximately 2.5dB. This circuit is valid in the adaptive processing and BPF separation modes noted above.

• Using the internal PLL (clock selection method)

Mode name

Adaptive processing mode

BPF separation mode

Through mode

MOD2 (Pin 17)

L H H

MOD1 (Pin 19)

L L

H

PLL used

PLL not used

FIN (Pin 37)

fsc input 2fsc input 4fsc input

CKSL (Pin 38)

H H

L

PLSL (Pin 39)

L

H

L/H

– 8 –

CXD2093Q

• Vertical enhancement circuit This circuit generates an enhanced component in accordance with the vertical aperture component (luminance difference from the preceding and following lines) of the luminance signal. The vertical aperture of the picture can be enhanced naturally by adding this enhanced component to the luminance signal after Y/C separation. The enhancement level can be set in eight steps. The size of | a | in the figure below varies according to the pin settings. Accordingly,enhanced level can be changed for portions of natural pictures with small luminance differences where the effects are particularly easy to see. Portions with large luminance differences are cut with a limiter so that they are not excessively enhanced. Also, portions with extremely large luminance differences such as white and black lines are not enhanced because they need be enhanced any more.

0

–a a

Limiter

Enhancement level

Luminance difference

OFF

1 2 3 4 5 6

Max

| a |

—

Large

↑

↓

Small

Pin settings

VEH3 VEH2 VEH1

(Pin 20) (Pin 21) (Pin 22)

L L L L L H L H L

L H H H L L H L H H H L H H H

Enhancement

level

– 9 –

CXD2093Q

Application Circuit for D/A Converter Block

DAVD

DAVS

3k

2k

0.1µ

Y output

C output

0.1µ

AYO

VRF

IRF

ACO

VG

VB

0.1µ10µ

3.3k (R’)

200

(R)

: Analog power Supply (5V)

: Analog ground

200

(R)

7

8

9

10

11

12

13

14

• Method of selecting the output resistor The CXD2093Q has a built-in current output type D/A converter. To obtain the output voltages, connect resistors to the AYO and ACO pins. The specs are as follows: output full-scale voltage VFS = 0.5 to 2.0 [V], output full-scale current IFS = 0 to 15 [mA]. Calculate the output resistance value using the relationship VFS = IFS × R. In addition, connect a resistor of 16 times the output resistor to the reference current pin (IRF). In case this results in a unpractical value, use a resistance value as close to the calculated value as possible. Note that, at this time, VFS = VRF × 16R/R’ (VRF: Pin voltage of VRF). Here, R is the resistor connected to AYO/ACO, and R’ is the resistor connected to IRF. Power consumption can be reduced by using higher resistance values, but the glitch energy and data settling time increase contrastingly. Set the optimum values according to the system applications.

• VDD, VSS Separate the analog and digital systems around the device to reduce the effects of noise. DAVD is bypassed to DAVS as close to each other as possible through a ceramic capacitor of approximately 0.1µF.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 10 –

CXD2093Q

External Connection Diagram

DV

SS

FIN

CKSL

PLSL

MCKO

ADCK

CPO

PLVS

VCV

PLVD

CLVD

CLPEN

CLVS

DV

SS

DVSS

VEH1

VEH2

VEH3

MOD1

DV

SS

MOD2

DV

DD

TEST

VB

IRF

DV

SS

TEST

DV

DD

TEST

TRAP

APCN

DV

SS

TEST

DV

DD

CLPO

ADIN

RB

ADVS

ADVD

RT

ACO

DAVD

AYO

DAVS

VG

VRF

0.1µ

L

56k560

0.1µ

0.022µ

0.1µ

3.3k

10µ

0.1µ 0.1µ

2k

3k

0.1µ

C output Y output

0.1µ

0.001µ

Composite Video Input

0.1µ

H

H L H L

L

H

L

H

L

H

L

H

L

H

L

H

L

H

0.1µ

0.1µ 0.1µ

0.1µ

Clock Input

200 200

: Analog power Supply (5V)

: Analog ground

H L

: CMOS High level : CMOS Low level

: Digital power Supply (5V)

: Digital ground

21

22

23

24

25

26

27

28

29

30

40

39

38

37

36

35

34

31

32

33

11

12

13

14

15

16

17

18

19

20

41

42

43

44

45

46

47

48

2

3

4

5

6

7

8

9

10

1

DV

SS

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 11 –

CXD2093Q

Notes on Operation

• Make the wiring for the signal input to ADIN (Pin 2) as short as possible. Also, drive the input signal to ADIN at

low impedance.

• Make the analog and digital power supply and GND lines as wide and short as possible to ensure low impedance.

• Bypass the analog and digital power supply pins to GND with a ceramic capacitor of about 0.1µF connected as close to the pin as possible.

• Input a clock that is locked to the burst signal of the input video signal.

• Separate the wiring to the clock input pin FIN (Pin 37) from the external analog circuits, analog power

supplies and analog GND.

• ADIN (analog input signal)

Set the input signal peak-to-peak value VPP to 1.75V or less. Additionally, VPP is recommended to be

1.3V or more since the A/D converter input dynamic range should be made as large as possible.

The DC level at the ADIN pin is as shown in the diagram above when the internal sync tip clamp is used.

Labeling the internal D/A converter AYO output full-scale voltage as VFS, the correspondence between the ADIN pin voltage and AYO output pin voltage (DC level) is as follows;

DC voltage at point B → AYO maximum output voltage [V] DC voltage at point A → 0 [V] DC voltage at point C → VFS [V]

The VFS is the AYO output voltage generated when the voltage equivalent to the point C is input.

• Internal delay

The delay from the internal A/D converter to the D/A converter output is as follows;

1H + 24.5 clocks + αns

(α: D/A converter analog output delay = approximately 20ns)

The 24.5 clocks are the sum of the clocks shown below;

A/D converter:3.5 clocks (“0.5” is for fetching the data at the fall of the clock.) Internal logic: 20 clocks D/A converter:1 clock

C

→

B

→

A

→

VPP

2.60V (Reference top voltage typical value for internal A/D converter)

0.67V (Sync tip clamp level)

0.52V (Reference bottom voltage typical value for internal A/D converter)

– 12 –

CXD2093Q

Application Circuit 1

• fsc is used for clock

DV

SS

DV

SS

FIN

CKSL

PLSL

MCKO

ADCK

CPO

PLVS

VCV

PLVD

CLVD

CLPEN

CLVS

DV

SS

DVSS

VEH1

VEH2

VEH3

MOD1

DV

SS

MOD2

DV

DD

TEST

VB

IRF

DV

SS

TEST

DV

DD

TEST

TRAP

APCN

DV

SS

TEST

DV

DD

CLPO

ADIN

RB

ADVS

ADVD

RT

ACO

DAVD

AYO

DAVS

VG

VRF

0.1µ

L

56k560

0.1µ

0.022µ

0.1µ

3.3k

10µ

0.1µ 0.1µ

200

2k

3k

0.1µ

C output

Y output

0.1µ

0.001µ

Composite Video Input

H L H L

0.1µ

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

LPF

Burst-locked Clock (fsc)

X’tal NTSC : 3.58MHz

0.1µ

0.1µ 0.1µ

0.1µ

LPF

200

LPF

H L

Clock Generator

: Analog power Supply (5V) : Analog ground

: Digital ground

: Digital power Supply (5V)

: CMOS High level : CMOS Low level

21

22

23

24

25

2627

28

29

30

40

39

38

37

36

35

34

31

32

33

11

12

13

14

15

16

17

18

19

20

41

42

43

44

45

46

47

48

2

3

4

5

6

7

8

9

10

1

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 13 –

CXD2093Q

Application Circuit 2

• 2fsc is used for clock

DV

SS

DV

SS

FIN

CKSL

PLSL

MCKO

ADCK

CPO

PLVS

VCV

PLVD

CLVD

CLPEN

CLVS

DV

SS

DVSS

VEH1

VEH2

VEH3

MOD1

DV

SS

MOD2

DV

DD

TEST

VB

IRF

DV

SS

TEST

DV

DD

TEST

TRAP

APCN

DV

SS

TEST

DV

DD

CLPO

ADIN

RB

ADVS

ADVD

RT

ACO

DAVD

AYO

DAVS

VG

VRF

0.1µ

L

56k560

0.1µ

0.022µ

0.1µ

3.3k

10µ

0.1µ 0.1µ

200

2k

3k

0.1µ

C output

Y output

0.1µ

0.001µ

Composite Video Input

H L H L

0.1µ

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

LPF

Clock Generator

Burst-locked Clock (2fsc)

X’tal NTSC : 7.16MHz

0.1µ

0.1µ 0.1µ

0.1µ

LPF

200

LPF

H L

: Analog power Supply (5V) : Analog ground

: Digital power Supply (5V) : Digital ground

: CMOS High level : CMOS Low level

21

22

23

24

25

26

27

28

29

30

40

39

38

37

36

35

34

31

32

33

11

12

13

14

15

16

17

18

19

20

41

42

43

44

45

46

47

48

2

3

4

5

6

7

8

9

10

1

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 14 –

CXD2093Q

Application Circuit 3

• 4fsc is used for clock

FIN

CKSL

PLSL

MCKO

ADCK

CPO

PLVS

VCV

PLVD

CLVD

CLPEN

CLVS

DV

SS

DVSS

VEH1

VEH2

VEH3

MOD1

DV

SS

MOD2

DV

DD

TEST

VB

IRF

DV

SS

TEST

DV

DD

TEST

TRAP

APCN

DV

SS

TEST

DV

DD

DV

SS

DV

SS

CLPO

ADIN

RB

ADVS

ADVD

RT

ACO

DAVD

AYO

DAVS

VG

VRF

0.1µ

L

0.1µ

3.3k

10µ

0.1µ 0.1µ

200

2k

3k

0.1µ

C output

Y output

0.1µ

0.001µ

Composite Video Input

H L H L

0.1µ

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

LPF

Clock Generator

Burst-locked Clock (4fsc)

X’tal NTSC : 14.3MHz

0.1µ

0.1µ 0.1µ

0.1µ

LPF

200

LPF

H L

: Analog power Supply (5V) : Analog ground

: Digital power Supply (5V) : Digital ground

: CMOS High level : CMOS Low level

21

22

23

24

25

26

27

28

29

30

40

39

38

37

36

35

34

31

32

33

11

12

13

14

15

16

17

18

19

20

41

42

43

44

45

46

47

48

2

3

4

5

6

7

8

9

10

1

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 15 –

CXD2093Q

SONY CODE EIAJ CODE JEDEC CODE

M

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN SOLDER / PALLADIUM

PLATING 42/COPPER ALLOY

48PIN QFP (PLASTIC)

15.3 ± 0.4

12.0 – 0.1

+ 0.4

0.8

0.3 – 0.1

+ 0.15

0.24

13

24

2536

37

48

1 12

2.2 – 0.15

+ 0.35

0.9 ± 0.2

0.1 – 0.1

+ 0.2

13.5

0.15 – 0.05

+ 0.1

QFP-48P-L04 QFP048-P-1212

0.7g

0.15

Package Outline Unit : mm