Page 1
CXD2044Q
For the availability of this product, please contact the sales office.
Digital Comb Filter (NTSC/PAL/PAL-M/PAL-N)
Description
The CXD2044Q is an adaptive intra-field comb
filter compatible with NTSC, PAL, PAL-M and PAL-N
systems, and can provide high-precision Y/C
separation with a single chip.
Features
• Intra-field Y/C separation by adaptive processing
• 8-bit A/D converter (1-channel)
• 8-bit D/A converter (2-channel)
• Four 1H delay lines
• Clock 4fsc
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
• Supply voltage DVDD VSS – 0.5 to +7.0 V
AAVD VSS – 0.5 to +7.0 V
ADVD VSS – 0.5 to +7.0 V
YVDD VSS – 0.5 to +7.0 V
CVDD VSS – 0.5 to +7.0 V
• Input voltage VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Storage temperature
Tstg –55 to +150 °C
Block Diagram
Recommended Operating Conditions
• Supply voltage DVDD 5.0 ± 0.25 V
• Analog input ADIN 1.8 Vp-p
• Operating temperature
Applications
Y/C separation for color TVs and VCRs
Structure
Silicon gate CMOS IC
80 pin QFP (Plastic)
AAVD 5.0 ±0.25 V
ADVD 5.0 ± 0.25 V
YVDD 5.0 ± 0.25 V
CVDD 5.0 ± 0.25 V
Topr –20 to +75 °C
Analog Vin
Digital Vin
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
A/D
8
NTSC: 1H
PAL: 2H
Logic operation
NTSC: 1H
PAL: 2H
– 1 –
DL D/A
Adaptive
filter
operation
8
D/A
8
A-Yout
D-Yout
A-Cout
D-Cout
E95418-ST
Page 2
Pin Configuration
64
TEST
65
TEST
66
XCOE
67
APCN
68
RATI
69
NTPL
70
YOT
71
DVss
72
DV
DD
73
DTR
74
TEST
75
PMN
76
TEST
77
TEST
78
BPF
79
TEST
80
C1
63
C2
62
C3
61
C4
60
C5
59
C6
58
C7
57
C8
XYOE
56
CONT
55
54
TEST
53
DD
DV
52
DVss
51
Y1
50
Y2
49
Y3
48
Y4
47
Y5
46
Y6
45
Y7
44
Y8
43
CVss
42
CIRF
41
CVRF
CXD2044Q
40
CVG
39
ACO
38
XACO
37
CVDD
36
VB
35
YVss
34
YIRF
33
YVRF
32
YVG
31
AYO
30
XAYO
29
YVDD
28
ADVD
27
RT
26
AAVD
25
ADIN
Pin Description
Pin
Symbol
No.
1
VI8
2
VI7
3
VI6
4
VI5
5
VI4
6
VI3
7
VI2
8
VI1
9
ADCO
6
VI6
5
4
VI3
VI4
VI5
1
2
3
VI7
VI8
9
10
8
7
VI1
VI2
INSL
ADCO
11
12
OCLK
13
DVss
14 15
DD
DV
CLKO
MCK
I/O Description
I
Digital input (MSB). Connect to DVDD or DVss when not in use.
I
Digital input. Connect to DVDD or DVss when not in use.
I
Digital input. Connect to DVDD or DVss when not in use.
I
Digital input. Connect to DVDD or DVss when not in use.
I
Digital input. Connect to DVDD or DVss when not in use.
I
Digital input. Connect to DVDD or DVss when not in use.
I
Digital input. Connect to DVDD or DVss when not in use.
I
Digital input (LSB). Connect to DVDD or DVss when not in use.
A/D converter output through mode.
High: Video signals taken into the A/D converter (input pin: ADIN) are output without
I
change from the Y output pins as 8-bit digital data with a 3.5 clock delay.
Low: Standard mode
16
17
ADCK
18
CLPI
19
ADVS
XCPON
20
ICP
21
22
CRV
RB
23
24
GR
AAVS
10
11
INSL
OCLK
Input switching. Switches the input data fed to the comb filter.
I
High: Digital input
Low: Analog input
Clock amplifier input.
I
Input 0.8Vp-p or more, eliminating the DC components with a capacitor.
– 2 –
Page 3
Pin
Symbol I/O Description
No.
12
13
14
DVSS
DVDD
CLKO
—
Digital ground.
—
Digital power supply. (5V)
O
Clock amplifier output.
Master clock input.
15
MCK
I
Input the 4fsc clock locked to the color burst.
Normally, connect the clock amplifier output (CLKO: Pin 14).
Clock input for the A/D converter.
16
ADCK
I
Input the same clock as the master clock (MCK: Pin 15).
Normally, connect the clock amplifier output (CLKO: Pin 14).
Clamp pulse input for the A/D converter.
17
CLPI
I
Clamps the signal voltage during the low period of the clamp pulse signal.
When the clamp function is off, connect to the digital power supply (DVDD).
Clamp setting for the A/D converter.
18
XCPON
I
High: Clamp function is set to off, and the normal A/D converter function is only enabled.
Low: Clamp function is enabled.
CXD2044Q
19
20
21
22
23
24
25
26
27
28
29
30
31
ADVS
ICP
CRV
RB
GR
AAVS
ADIN
AAVD
RT
ADVD
YVDD
XAYO
AYO
—
Digital ground for the A/D converter.
Clamp control voltage integral pin.
I
Connect a capacitor of approximately 0.01µF.
When not using clamp, connect to the analog ground (AAVS).
Clamp reference voltage input.
I
Operates to make the analog input voltage equal to the clamp reference voltage during
the clamp period. When not using clamp, connect to the analog ground (AAVS).
O
Reference voltage (bottom): 0.5V (typ.)
—
Guard ring. Connect to the analog ground (AAVS).
—
Analog ground for the A/D converter.
I
Comb filter analog input (A/D converter input).
—
Analog power supply for the A/D converter. (5V)
O
Reference voltage (top): 2.6V (typ.)
—
Digital power supply for the A/D converter. (5V)
—
Analog power supply for the Y D/A converter. (5V)
AYO inverted current output.
O
Connect to the analog ground (YVss).
Analog luminance signal output.
O
Output can be obtained by connecting a resistor between this pin and the analog ground.
32
33
34
35
36
37
38
YVG
YVRF
YIRF
YVss
VB
CVDD
XACO
O
Connect a capacitor of approximately 0.1µF.
I
Sets the full-scale value of the analog luminance output signal.
O
Connect a resistor of “16R” (16 times the output resistor “R” of the AYO pin).
—
Analog ground for the Y D/A converter.
O
Connect a capacitor of approximately 0.1µF.
—
Analog power supply for the C D/A converter. (5V)
ACO inverted current output.
O
Connect to the analog ground (CVss).
– 3 –
Page 4
Pin
No.
Symbol
CXD2044Q
I/O Description
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
ACO
CVG
CVRF
CIRF
CVss
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
DVss
DVDD
TEST
Analog chroma signal output.
O
Output can be obtained by connecting a resistor between this pin and the analog ground.
O
Connect a capacitor of approximately 0.1µF.
I
Sets the full-scale value of the analog chroma output signal.
O
Connect a resistor of “16R” (16 times the output resistor “R” of the ACO pin).
—
Analog ground for the C D/A converter.
O
Digital luminance signal output (MSB).
O
Digital luminance signal output.
O
Digital luminance signal output.
O
Digital luminance signal output.
O
Digital luminance signal output.
O
Digital luminance signal output.
O
Digital luminance signal output.
O
Digital luminance signal output (LSB).
—
Digital ground.
—
Digital power supply. (5V)
I
Test. Normally open or fix to “Low”.
55
56
57
58
59
60
61
62
63
64
65
66
67
CONT
XYOE
C8
C7
C6
C5
C4
C3
C2
C1
TEST
TEST
XCOE
I
Normally open or fix to “High”.
Digital luminance signal output control.
High: High impedance
I
Low: Standard output
However, during PAL-M/N mode (Pins 70 and 76 are both “High”), the digital chroma
signal output is also controlled simultaneously. See Table 1.
O
Digital chroma signal output (MSB).
O
Digital chroma signal output.
O
Digital chroma signal output.
O
Digital chroma signal output.
O
Digital chroma signal output.
O
Digital chroma signal output.
O
Digital chroma signal output.
O
Digital chroma signal output (LSB).
I
Test. Normally open or fix to “Low”.
I
Test. Normally open or fix to “Low”.
Digital chroma signal output control. See Table 1.
I
High: High impedance
Low: Standard output
68
APCN
Aperture compensation circuit setting.
High: Compensates for the aperture-induced frequency response characteristics degradation.
I
Even in through mode (YOT: H), aperture compensation is performed for the Y output.
Low: Standard mode
– 4 –
Page 5
CXD2044Q
Pin
No.
69
70
71
72
73
74
Symbol
RATI
NTPL
YOT
DVss
DVDD
DTR
I/O Description
Ratio setting.
High: PAL/PAL-M/PAL-N:
I
When DTR: H, compulsively fixed to “Low” internally.
Low: NTSC
NTSC/PAL/PAL-M/PAL-N mode setting. See Table 1.
I
High: PAL/PAL-M/PAL-N
Low: NTSC
Y output through mode.
High: Outputs the input composite video signal from the Y output. At this time, there
I
is 1H + 15 clock delay from the digital input for NTSC, and 2H + 15 clock
delay from the digital input for PAL/PAL-M/PAL-N. For C output, the Y/C
separated chroma signal is output.
Low: Y/C separation mode
—
Digital ground.
—
Digital power supply. (5V)
PAL/PAL-M/PAL-N:
High: Dot interference reduction mode
I
Low: Before dot interference reduction
NTSC: Fix to “Low”.
75
76
77
78
TEST
PMN
TEST
TEST
I
Test. Normally fix to “Low”.
I
NTSC/PAL/PAL-M/PAL-N mode selection. See Table 1.
I
Test. Normally fix to “Low”.
I
Test. Normally fix to “Low”.
Y/C separation processing mode setting.
79
BPF
I
High: Fixed to BPF separation mode
Low: Adaptive processing mode
80
TEST
I
Test. Normally fix to “Low”.
Table 1. NTSC/PAL/PAL-M/PAL-N mode selection
(Numbers in parentheses indicate the Pin No.)
Mode
NTSC
PAL
PAL-M
PAL-N
∗
Digital Y output enable and digital C output enable are simultaneously controlled by XYOE (Pin 56) during
NTPL (70)
0
1
1
1
PMN (76)
0
0
1
1
XCOE (67)
∗
0
0
0
1
PAL-M/PAL-N mode.
– 5 –
Page 6
Electrical Characteristics
CXD2044Q
DC Characteristics
Item Symbol
VDD
AAVD
Supply voltage —
Operating temperature
Input/output voltage
Input voltage
Input rise/fall time
Output voltage
ADVD
YVDD
CVDD
Topr
VI, VO
VIH
VIL
tr, tf
VOH
VOL
Measurement
conditions
CMOS level input
IOH = –2mA
IOH = –4mA
IOL = 4mA
IOL = 8mA
—
—
—
(VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C)
V
°C
V
V
ns
V
Applicable
pins
∗1
∗2
∗3
∗1
∗4
∗5
∗4
∗5
Min. Typ. Max. Unit
4.75
–20
Vss
0.7VDD
0
VDD–0.8
5.0
5.25
+75
VDD
0.3VDD
500
0.4
Logical Vth
Input voltage
Input amplitude
Feedback resistance value
Input leak current
Clock amplifier output delay
∗1
All pins
∗2
All pins other than
∗3
All input pins other than
∗4
All output pins other than
∗5
CLKO (Pin 14)
∗6
OCLK (Pin 11)
∗7
All pins other than ∗8and
∗8
Pins 54, 65, 66 and 75 to 80
∗9
Pin 55
∗6
∗6
∗5
∗9
LVth
VIH
VIL
VIN
RFB
IIL, IIH
IIH
IIL
—
—
fmax = 50MHz sine wave
VIN = Vss or VDD
VIN = VSS or VDD
VIH = VDD
VIL = VSS
—
0.7VDD
0.8
250k
–10
40
–40
3.0
VDD/2
1M
100
–100
9.0
0.3VDD
2.5M
10
240
–240
18.0
V
V
Vp-p
Ω
µA
ns
∗6
∗7
∗8
∗9
∗5
– 6 –
Page 7
AC Characteristics
Input Interface Timing
Input Data
CXD2044Q
MCK
Input Characteristics
Input pin Pin No.
VI8 to VI1 1 to 8
Output Interface Timing
MCK
Tsu
Th
0.7V
DD
(VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C)
Min.
Unit Remarks
Tsu Th
20.00 10.00 ns Rising edge of MCK is used as a reference.
DD
0.7V
Output Data
Output Characteristics
Output pin Pin No.
Y8 to Y1
C8 to C1
44 to 51
57 to 64
Tpd
(output load capacitance 20 [pF])
Max.
Min.
Max.
Min.
25.0
5.00
25.00
5.00
– 7 –
Tpd
(VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C)
Unit Remarks
Rising edge of MCK is used as a
ns
reference.
Rising edge of MCK is used as a
ns
reference.
Page 8
Clock Frequency (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C)
Input pin Pin No. Symbol Min. Typ. Max. Unit
∗1
OCLK, MCK, ADCK 11, 15, 16 f —
∗1
fsc = 3.58MHz (NTSC), 4.43MHz (PAL)
4fsc
— MHz
CXD2044Q
I/O Pin Capacitance
Item Symbol Min. Typ. Max. Unit
Input pin capacitance
Output pin capacitance
Internal 8-bit ADC Characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Resolution
Max. conversion speed
Analog input bandwidth
Self bias
Output data delay
Differential linearity error
Integral linearity error
Clamp offset voltage
CIN
COUT
n
fmax
BW
VRB
VRT–VRB
tpd
ED
EL
EOC
(Ta = 25°C, f = 1MHz, VIN = VOUT = 0V)
—
—
–3dB
VREF = VRB
VREF = VRT
—
—
9
11
(VDD = 5V, Ta = 25°C, f = 10MHz)
—
18
—
0.48
1.96
—
–1.0
–3.0
–20
–30
pF
8
—
18
0.52
2.08
—
—
—
0
–10
—
—
—
0.56
2.22
45
+1.0
+3.0
+20
+10
bit
MSPS
MHz
V
V
ns
LSB
LSB
mV
mV
Internal 8-bit DAC Characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Resolution
Max. conversion speed
Differential linearity error
Integral linearity error
Output full-scale voltage
Output full-scale current
Output offset voltage
Glitch energy
∗2
R = 75Ω, 1Vp-p output
(VDD = 5V, VRF = 2V, RIRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz)
n
fmax
ED
EL
VFS
IFS
VOS
GE
∗2
– 8 –
—
18
–0.8
–2.0
1.805
—
—
—
8
—
—
—
1.90
9.5
—
30
—
—
+0.8
+2.0
1.995
15
1.0
—
MSPS
bit
LSB
LSB
V
mA
mV
pV-s
Page 9
Application Circuit for the A/D Converter Block
(1) When inputting the clamp pulse directly
CXD2044Q
27
25
22
21
20
23
26
0.1µ
24
ADC input
10µ
20k
0.01µ
75
10p
0.01µ
0.01µ
(2) When not using the internal clamp circuit
RT
ADIN
RB
CRV
ICP
GR
AAVD
AAVS
CLPI
XCLP
ADCK
ADVD
ADVS
17
18
16
28
19
Clamp pulse
ADC clock
0.1µ
ADC input
75
0.01µ
0.01µ
10p
0.1µ
27
25
22
21
20
23
26
24
RT
ADIN
RB
CRV
ICP
GR
AAVD
AAVS
CLPI
XCLP
ADCK
ADVD
ADVS
18
16
28
17
ADC clock
0.1µ
19
– 9 –
Page 10
Application Circuit for the D/A Converter Block
CXD2044Q
CLOCK
0.1µ
0.1µ
35
15
29
37
43
YVDD
YVSS
MCK
DD
DV
DVSS
CVDD
CVSS
AYO
XAYO
YVG
YVRF
YIRF
VB
ACO
XACO
CVG
CVRF
CIRF
31
30
32
34
39
38
40
41
42
33
36
Y OUTPUT
200 (R)
0.1µ
1K
3.3k (R')
0.1µ
C OUTPUT
200 (R)
0.1µ
1K
3.3k (R')
• Method of selecting the output resistor
The CXD2044Q has a built-in current output type D/A converter. To obtain the output voltages, connect
resistors to the AYO and ACO pins.
The specs are as follows: output full-scale voltage VFS = 0.5 to 2.0 [V], output full-scale current IFS = 0 to
15 [mA].
Calculate the output resistance value using the relationship VFS = IFS × R. In addition, connect a resistor of 16
times the output resistor to the reference current pin (YIRF, CIRF). In case this results in a non-existent
value, use a resistance value as close to the calculated value as possible.
Note that, at this time, VFS = VRF × 16R/R' (VRF: Pin voltage of YVRF and CVRF). Here, R is the resistor
connected to AYO/ACO, and R' is the resistor connected to YIRF/CIRF. Power consumption can be reduced
by using higher resistance values for the R, but the glitch energy and data settling time increase
contrastingly. Set the optimum values according to the system applications.
• VDD, Vss
Separate the analog and digital systems around the device to reduce the effects of noise. YVDD and CVDD
are by-passed to YVss and CVss, respectively, as close to each other as possible through ceramic
capacitors of approximately 0.1µF.
– 10 –
Page 11
CXD2044Q
: Digital power supply (5V)
: Analog ground
: Analog power supply (5V)
: Digital ground
1k
3.3k
0.1µ
Y1 to 8: Standard output
Y1 to 8: High impedance
0.1µ
31
AYO
DTR
74
LPF
30
XAYO
TEST
75
Y OUT
200
0.1µ
29
YVDD
PMN
76
28
ADVD
TEST
77
0.1µ
27
RT
TEST
78
0.01µ
26
AAVD
BPF
79
25
ADIN
TEST
80
VIDEO IN
10µ
75
10p
0.01µ
0.01µ
0.1µ
1000p
20k
Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these
circuits or for any infringement of third party patent and other right due to same.
Digital ground
C1 to 8: High Impedance
C1 to 8: Standard output
(5V)
PAL-N
PAL-M
Digital power supply
PMN (pin76)
DD
AAVS
24
GR
23
RB
22
CRV
21
ICP
20
ADVS
19
XCPON
18
CLPI
17
ADCK
16
MCK
CLKO
14 15
DV
13
DVss
12
OCLK
11
INSL
10
ADCO
9
VI1
8
VI2
7
VI3
6
VI4
5
VI5
4
VI6
3
VI7
2
VI8
1
C OUT
LPF
3.3k
35
YVss
NTPL
70
34
YIRF
YOT
71
1k
33
YVRF
DVss
72
32
YVG
DD
DV
73
200
0.1µ
39
ACO
38
XACO
XCOE
67
0.1µ
37
CVDD
APCN
68
36
VB
RATI
69
0.1µ
40
CVG
CVRF
4142
CIRF
CVss
43
Y8
44
Y7
45
Y6
46
Y5
47
Y4
48
Y3
49
Y2
50
Y1
51
DVss
52
DD
DV
53
TEST
54
CONT
55
XYOE
56
C8
57
C7
58
C6
59
C5
60
C4
61
C3
62
C2
63
C1
64
TEST
TEST
66
65
Application Circuit
∗
1
)
(
Aperture ON
OFF
PAL
Through
NTSC
0.1µ
Normal
– 11 –
BPF
Normal
Digital power supply (5V)
Digital ground
XCOE (pin67)
Clock input
)
1
∗
(
Clamp pulse input
Page 12
Package Outline Unit: mm
CXD2044Q
80PIN QFP (PLASTIC)
65
80
23.9 ± 0.4
+ 0.4
+ 0.1
0.15 – 0.05
20.0 – 0.1
64
41
40
0.15
+ 0.4
16.3
17.9 ± 0.4
14.0 – 0.1
A
25
1
0.8
0.12
M
24
0.35 – 0.1
+ 0.15
+ 0.35
2.75 – 0.15
+ 0.2
0.1 – 0.05
0.8 ± 0.2
SONY CODE
EIAJ CODE
JEDEC CODE
0° to 10°
DETAIL A
∗QFP080-P-1420-A
QFP-80P-L01
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY
1.6g
– 12 –
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