Datasheet CXD2309Q Datasheet (Sony) [en, no]

Page 1
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E94341B01
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage AVDD, DVDD 7V
VIN VDD+0.5 to VSS–0.5 V
• Output current IOUT 0 to 15 mA
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25 V
DVDD, DVSS 4.75 to 5.25 V
• Reference input voltage VREF 0.5 to 2.0 V
• Clock pulse width TPW1, TPW0 9 (min.) ns
• Operating temperature Topr –20 to +85 °C
Description
The CXD2309Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel input/output. This is ideal for use in high-definition TVs and high-resolution displays.
Features
• Resolution 10-bit
• Maximum conversion speed 85MSPS
• RGB 3-channel input/output
• Differential linearity error ±0.5 LSB
• Low power consumption 275 mW
(200 Ω load for 2 Vp-p output)
• Single +5 V power supply
• Low glitch
• 48-pin QFP package
Structure
Silicon gate CMOS IC
10-bit 85MSPS 3-Channel D/A Converter
48 pin QFP (Plastic)
CXD2309Q
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CXD2309Q
Block Diagram
DECODER
DECODER
LATCHES
4LSB’S
CURRENT
CELLS
DECODER
DECODER
LATCHES
6LSB’S
CURRENT
CELLS
CLOCK
GENERATOR
4LSB’S
CURRENT
CELLS
6LSB’S
CURRENT
CELLS
CLOCK
GENERATOR
DECODER
DECODER
LATCHES
4LSB’S
CURRENT
CELLS
6LSB’S
CURRENT
CELLS
CLOCK
GENERATOR
1 2 3
4 5 6
7 8 9
10
11 12 13 14 15 16 17 18 19 20
31
32
33
48
21 22 23 24 25 26 27 28 29 30
35
34
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
43 42
44
45
46
47
41 40 39
38
37
36
(LSB) R0
R1 R2 R3 R4 R5 R6 R7 R8
(MSB) R9
RCK
(LSB) G0
G1 G2 G3 G4 G5 G6 G7 G8
(MSB) G9
GCK
(LSB) B0
B1 B2 B3 B4 B5 B6 B7 B8
(MSB) B9
BCK
DV
DD
VB
DV
SS
AVSS RO
AV
SS
GO
AV
SS
BO
AV
DD
AVDD AVDD
VG
VREF
IREF
Page 3
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CXD2309Q
Pin Configuration
2 31 4 5 6 7 8 9
10 11 12
22
23
24
21 20 19 18 17 16 15 14 13
35 34 33 32 31 30 29 28 27 26 2536
46
45
44
43
42
41
40
39
38
47 48
37
(LSB) R0
R1
R2
R3
R4
R5
R6
R7
R8
(MSB) R9
(LSB) G0
G1
IREF
VB
DV
SS
BCK
GCK
RCK
B9 (MSB)
B8
B7
B6
B5
B4
B3 B2 B1 B0 (LSB) G9 (MSB) G8 G7 G6 G5 G4 G3 G2
1
35,48
36 47
to
to
Digital system Analog system
VG
AV
DD
AVDD AVDD
RO
AV
SS
GO
AV
SS
BO
AV
SS
DVDD
VREF
Pin Description and Equivalent Circuit
Pin No. Symbol I/O Equivalent circuit Description
1 to 10
11 to 20
21 to 30
31
32
33 34
35
R0 to R9
G0 to G9
B0 to B9
RCLK
GCLK
BCLK
DVSS
VB
I
—
O
DVDD
DVSS
33
1
to
Digital input. 1 pin R0 (LSB) to 10 pin R9 (MSB) 11 pin G0 (LSB) to 20 pin G9 (MSB) 21 pin B0 (LSB) to 30 pin B9 (MSB)
Clock input.
Digital ground.
Connect an approximately 0.1µF capacitor.
DVDD
DVSS
35
DVDD
Page 4
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CXD2309Q
Pin No. Symbol I/O Equivalent circuit Description
36
37
38
39 to 41
42
44
46
43, 45, 47
48
IREF
VREF
VG
AVDD
RO
GO
BO
AVSS
DVDD
O
I
O
—
O
— —
AVDD
AVSS
AVDD
AVSS
37
36
AVDD
AVDD
AVSS
38
AVDD
AVSS
44 46
42
AVSS
Reference current output. Connect an “RIR” resistor which are 16 times the output resistance “ROUT”.
Reference voltage input. Sets an output full-scale value.
Connect an approximately 0.1µF capacitor.
Analog power supply.
Current output. Output can be obtained by connecting a resistor (200 Ω typ.).
Analog ground. Digital power supply.
Page 5
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CXD2309Q
Electrical Characteristics (fCLK=85 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, RIR=3.3 kΩ, Ta=25°C)
Item
Resolution Conversion speed Integral non-linearity error
Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale ratio
∗1
Output full-scale current Output offset voltage Glitch energy
Crosstalk
SN ratio
Supply current Analog input resistance
Input capacitance Output capacitance
Digital input voltage
Digital input current Setup time
Hold time Propagation delay time Rise time Fall time
Symbol
n fCLK EL
ED VOC VFS
FSR IFS VOS GE
CT
SNR
IDD RIN
CI CO VIH VIL IIH IIL ts th tPD tr tf
Measurement conditions
AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +85 °C
Endpoint
When “0000000000” data input ROUT=100 Ω, 1 Vp-p output When 10 MHz FCLK=50 MHz sin wave input FCLK=85 MHz When 1 MHz FCLK=50 MHz sin wave input FCLK=85 MHz When 10 MHz FCLK=50 MHz sin wave output FCLK=85 MHz VREF
AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C
Min.
0
–2.0 –0.5
1.8
1.8 0
9.0
40
50
1
2.15
–5
4 1
Typ.
10
1.92
1.92
9.6
50 42 40 55 50 48 55
125
14
26.5
26.0
Max.
85
2.0
0.5
2.0
2.0 3
10
1
58
9
0.85 5
Unit
bit
MSPS
LSB LSB
V V
% mA mV
pV•s
dB
dB
mA MΩ
pF pF
V
µA
ns ns ns ns ns
Electrical Characteristics Measurement Circuit Analog Input Resistance
Measurement Circuit
Digital Input Current
CXD2309Q
+5.25V
AVDD, DVDD
AVSS, DVSS
V
A
}
Full-scale voltage of channel
∗1
Full-scale output ratio =
Average of the full-scale voltage of the channels
–1 × 100 (%)
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CXD2309Q
35
31 32 33
42
43 44 45
46 47
38
37
36
2V
10bit
COUNTER
with
LATCH
OSCILLOSCOPE
CLK 50MHz SQUARE WAVE
RO
AV
SS
GO
AV
SS
BO
AV
SS
VG
VREF
IREF
0.1µ
0.1µ
DV
SS
200
200
200
AV
SS
AVSS
AVSS
AVDD
3.3k AV
SS
VB
RCK GCK
BCK
R0 to R9 1 to 10
G0 to G9 11 to 20
B0 to B9 21 to 30
Crosstalk Measurement Circuit
35
31 32 33
42 43 44 45
46 47
37 36
2V
DIGITAL
WAVEFORM
GENERATOR
CLK 50MHz SQUARE WAVE
DV
DD
DVSS
0.1µ
RO
AV
SS
GO
AV
SS
BO
AV
SS
VG
VREF
IREF
200
200
200
AV
SS
AVSS
AVSS
AVDD
0.1µ
AV
SS
3.3k
VB
RCK GCK
BCK
R0 to R9 1 to 10
G0 to G9 11 to 20
B0 to B9 21 to 30
38
SPECTRUM
ANALYZER
Setup Time Hold Time Measurement Circuit Glitch Energy
35
31 32 33
42 43 44 45
46 47
38 37 36
2V
10bit
COUNTER
with
LATCH
DELAY
CONTROLLER
CLK 50MHz SQUARE WAVE
OSCILLOSCOPE
VB
RCK GCK
BCK
DV
SS
0.1µ
RO
AV
SS
GO
AV
SS
BO
AV
SS
VG
VREF
IREF
200
200
200
AV
SS
AVSS
AVSS
AVDD
0.1µ
3.3k AV
SS
DELAY
CONTROLLER
R0 to R9 1 to 10
G0 to G9 11 to 20
B0 to B9 21 to 30
}
Conversion Rate Measurement Circuit
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CXD2309Q
DC Characteristics Measurement Circuit
35
31 32 33
42
43 44 45
46 47
38
37
36
DVM
CLK 50MHz SQUARE WAVE
DV
SS
0.1µ
0.1µ
2V
AV
SS
AVSS
AVDD
AVSS
AVSS
200
200
200
RO
AV
SS
AVSS
AVSS
GO
BO
VG
VREF
IREF
CONTROLLER
3.3k
R0 to R9 1 to 10
VB
RCK GCK
BCK
G0 to G9 11 to 20
B0 to B9 21 to 30
Propagation Delay Time Measurement Circuit
SNR Measurement Circuit
200
35
31 32 33
42 43 44 45
46 47
38 37 36
10bit
COUNTER
with
LATCH
DELAY
CONTROLLER
DELAY
CONTROLLER
CLK 50MHz SQUARE WAVE
DV
SS
OSCILLOSCOPE
0.1µ
0.1µ
RO
AV
SS
AVSS
AVSS
GO
BO
VG
VREF
IREF
200 AV
SS
AVSS
AVSS
200
AVDD
2V
3.3k AV
SS
VB
RCK GCK
BCK
R0 to R9 1 to 10
G0 to G9 11 to 20
B0 to B9 21 to 30
35
31
32
33
42
43 44 45
46 47
38
37
36
DIGITAL
WAVEFORM
GENERATOR
CLK 50MHz SQUARE WAVE
ALL “1”
ALL “1”
0.1µ
DV
SS
200
200
200
AV
SS
AVSS
AVSS
AVDD
0.1µ
2V
3.3k AV
SS
RO
AV
SS
AVSS
AVSS
GO
BO
VG
VREF
IREF
VB
RCK GCK
BCK
R0 to R9 1 to 10
G0 to G9 11 to 20
B0 to B9 21 to 30
SPECTRUM
ANALYZER
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CXD2309Q
Description of Operation
Timing Chart
I/O Correspondence Table (output full-scale voltage: 2.00 V)
CLK
DATA
D/A OUT
tPW1 tPW0
1.5V
t
s th ts th ts th
tPD
tr
100%
50%
0%
90%
tf
10%
1.5V
Input code
MSB LSB
1 1 1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0 0 0
:
0 0 0 0 0 0 0 0 0 0
Output voltage
2.0 V
1.0 V
0 V
Page 9
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CXD2309Q
Notes on Operation
• Selecting the Output Resistance
CXD2309Q is a current output type D/A converter. The output voltage can be obtained by connecting the resistor ROUT to the current output pins RO, GO and BO. Specifications: Output full-scale voltage VFS = 1.8 to 2.0 [V]
Output full-scale current IFS = 9.0 to 10.0 [mA] Calculate the output resistance from VFS = IFS × ROUT. Connect a resistance sixteen times the output resistance to the reference current output pin IREF. In some cases, as this value may not exist, a similar value can be used instead. Note that the VFS will be the following.
VFS = VREF × 16ROUT/RIR VREF is the voltage set at the reference voltage input pin VREF, ROUT is the resistor to be connected to the current output pins RO, GO, BO and RIR is the resistor to be connected to the IREF. Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data setting time. Set the best values according to the purpose of use.
• Correlation between Data and Clock For CXD2309Q to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in “Electrical Characteristics”.
• Power supply, ground Separate the analog and digital signals around the device to reduce noise effects. Bypass the power supply pin to each ground with a 0.1 µF ceramics capacitor as near as possible to the pin for both the digital and analog signals.
• Latch up Analog and digital power supplies must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on.
• IREF The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable.
• VG pin It is recommended to use a 1 µF capacitor to improve the AC characteristics though the typical capacitance value externally connected to the VG pin is 0.1 µF.
• Output full-scale voltage For the applications using the RGB signal, the color balance may be broken up when the RO, GO and BO output full-scale voltages are used with not adjustment.
Page 10
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CXD2309Q
• When the power supply (AVDD and DVDD) is 5.0 V.
• R1=200 Ω
• R2=3.3 kΩ
• R3=3.0 kΩ
• R4=2.0 kΩ
• C=0.1 µF
Application Circuit
R2
C
C
Clock input
B ch input
LSB
G ch input
R ch
input
LSB
LSB
R3
R4
C
C
C
R1
R1
R1
37 38 39 40 41 42 43 44 45 46 47 48
1 2 3 4 5 6 7 8 9
10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
252627282930313233343536
AVDD
AVSS
DVDD
DVSS
MSB
MSB
MSB
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 11
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CXD2309Q
AVSS
33
C C
31
+5V
DIGITAL IC
DVDD
CXD2309Q
39 40 41
AVDD DVDD
DVSSAVSS
34
48
474543
Latch Up Prevention
The CX2309Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pin 39, 40 and 41) and DVDD (Pin 48), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
b. When analog and digital supplies are from a common source
(i)
(ii)
CXD2309Q
AVSS
AVDD
39 40 41
AV
DD DVDD
DVSSAVSS
C C
34
+5V +5V
48
DIGITAL IC
DVDD
45 4743
AVSS
C C
+5V
DIGITAL IC
DVDD
CXD2309Q
39 40 41
AV
DD DVDD
DVSSAVSS
34
48
45 4743
Page 12
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CXD2309Q
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
b. When analog and digital supplies are from common source
(i)
(ii)
AVSS
AVDD
C C
+5V +5V
DIGITAL IC
DVDD
CXD2309Q
39 40 41
AV
DD DVDD
DVSSAVSS
34
48
474543
AVSS
C C
+5V
DIGITAL IC
DVDD
AVDD
CXD2309Q
39 40 41
AV
DD DVDD
DVSSAVSS
34
48
474543
AVSS
C
+5V
DIGITAL IC
DVDD
AVDD
CXD2309Q
39 40 41
AVDD DVDD
DVSSAVSS
34
48
474543
Page 13
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CXD2309Q
Example of Representative Characteristics
Fig. 1. Reference voltage vs. Output full-scale voltage
Output full-scale voltage V
FS
[V]
2.0
1.0
Reference voltage VREF [V]
1.0 2.00
Fig. 2. Output resistance vs. Glitch energy
Glitch energy GE [pV•s]
100
50
Output resistance R
OUT [Ω]
100 2000
Fig. 3. Ambient temperature vs. Output full-scale voltage
1.95
1.90
Ambient temperature Ta [°C]
250
Output full-scale voltage V
FS
[V]
–25
0
50 75
∆V=0.02mV/°C
Fig. 4. Output frequency vs. Supply current
50
40
Output frequency Fo [MHz]
Supply current I
DD
[mA]
60
70
sin wave output
20105 30 4021 42
Standard Measurement Conditions
• AVDD=DVDD=5.0 V
• VREF=2.0 V
• FCLK=85 MHZ
• ROUT=200 Ω
• RIR=3.3 kΩ
• Ta=25 °C
Page 14
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CXD2309Q
Fig. 5. Clock frequency vs. Supply current
Supply current I
DD
[mA]
40
Clock frequency F
CLK [MHz]
20 50
10
20
30
50
60
85
IDD
IA [Analog]
I
D [Digital]
Fig. 6. Clock frequency vs. Supply current
Supply current I
DD
[mA]
40
Clock frequency F
CLK [MHz]
20 50
fout=10MHz sin wave
10
20
30
50
60
85
I
DD
IA [Analog]
I
D [Digital]
Fig. 7. Output frequency vs. Cross talk
Cross talk CT [dB]
40
Output frequency Fo [MHz]
0
sin wave output
10
20
30
50
60
Fig. 8. Output frequency vs. Output level
(Including primary hold characteristics sinx/x)
Output level [dBm]
Output frequency Fo [MHz]
0
–20
–10
0
fout=1MHz sin wave
1 102 5 20 42 1 102 5 20 50
Standard Measurement Conditions
• AVDD=DVDD=5.0 V
• VREF=2.0 V
• FCLK=85 MHZ
• ROUT=200 Ω
• RIR=3.3 kΩ
• Ta=25 °C
Page 15
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CXD2309Q
SNR [dB]
Output frequency Fo [MHz]
30
40
50
Fig. 9. Output frequency vs. SNR
Input current [µA]
Input voltage [V]
1 60
500
1000
5
Fig. 10. Input terminal V-I characteristics
500
1000
–10 1 102 5 20 50
Standard Measurement Conditions
• AVDD=DVDD=5.0 V
• VREF=2.0 V
• FCLK=85 MHZ
• ROUT=200 Ω
• RIR=3.3 kΩ
• Ta=25 °C
Page 16
SONY CODE EIAJ CODE JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN SOLDER / PALLADIUM
PLATING 42/COPPER ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1
+ 0.4
0.8
0.3 – 0.1
+ 0.15
0.24
13
24
2536
37
48
1 12
2.2 – 0.15
+ 0.35
0.9 ± 0.2
0.1 – 0.1
+ 0.2
13.5
0.15 – 0.05
+ 0.1
QFP-48P-L04 QFP048-P-1212
0.7g
0.15
Package Outline Unit : mm
CXD2309Q
—16—
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