Page 1
CXD2302Q
8-bit 50MSPS Video A/D Converter with Clamp Function
Description
The CXD2302Q is an 8-bit CMOS A/D converter
for video with synchronizing clamp function. The
adoption of 2 step-parallel method achieves low
power consumption and a maximum conversion rate
of 50MSPS.
Features
• Resolution: 8 bit ± 1/2LSB (DL)
• Maximum sampling frequency: 50MSPS
• Low power consumption: 125mW (at 50MSPS typ.)
(reference current excluded)
• Synchronizing clamp function
• Clamp ON/OFF function
• Reference voltage self-bias circuit
• Input CMOS/TTL compatible
• 3-state TTL compatible output
• Single 5V power supply or dual 5V/3.3V power supply
• Low input capacitance: 15pF
• Reference impedance: 370Ω (typ.)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD 7V
•Reference voltage VRT,VRBVDD + 0.5 to Vss – 0.5V
• Input voltage VIN VDD + 0.5 to Vss – 0.5V
(Analog)
• Input voltage VI VDD + 0.5 to Vss – 0.5V
(Digital)
• Output voltage VO VDD + 0.5 to Vss – 0.5V
(Digital)
• Storage temperature
32 pin QFP (Plastic)
Tstg –55 to +150 °C
Applications
Wide range of applications that require high-speed
A/D conversion such as TV and VCR.
Structure
Silicon gate CMOS IC
Recommended Operating Conditions
• Supply voltage AVDD, AVss 4.75 to 5.25 V
DVDD, DVss 3.0 to 5.5 V
| DVss – AVss | 0 to 100 mV
• Reference input voltage
VRB 0 and above V
VRT 2.7 and below V
• Analog input VIN 1.7Vp-p above
• Clock pulse width
TPW1, TPW0 9ns (min) to 1.1µs (max)
• Operating ambient temperature
Topr –40 to +85 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94102E78-PS
Page 2
Block Diagram
OE
DVss
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DVDD
TEST (OPEN)
CLK
30
10
12
31
11
CXD2302Q
DVss
28
Reference supply
1
2
3
4
5
6
7
8
Lower
data
latch
Upper
data
latch
Clock generator
Lower encoder
(4 BIT)
Lower encoder
(4 BIT)
Upper encoder
(4 BIT)
Lower
sampling comparator
(4 BIT)
Lower
sampling comparator
(4 BIT)
Upper
sampling comparator
(4 BIT)
25
24
23
22
21
20
19
18
17
16
VRBS
VRB
AVss
AVss
VIN
AVDD
AVDD
VRT
VRTS
AVDD
TEST (OPEN)
NC
32
15
14
13
CLP
NC
NC
9
D-FF
29
CLE CCP V
27
26
REF
– 2 –
Page 3
Pin Description
Pin No. Symbol Equivalent circuit Description
DVDD
Di
1 to 8
D0 to D7
D0 (LSB) to D7 (MSB) output
DVSS
DVDD
CXD2302Q
9
10
11
TEST
DVDD
TEST
15 CLP
29 CLE
11
15
29
9
DVSS
Leave open for normal use.
Digital power supply +5V or +3.3V
Leave open for normal use.
Pull-up resistor is built in.
AVDD
Input the clamp pulse.
Clamps the signal voltage during
Low interval. Pull-up resistor is
built in.
The clamp function is enabled
when CLE = Low.
AVSS
The clamp function is set to off
and the converter functions as a
normal A/D converter when
CLE = High.
Pull-up resistor is built in.
AVDD
12
13, 14, 32
16, 19, 20
CLK
12
Set to Low level when no clock is
input.
Clock input.
AVSS
NC
AVDD Analog power supply +5V
– 3 –
Page 4
Pin No. Symbol Equivalent circuit Description
CXD2302Q
Generates approximately +2.5V
when shorted with AVDD.
Reference voltage (top)
Reference voltage (bottom)
Generates approximately +0.6V
when shorted with AVSS.
AVDD
AVSS
AVDD
RT
AVDD
Rref
AVSS
24
B
R
25
17 VRTS
18 VRT
17
18
24 VRB
25 VRBS
21 VIN Analog input
22, 23
AVSS Analog ground
21
26 VREF
27 CCP
28, 31
DVSS Digital ground
30 OE
26
30
27
Clamp reference voltage input.
Clamps so that the reference
voltage and the input signal during
clamp interval are equal.
AVSS
AVDD
Integrates the clamp control
voltage.
The relationship between the
changes in CCP voltage and in VIN
voltage is positive phase.
AVSS
AVDD
Data is output when OE = Low.
Pins D0 to D7 are at high
impedance when OE = High.
Pull-down resistor is built in.
AVSS
– 4 –
Page 5
Digital output
The following table shows the relationship between analog input voltage and digital output code.
CXD2302Q
Timing Chart I
Clock 1.3V
Analog input
Data output
Clock
Input signal
voltage
TPW1 TPW0
1.3V
VRT
:
:
:
:
VRB
N
4ns
Step
0
:
127
128
:
255
N + 1
Digital output code
MSB LSB
1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
:
0 0 0 0 0 0 0 0
N + 2 N + 3 N + 4
N + 1NN – 1N – 2N – 3
O: Analog signal sampling point
Timing Chart I-1.
tr
tf
4ns
90%
3V
Data output
DD
0.7DV
0.3DVDD
OE input
Output 1
Output 2
10%
tpLH,
tpHL
Timing Chart I-2.
tr = 4.5ns tf = 4.5ns
90%
1.3V
tpZLtpLZ
10%
tpHZ
tpZH
90%
10%
1.3V
1.3V
0V
3V
0V
OH
V
VOL (≠ DVSS)
V
OH (≠ DVDD)
V
OL
Timing Chart I-3.
– 5 –
Page 6
Electrical Characteristics
CXD2302Q
Analog characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Max. conversion rate
Min. conversion rate
Analog input band width
Differential non-linearity error
Integral non-linearity error
Offset voltage
Differential gain error
Differential phase error
Sampling delay
Clamp offset voltage
∗1
∗2
(Fc = 50MHz, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
Fc max.
Fc min.
BW
ED
EL
EOT
EOB
DG
DP
tsd
EOC
AVDD = 4.75 to 5.25V
Ta = –40 to +85°C,
VIN = 0.5 to 2.5V
fIN = 1kHz triangular wave
Envelope
RIN = 33Ω
End point
Potential difference to VRT
Potential difference to VRB
NTSC 40 IRE mod ramp
Fc =14.3MSPS
VIN = DC
CIN = 10µF
–1dB
–3dB
VREF = 0.5V
tpcw = 2.75µs
Fc = 14.3MHz
Fclp = 15.75kHz
VREF = 2.5V
50
–70
20
02040
02040
65
60
100
±0.3
+0.7
–50
40
3
1.5
0
0.5
±0.5
±1.5
–30
60
MSPS
MHz
LSB
mV
%
deg
ns
mV
FIN = 100kHz
FIN = 500kHz
Signal-to-noise ratio
Spurious free dynamic
range
∗1
The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”.
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2LSB of the voltage when the output data changes from “11111111” to “11111110”.
∗2
Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be
generated.
SNR
FSDR
FIN = 1MHz
FIN = 3MHz
FIN = 10MHz
FIN = 25MHz
FIN = 100kHz
FIN = 500kHz
FIN = 1MHz
FIN = 3MHz
FIN = 10MHz
FIN = 25MHz
45
44
44
43
38
32
51
46
49
46
45
45
dB
dB
– 6 –
Page 7
CXD2302Q
DC characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Supply
current
Analog
Digital
Reference current
Reference resistance
(VRT – VRB)
Self-bias voltage
Analog input resistance
Input capacitance
Output capacitance
(Fc = 50MHz, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
IAD + IDD
IAD
IDD
IREF
RREF
VRB
VRT – VRB
RIN
CAI1
CAI2
CDIN
CAO
NTSC ramp
DVDD = 5V
wave input
CLE = 0V
DVDD = 3.3V
Shorts VRTS and AVDD
Shorts VRBS and AVSS
Fc = 50MHz
VIN
Fc = 35MHz
Fc = 20MHz
VIN, VIN = 1.5V + 0.07Vrms
VRTS, VRT, VRB, VRBS, VREF
TEST, CLK, CLP, CLE, OE
CCP
4.1
260
0.52
1.80
25
23
2
5.4
370
0.56
1.92
13
16
30
15
36
33
3
7.7
480
0.60
2.04
11
11
11
mA
mA
Ω
V
kΩ
pF
pF
CDO
D0 to D7, TEST
11
Digital input voltage
Digital input current
Digital output current
VIH
VIL
IIH
IIL
IOH
IOL
IOH
IOL
IOZH
IOZL
AVDD = 4.75 to 5.25V
DVDD = 3 to 5.5V
Ta = –40 to +85°C
CLK
VI = 0V to AVDD
Ta = –40 to +85°C
TEST,
CLP, CLE
OE
OE = 0V
VOH = DVDD – 0.8V
DVDD = 5V
Ta = –40 to +85°C
OE = 0V
VOL = 0.4V
VOH = DVDD – 0.8V
DVDD = 3.3V
Ta = –40 to +85°C
OE = 3V
VOL = 0.4V
VOH = DVDD
DVDD = 3 to 5.5V
Ta = –40 to +85°C
VOL = 0V
2.2
–240
–240
–40
4
2.4
–40
–40
0.8
240
40
240
–2
–1.2
40
40
V
µA
mA
mA
µA
Note) The voltage of up to (AVDD + 0.5V) can be input when DVDD = 3.3V. But the output pin voltage is less
than the DVDD voltage. When the digital output is in the high impedance mode, the IC may be damaged
by applying the voltage which is more than the (DVDD + 0.5V) voltage to the digital output.
– 7 –
Page 8
CXD2302Q
Timing
Item Symbol Conditions Min. Typ. Max. Unit
Output data delay
Tri-state
output enable time
Tri-state
output disable time
Clamp pulse width
∗
The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for
NTSC) for other processing systems to equal the values for NTSC.
∗
(Fc = 50MHz, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpZH
tpZL
tpHZ
tpLZ
tpHZ
tpLZ
tCPW
DVDD = 5V
CL = 15pF
OE = 0V
DVDD = 3.3V
RL = 1kΩ
CL = 15pF
OE = 3V → 0V
RL = 1kΩ
CL = 15pF
OE = 0V → 3V
Fc = 14.3MHz, CIN = 10µF
for NTSC wave
DVDD = 5V
DVDD = 3.3V
DVDD = 5V
DVDD = 3.3V
5.5
4.3
2.5
3.0
3.5
2.5
1.75
9.5
8.5
11.8
7.6
4.5
6.0
7.0
5.0
5.5
5.5
2.75
12.0
16.3
8.0
9.0
7.5
8.0
3.75
ns
ns
ns
µs
Electrical Characteristics Measurement Circuit
Output data delay measurement circuit Tri-state output measurement circuit
Measurement point DVDD
To output pin
Note) CL includes capacitance of probes.
Measurement
point
CL
To output pin
CL RL
RL
– 8 –
Page 9
CXD2302Q
Integral non-linearity error
Differential non-linearity error }test circuit
Offset voltage
+V
S2
S1: ON IF A < B
S2: ON IF B > A
S1
–V
A < B A > B
DVM
VIN
DUT
CXD2302Q
CLK (50MHz)
COMPARATOR
A8
to
A1
A0
"0" "1"
CONTROLLER
B8
to
B1
B0
88
BUFFER
000 · · · 00
8
111 · · · 10
TO
Analog input resistance test circuit
+5V
2.5V
V
DD
VRT
VIN
VRB
0.5V
CLK
GND
Differential gain error
Differential phase error
NTSC
SIGNAL
SOURCE
100
IAE
0
–40
S.G.
(CW)
FC
test circuit
}
40 IRE
MODULATION
BURST
SYNC
AMP
Digital output current test circuit
2.5V
0.5V
CXD
2302Q
8VIN
TTL
ECL
TTL
ECL
8
–5.2V
CX20202A-1
620
CLK
10bit
D/A
–5.2V
VECTOR
SCOPE
D.G
D.P.
620
2.5V
0.5V
VRT
VIN
VRB
CLK
OE
VDD
GND
D0
to
D7
VOL
VDD
I
OL
+
–
2.5V
0.5V
VRT
VIN
VRB
CLK
OE
GND
D0
D7
I
OH
to
VOH
+
–
– 9 –
Page 10
Timing Chart II
CXD2302Q
Vi (1) Vi (2) Vi (3) Vi (4)
Analog input
External clock
Upper comparators block
Upper data
Lower reference voltage
Lower comparators A block
Lower data A
(1) (2) (3) (4)
S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4)
MD (0) MD (1) MD (2) MD (3)
RV (0) RV (1) RV (2) RV (3)
S (1) C (1) S (3) C (3)H (3)H (1)
LD (–1) LD (1)
Lower comparators B block
Lower data B
Digital output
LD (–2) LD (0) LD (2)
C (0) S (2) C (2) S (4)H (0) H (2) H (4)
Out (–2) Out (–1) Out (0) Out (1)
Operation (See Block Diagram and Timing Chart II)
1. The CXD2302Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparator block and 2
lower comparator blocks of 4-bit each. The reference voltage that is equal to the voltage between VRT –
VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper
data is fed through the reference supply to the lower 4-bit comparator block. VRTS and VRBS pins serve
for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom), and they are
also used as the sence pins as shown in the Application Circuit examples I-4 and I-5.
– 10 –
Page 11
CXD2302Q
2. This IC uses an offset cancel type comparator which operates synchronously with an external clock. It
features the following operating modes which are respectively indicated on the timing chart II with S, H, C
symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.
3. The operation of respective parts is as indicated in the Timing Chart II. For instance input voltage Vi (1) is
sampled with the falling edge of the external clock (1) by means of the upper comparator block and the
lower comparator A block.
The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2).
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to
the upper results. The lower comparator A block finalizes comparison data LD (1) with the rising edge of
the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the
external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital
data output.
Operation Notes
1. VDD, VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital
and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass
to the respective GND’s.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be
prevented by insetting a resistance of about 33Ω in series between the amplifier output and A/D input.
When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect
on the characteristics of A/D conversion.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins
to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VDD and
VRTS, VSS and VRBS respectively, the self-bias function that generates VRT=about 2.5V and VRB=about
0.6V, is activated.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay
of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is
about 9ns (DVDD = 5V).
6. OE pin
Pins 1 to 8 (D0 to D7) are in the output mode by leaving OE open or connecting it to DVSS, and they are in
the high impedance mode by connecting it to DVDD.
– 11 –
Page 12
Application Circuit
I. Single +5V Power Supply
I-1. When clamp is used (self-bias used)
CXD2302Q
+5V (Digital)
ACO4
CLOCK IN
CLAMP PULSE IN
+5V (Analog)
VIDEO IN
10µ 33Ω
+5V (Analog)
I-2. Digital clamp (self-bias used)
10p
0.01µ
0.1µ
0.01µ
V
REF
20K
16
17
18
19
20
21
22
23
24
25
GND (Analog)
26
1415
27
13
28
0.01µ
12
29
10
11
31
30
GND (Digital)
OPEN
9
32
0.1µ
8
7
6
5
4
3
2
1
D
D6
D5
D4
D3
D2
D1
D0
7
ACO4
CLOCK IN
0.01µ
+5V (Analog)
VIDEO IN
∗
The relationship between the changes
10µ 33Ω
10p
in CCP voltage (Pin 27) and in V
voltage is positive phase.
∗
∆Vin/∆Vccp = 3.0 (fs = 20MSPS)
0.1µ
0.01µ
IN
16
17
18
19
20
21
22
23
24
25
GND (Analog)
26
1415
27
13
28
12
29
OPEN
10
11
31
30
GND (Digital)
32
+5V (Digital)
0.1µ
9
8
7
6
5
4
3
2
1
Subtracter
·
Comparator
·
etc.
DAC
·
PWM
·
etc.
Clamp level
setting data
← Information other than
that for clamp interval
is at high impedance.
– 12 –
Page 13
I-3. When clamp is not used (self-bias used)
CXD2302Q
+5V (Digital)
ACO4
CLOCK IN
0.01µ
+5V (Analog)
VIDEO IN
33Ω
0.1µ
10p
0.01µ
I-4. When clamp is used (self-bias not used)
17
18
19
20
21
22
23
24
16
26
25
GND (Analog)
1415
27
13
28
12
29
10
11
31
30
GND (Digital)
OPEN
9
32
0.1µ
8
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK IN
CLAMP PULSE IN
VRT
VIDEO IN
VRB
+5V (Analog)
+5V (Analog)
ACO4
10µ
33Ω
10p
0.01µ
0.01µ
0.1µ
REF
V
20K
16
17
18
19
20
21
22
23
24
25
GND (Analog)
26
27
+5V (Digital)
0.1µ
OPEN
13
28
0.01µ
12
29
11
30
1415
9
10
32
31
GND (Digital)
8
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D1
D0
– 13 –
Page 14
I-5. When clamp is not used (self-bias not used)
CXD2302Q
+5V (Digital)
ACO4
CLOCK IN
VRT
+5V (Analog)
VIDEO IN
VRB
0.01µ
33Ω
0.1µ
10p
0.01µ
II. Dual +5V/+3.3V Power Supply
II-1. When clamp is used (self-bias used)
17
18
19
24
20
21
22
23
16
26
25
GND (Analog)
1415
27
13
28
12
29
10
11
31
30
GND (Digital)
OPEN
9
32
0.1µ
8
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK IN
CLAMP PULSE IN
VIDEO IN
ACO4
+5V (Analog)
10µ 33Ω
10p
+5V (Analog)
0.01µ
0.1µ
0.01µ
V
REF
20K
16
17
18
19
20
21
22
23
24
25
GND (Analog)
26
1415
27
13
28
0.01µ
12
29
10
11
31
30
GND (Digital)
OPEN
9
32
8
7
6
5
4
3
2
1
+3.3V (Digital)
0.1µ
D7
D6
D5
D4
D3
D2
D1
D0
– 14 –
Page 15
Example of Representative Characteristics
CXD2302Q
Ambient temperature vs. Supply current
Fc = 50MHz
26
25
24
Supply current [mA]
–20 0 25 50 75
Ambient temperature [°C]
NTSC ramp wave input
AVDD = DVDD = 5V
Sampling frequency vs. Supply current
25
20
15
Supply current [mA]
10 30 40 50
20
Sampling frequency [MSPS]
NTSC ramp wave input
AVDD = DVDD = 5V
Ta = 25°C
Supply voltage vs. Supply current
27
25
23
Supply current [mA]
4.75 5 5.25
Supply voltage [V]
Input frequency vs. Supply current
Fc = 50MHz
Sine wave 1.9Vp-p
35
AVDD = DVDD = 5V
Ta = 25°C
30
25
Supply current [mA]
0.01 1 10 25
0.1
Input frequency [MHz]
Fc = 50MHz
NTSC ramp wave input
AVDD = DVDD
Ta = 25°C
Ambient temperature vs. Maximum operating frequency
70
65
60
–20 25 50 75
Maximum operating rate [MSPS]
0
Ambient temperature [°C]
Fc = 50MHz
fin = 1kHz, triangular wave input
AVDD = DVDD = 5V
Ambient temperature vs. Sampling delay
Fc = 50MHz
1
0
–1
Sampling delay [ns]
AVDD = DVDD = 5V
Supply voltage vs. Maximum operating frequency
Fc = 50MHz
NTSC ramp wave input
67
AVDD = DVDD
65
63
Maximum operating rate [MSPS]
4.75 5 5.25
Supply voltage [V]
Analog input band
Fc = 50MHz
0
–1
Output level [dB]
–3
Sine wave 1Vp-p input
AVDD = DVDD = 5V
Ta = 25°C
0
–20 25 50 75
Ambient temperature [°C]
– 15 –
0.1 10 100
1
Analog input frequency [MHz]
Page 16
CXD2302Q
Analog input frequency vs. SNR, effective bit
50
8
7
40
6
SNR [dB]
5
Effective bit [bit]
30
0.01 0.1 1 10
Analog input frequency [MHz]
Ambient temperature vs. Output data delay
Fc = 10MHz
12
10
8
Output data delay [ns]
6
tp
tpHL
–20 25 50 75
Ambient temperature [°C]
LH
0
AVDD = DVDD = 5V
CL = 15pF
Fc = 50MHz
AVDD = DVDD = 5V
VIN = 2Vp-p
Ta = 25°C
Analog input frequency vs. FSDR
60
50
40
FSDR [dB]
30
0.01 1 10
0.1
Analog input frequency [MHz]
Fc = 50MHz
AVDD = DVDD = 5V
VIN = 2Vp-p
Ta = 25°C
Ambient temperature vs. Output data delay
12
10
8
Output data delay [ns]
6
tpLH
tpHL
0
–20 25 50 75
Ambient temperature [°C]
Fc = 10MHz
AVDD = 5V
DVDD = 3.3V
CL = 15pF
Load capacitance vs. Output data delay
Fc = 10MHz
AVDD = DVDD = 5V
12
10
8
Output data delay [ns]
6
Ta = 25°C
tpLH
tpHL
5152025
0
10
Load capacitance [pF]
DVDD supply voltage vs. Output data delay
Fc = 10MHz
LH
12
10
Output data delay [ns]
tp
8
tpHL
6
3.5
3 4.5 5 5.5
DVDD supply voltage [V]
AVDD = 5V
CL = 15pF
Ta = 25°C
Load capacitance vs. Output data delay
14
12
10
8
Output data delay [ns]
6
0
51525
Analog input voltage vs. Input current
[µA]
80
AI
0
–80
Analog input current I
0.5 1.5 2.5
Analog input voltage VIN [V]
tpLH
tpHL
10 20
Load capacitance [pF]
Fc = 50MHz
AVDD = DVDD = 5V
VRT = 2.5V
VRB = 0.5V
Ta = 25°C
Fc = 10MHz
AVDD = 5V
DVDD = 3.3V
Ta = 25°C
– 16 –
Page 17
CXD2302Q
8-bit 50MSPS ADC and DAC Evaluation Board
Evaluation boards are available for the high speed, low power consumption CMOS converters CXD2302Q
(8-bit 50MHz A/D) and CXD1171M (8-bit 40MHz D/A).
The evaluation boards are composed of a main board, CXD2302Q sub board and CXD1171M sub board. The
each board is connected with sockets.
An input interface, clock buffer and latches are mounted on the main board. The CXD2302Q and CXD1171M
are mounted on each of the sub boards. Those ICs are mounted according to recommended print patterns
designed to provide maximum performance to the A/D and D/A converters.
Block Diagram
V OUT
V IN
ANALOG CIRCUIT
MOUNT PORTION
V REF
ANALOG INPUT
INTERFACE
ANALOG CIRCUIT
MOUNT PORTION
8
DAC
SOCKET
DIGITAL
CIRCUIT MOUNT
PORTION
8
ADC
4
SOCKET
BUFFER
–5V+5VGND CLOCK OE SEL SYNC CLE BLK
DATA LATCH
CLOCK
OSC
SW
Unnecessary
at self bias use
Characteristics
• Resolution 8bit
• Maximum conversion rate 50MHz
• Digital input level CMOS level
• Supply voltage ±5.0V (Single +5V power supply possible at self bias use)
Supply voltage
Item
Min. Typ.
+5V
–5V
Clock input
CMOS compatible
Pulse width TCW1 10ns (min)
TCW0 10ns (min)
Max. Unit
185
20
mA
– 17 –
Page 18
Analog Output (CXD1171M) (RL > 10kΩ)
CXD2302Q
Item
Min. Typ. Max. Unit
Analog output 1.8 2.0 2.1 V
Output Format (CXD2302Q)
The table shows the output format of AD Converter.
Analog input
voltage
VRT
:
:
:
:
VRB
Step
0
:
127
128
:
255
Digital output code
MSB LSB
11111111
:
10000000
01111111
:
00000000
Timing Chart
Analog input
External clock
Tpw0
Tpw1
Item
Clock High time
Clock Low time
Clock Delay
Data delay AD
AD clock
AD output
Latch output
DA input
DA clock
DA output
Tdc
tPD (AD)
ts
tPD (DA)
Symbol Min.
TPW1
TPW0
Tdc
tPD (AD)
tDD
10
10
th
Typ.
Max.
Unit
ns
ns
24
9
ns
ns
Data delay (latch)
Settling time
Hold time
Data delay DA
tDD
tS
th
tPD (DA)
5
10
– 18 –
10
17
ns
ns
ns
ns
Page 19
DD
DV
CXD2302Q
75
R10
IN = 75Ω)
SYNC INT
47µ
(R
20k
VR5
SS
1
14
0.01µ
DV
8
7
OSC out
INPUT
75
EXTERNAL CLOCK
R9
EXT/INT
OSC SWITCH
BLK
1
3
2
(INV BUFFER)
74S04
12
14
13
DD
DV
OE
SEL
CLE
0.01µ
SYNC
0.01µ
SS
DV
7
8
4
6
5
OR
74HC04
9
11
10
8
7
4
6
3
5
2
CLEAR
SS
DV
1
8
7
4
6
5
CLEAR
1
3
2
0.01µ
74S174
(LATCH)
CLK
9
11
10
12
13
9
11
10
12
13
CLK DVSS
16
14
15
DD
DV
74S174
(LATCH)
16
14
15
DD
DV
DVSS
DVSS
DVDD
6
8
7
9
11
10
12
SS
NC
DV
DVDD
NCNCAVSSAVSS
14
13
GAIN
ADJUST
OUTPUT
D7D6D5D4D3D2D1
BLK
CLK
IREF
VREF
16
15
17
18
(16R)
R8 3.3k
20k
VR4
C5
0.1
AVDDAVDDIOIONCDV
19
5
20
R7 200
3
2
4
21
1
D0
DD
SW1
24
23
22
13
12
14
CLK
CLPNCNC
16
15
17
9
11
10
DD
D7D6D5D4D3D2D1
DV
RT
AVDD
V
20
19
18
V out
(R)
SW2
C3
0.01
6
8
7
AVDD
VIN
AVSS
21
23
22
3
4
25
0.01
D0
VRB
26
SW3
VR3
2
SS
DV
VREF
27
20k
1
OE
CLE
28
47µ
0.01
DV
DD
DD
AV
GND
+5V
–5V
5
AVSS
24
C4
CMOS ADC/DAC Peripheral Circuit Board (Main Board)
VRT
ADJUST
VRB
ADJUST
DD
AV
R4
Q2
VR2
510
33
R3
C2
AVDD
10µ
R5
510
AVSS
2k
Q1
Q3
VR1
R6
510
2k
VIDEO INPUT
R2
R1
C1
AVSS
75
470µ
100k
CLAMP
ADJUST
VOLTAGE
– 19 –
Page 20
CMOS ADC/DAC Peripheral Circuit Board (Sub Board)
CXD2302Q
CLP
NC
NC
RT
V
AVDD
AVDD
VIN
AVSS
AVSS
VRB
VREF
CLE
17
15
16
18
19
20
23
21
22
24
25
26
27
28
C3
0.1µ
C5
C4
JT
JB
17
18
19
20
23
24
21
22
16
25
1415
26
27
C1 0.01µ
13
12
CXD2302Q
28
29
30
11
10
31
32
14
13
9
8
7
6
5
4
3
2
1
C2 0.1µ
12
11
10
CLK
DV
DD
D7
9
D6
8
D5
7
D4
6
D3
5
D2
4
D1
3
D0
2
DV
SS
1
OE
NC
NC
SS
AV
AVSS
IREF
VREF
AVDD
AVDD
IO
IO
NC
DD
DV
17
13
14
15
16
18
19
20
23
21
22
24
13
14
15
16
17
C2C3
18
CXD1171M
19
20
21
22
23
24
12
11
10
12
NC
11
DV
10
SS
CLK
9
BLK
8
D7
7
D6
6
D5
5
D4
4
D3
3
D2
2
D1
1
D0
C4
9
8
7
6
5
4
3
2
1
C1
– 20 –
Page 21
List of Parts
CXD2302Q
resistance
R1 100K
R2 75Ω
R3 75Ω
R4 510Ω
R5 510Ω
R6 510Ω
R7 R = 200
R8 18R ≈ 3.3K
R9 75Ω
R10 75Ω
VR1 2K
VR2 2K
VR3 20K
VR4 20K
VR5 20K
capacitance
C1 470µF/6.3V (chemical)
C2 10µF/16V (chemical)
C3 0.01µF
C4 0.01µF
C5 0.1µF
C6 0.1µF
C7 0.1µF
C8 0.1µF
C9 0.1µF
C10 0.1µF
C11 47µF/10V (chemical)
C12 47µF/10V (chemical)
C13 47µF/10V (chemical)
C14 0.1µF
transistor
Q1 2SC2785
Q2 2SC2785
Q3 2SC2785
IC
IC1 74S174
IC2 74S174
IC3 74S04
oscillator
OSC
others
connector BNC071
SW AT1D2M3
Adjustment
1. Vref adjustment (VR1, VR2)
Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2.
When self bias is used, there is no need for adjustment. Reference voltage is set through self bias delivery.
2. Setting of clamp reference voltage (VR3)
Clamp reference voltage is set.
3. DAC output full scale adjustment (VR4)
Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is
adjusted to approx. 2V.
4. Sync (clamp) pulse interface (VR5)
This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is
performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V.
– 21 –
Page 22
CXD2302Q
5. OE, SEL, Sync, BLK, CLE, Sync INT
The following pins are set on the main board: OE, Sync, CLE, Sync INT (CXD2302Q), BLK (CXD1171M)
and SEL (not used). For the pins function, refer to the Pin Description. The difference between Sync pin
and Sync INT pin is that a pulse above 3.5Vp-p should be input to Sync INT pin. The pulse threshold is set
through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the
junction line between Sync and Sync INT pin.
At the PCB shipment the main board pins are set as follows.
• OE : Low (A/D output ON)
• SEL : Low
• Sync : Line junction Sync INT pin
• CLE : Low (Clamp function ON)
• BLK : Low (Blanking OFF)
6. Clamp pulse input method
Directly input the clamp pulse as shown in Application Circuit example I-1. As SW1 is set to direct input at
the PCB shipment, use it in this position.
Points on the PCB Pattern Layout
1. Set the layout not to have Digital current flow into Analog GND (For 1, see p.24 “Component side
diagram”.).
2. The C2 and C3 capacitors for the CXD2302Q sub board serve the important role of bringing out ICs full
performance.
Connect over 0.1µF (ceramic) capacitors with good high frequency characteristics as close to the IC as
possible.
3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage supply source. Keeping ADC’s
DVSS (For 2, see p.24 “Component side diagram”.) as close to the voltage supply source as possible will
provide better characteristics. That is, a layout where ADC is close to the voltage supply source, is
recommended.
4. ADC samples analog signals at the clock falling edge. Accordingly it is important that clocks supplied to
ADC do not have any jitter.
5. The PCB layout shows ADC and DAC’s Analog GND independently from the voltage supply source. The
layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual
board, common use will not cause any problems.
– 22 –
Page 23
CXD2302Q
Notes on Operation
1. Reference voltage
Shorting AVDD and VRTS, AVSS and VRBS will activate the self-bias function that generates VRT = about 2.6V
and VRB=about 0.5V. On the PCB, either self bias or the external reference voltage can be selected
depending on the junction method of the jumper line. At shipment from the factory, reference voltage is
provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (VRT – VRB) to
above 1.8Vp-p.
2. Clock input
There are 2 modes for the PCB clock input
1) Provided from the external signal generator. (External clock)
2) Using the crystal oscillator (built-in clock driver). (Internal clock)
The 2 modes are selected using the switch on the PCB.
3. The 2 Latch ICs (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is,
operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output
data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate
an example layout of Digital signal processing IC. Use the Latch IC output when the ADC output data is
used.
4. When clamp is not used
Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on
the main board and DC voltage on the ADC side of C2 turns to about (VRT+VRB)/2. To transfer DC elements
of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can
also be used as buffer. Use the open space for the bias circuit.
5. Clamp pulse latch
On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to CLP pin.
However, the latch is incorporated in CLP pin of the CXD2302Q, so that the external latch is not required.
6. Peripheral through hole
There is a group of through holes on the Analog input, output and Logic. There are to be used when
mounting additional circuits to the PCB. Use when necessary.
The connector hole on DAC part is used to mount the test chassis mount jack.
– 23 –
Page 24
Silk Side
Component Side
CXD2302Q
Soldering Side (Diagram seen from the component side)
– 24 –
Page 25
Package Outline Unit: mm
CXD2302Q
32PIN QFP (PLASTIC)
25
32
9.0 ± 0.2
+ 0.3
7.0 – 0.1
+ 0.35
1.5 – 0.15
0.1
1724
16
(8.0)
9
+ 0.2
0.1 – 0.1
1
0.8 0.3 – 0.1
+ 0.15
8
± 0.12
+ 0.1
M
0.127 – 0.05
0.50
0° to 10°
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-32P-L01
∗QFP032-P-0707-A
– 25 –
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
42 ALLOY
0.2g
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