Page 1
Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD2497R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX252, ICX262 CCD image sensor.
Features
• Base oscillation frequency 24 to 36MHz
• High-speed/low-speed shutter function
• Draft (sextuple speed)/AF (auto focus) drive
• Horizontal driver for CCD image sensor
• Vertical driver for CCD image sensor
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX252 (Type 1/1.8, 3240K pixels)
ICX262 (Type 1/1.8, 3240K pixels)
Pin Configuration
Absolute Maximum Ratings
• Supply voltage VDD VSS – 0.3 to +7.0 V
VL –10.0 to VSS V
VH VL – 0.3 to +26.0 V
• Input voltage VI VSS – 0.3 to VDD + 0.3 V
• Output voltage VO1 VSS – 0.3 to VDD + 0.3 V
VO2 VL – 0.3 to VSS + 0.3 V
VO3 VL – 0.3 to VH + 0.3 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDDb 3.0 to 5.5 V
VDDa, VDDc, VDDd
3.0 to 3.6 V
VM 0.0 V
VH 14.5 to 15.5 V
VL –7.0 to –8.0 V
• Operating temperature
Topr –20 to +75 °C
– 1 –
E99Y23-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD2497R
48 pin LQFP (Plastic)
∗
Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
1 2 3 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
2526272829
30
313233343536
37
38
39
40
41
42
43
44
45
46
47
48
H2
V
DD3
V
DD4
XSHP
XSHD
XRS
PBLK
CLPDM
V
SS4
OBCLP
ADCLK
V
SS5
CKO
CKI
OSCO
OSCI
V
DD5
MCKO
SSI
SCK
SEN
VD
HD
V
SS6
H1
V
SS3VSS2
RG
V
DD2
SSGSL
V
DD1
WEN
ID
SNCSL
RST
V
SS1
TEST2
SUB
V3B
VL
V3A
V1B
VH
V1A
V4
V2
VM
TEST1
Page 2
– 2 –
CXD2497R
Block Diagram
35 34
39
44
43
41
5
4
24
23
22
20
19
2118171615
10
9811131214
28
27
26
25
30
V1B
V2
V3A
V1A
WEN
ID
V
SS5
ADCLK
OBCLP
CLPDM
PBLK
VSS4
XRS
XSHD
XSHP
V
DD4
V
SS2
RG
V
DD2
V
SS3
H2
H1
V
DD3
VD
HD
7 29 1
VSS136VSS6
V
DD5VDD1
MCKO
CKO
CKI
OSCO
OSCI
Pulse Generator
2
37
48
TEST2
TEST1
RST
45
38
42
47
40
46
VL
VM
VH
SUB
V4
V3B
31
32
33
SEN
SCK
SSI
Register
V Driver
6
SSGSL
3
SNCSL
1/2
Selector
Selector
Latch
SSG
Page 3
– 3 –
CXD2497R
Pin Description
GND
Internal system reset input. High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
With pull-down resistor
Vertical direction line identification pulse output.
Memory write timing pulse output.
Internal SSG enable. High: Internal SSG valid, Low: External sync valid
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output.
GND
GND
CCD horizontal register clock output.
CCD horizontal register clock output.
3.3 to 5.0V power supply. (Power supply for H1/H2)
3.3V power supply. (Power supply for CDS block)
CCD precharge level sample-and-hold pulse output.
CCD data level sample-and-hold pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD dummy signal clamp pulse output.
GND
CCD optical black signal clamp pulse output.
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
GND
Inverter output.
Inverter input.
Inverter output for oscillation. When not used, leave open or connect a capacitor.
Inverter input for oscillation. When not used, fix low.
3.3V power supply. (Power supply for common logic block)
System clock output for signal processing IC.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS1
RST
SNCSL
ID
WEN
SSGSL
VDD1
VDD2
RG
VSS2
VSS3
H1
H2
VDD3
VDD4
XSHP
XSHD
XRS
PBLK
CLPDM
VSS4
OBCLP
ADCLK
VSS5
CKO
CKI
OSCO
OSCI
VDD5
MCKO
—
I
I
O
O
I
—
—
O
—
—
O
O
—
—
O
O
O
O
O
—
O
O
—
O
I
O
I
—
O
Pin
No.
Symbol
I/O Description
Page 4
– 4 –
CXD2497R
Serial interface data input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Serial interface clock input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Serial interface strobe input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Vertical sync signal input/output.
Horizontal sync signal input/output.
GND
IC test pin 1; normally fixed to GND. With pull-down resistor
GND (GND for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
CCD vertical register clock output.
15.0V power supply. (Power supply for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
–7.5V power supply. (Power supply for vertical driver)
CCD vertical register clock output.
CCD electronic shutter pulse output.
IC test pin 2; normally fixed to GND. With pull-down resistor
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SSI
SCK
SEN
VD
HD
VSS6
TEST1
VM
V2
V4
V1A
VH
V1B
V3A
VL
V3B
SUB
TEST2
I
I
I
I/O
I/O
—
I
—
O
O
O
—
O
O
—
O
O
I
Pin
No.
Symbol
I/O
Description
Page 5
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CXD2497R
Electrical Characteristics
DC Characteristics (Within the recommended operating conditions)
VDD2
VDD3
VDD4
VDD1, VDD5
RST
SSI, SCK,
SEN,
TEST1,
TEST2
SNCSL,
SSGSL
VD, HD
H1, H2
RG
XSHP, XSHD,
XRS, PBLK,
OBCLP,
CLPDM, ADCLK
CKO
MCKO
ID, WEN
V1A, V1B,
V3A, V3B,
V2, V4
SUB
VDDa
VDDb
VDDc
VDDd
Vt+
Vt–
Vt+
Vt–
VIH1
VIL1
VIH2
VIL2
VIH3
VIL3
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VOH5
VOL5
VOH6
VOL6
VOH7
VOL7
IOL
IOM1
IOM2
IOH
IOSL
IOSH
3.0
3.0
3.0
3.0
0.8VDDd
0.8VDDd
0.7VDDd
0.7VDDd
0.8VDDd
VDDd – 0.8
VDDb – 0.8
VDDa – 0.8
VDDc – 0.8
VDDd – 0.8
VDDd – 0.8
VDDd – 0.8
10.0
5.0
5.4
3.3
3.3
3.3
3.3
3.6
5.5
3.6
3.6
0.2VDDd
0.2VDDd
0.2VDDd
0.3VDDd
0.2VDDd
0.4
0.4
0.4
0.4
0.4
0.4
0.4
–5.0
–7.2
–4.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Feed current where IOH = –1.2mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –22.0mA
Pull-in current where IOL = 14.4mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –6.9mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
V1A/B, V2, V3A/B, V4 = –8.25V
V1A/B, V2, V3A/B, V4 = –0.25V
V1A/B, V3A/B = 0.25V
V1A/B, V3A/B = 14.75V
SUB = –8.25V
SUB = 14.75V
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Input voltage 1
∗1
Input voltage 2
∗2
Input voltage 3
∗3
Input voltage 4
∗4
Input/output
voltage
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Output voltage 5
Output voltage 6
Output current 1
Output current 2
Item Pins
Symbol
Conditions Min. Typ. Max. Unit
∗1
This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC.
∗2
These input pins are schmitt trigger inputs.
∗3
These input pins are with pull-down resistor in the IC.
∗4
These input pins are with pull-down resistor in the IC and they do not have protective diode of the power
supply side in the IC.
Note) The above table indicates the condition for 3.3V drive.
Page 6
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CXD2497R
Inverter I/O Characteristics for Oscillation (Within the recommended operating conditions)
Item
Logical Vth
Input
voltage
Output
voltage
Feedback
resistor
Oscillation
frequency
Pins
OSCI
OSCI
OSCO
OSCI,
OSCO
OSCI,
OSCO
Symbol
LVth
VIH
VIL
VOH
VOL
RFB
f
Conditions
Feed current where IOH = –3.6mA
Pull-in current where IOL = 2.4mA
VIN = VDDd or VSS
Min.
0.7VDDd
VDDd – 0.8
500k
20
Typ.
VDDd/2
2M
Max.
0.3VDDd
0.4
5M
50
Unit
V
V
V
V
V
Ω
MHz
Item
Logical Vth
Input
voltage
Input
amplitude
Pins
CKI
Symbol
LVth
VIH
VIL
VIN
Conditions
fmax 50MHz sine wave
Min.
0.7VDDd
0.3
Typ.
VDDd/2
Max.
0.3VDDd
Unit
V
V
V
Vp-p
Item
Rise time
Fall time
Output noise voltage
Symbol
TTLM
TTMH
TTLH
TTML
TTHM
TTHL
VCLH
VCLL
VCMH
VCML
Conditions
VL to VM
VM to VH
VL to VH
VM to VL
VH to VM
VH to VL
Min.
200
200
30
200
200
30
Typ.
350
350
60
350
350
60
Max.
500
500
90
500
500
90
1.0
1.0
1.0
1.0
Unit
ns
ns
ns
ns
ns
ns
V
V
V
V
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics (VH = 15.0V, VM = GND, VL = –7.5V)
Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more)
between each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image
sensor.
Page 7
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CXD2497R
Switching Waveforms
V1A (V1B, V3A, V3B)
V2 (V4)
SUB
TTMH TTHM
VH
VM
VL
VM
VL
VH
VL
90%
10%
90%
10%
TTLM
TTLM
90%
10%
90%
10%
TTLH TTHL
90%90%
10% 10%
TTML
90%
10%
TTML
90%
10%
Waveform Noise
VCMH
VCML
VH
VL
VCLH
VCLL
Page 8
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CXD2497R
Measurement Circuit
1 2 3 4 5 6 7 8 9 10 11 12
13
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21
22
23
24
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30
313233343536
37
38
39
40
41
42
43
44
45
46
47
48
VD
CKI
C6
C6
C6
C6
C6
C6
C6
C6
C6
C5
C5C4
C3
CXD2497R
Serial interface data
HD
+3.3V
–7.5V
+15.0V
C2
C2 C2
C2
C2
R1
R1
R1
R2
R1
R1 R1
C2
C2
C2
C2
C2
C2
C2
C2
C2
C1
C1
C1
C1
C1
C1
C2
C1 3300pF C2 560pF C3 820pF C4 30pF C5 215pF C6 10pF
R1 30Ω R2 10Ω
Page 9
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CXD2497R
AC Characteristics
AC characteristics between the serial interface clocks
SSI
0.2V
DDd
0.2VDDd
0.8VDDd
ts2
th1ts1
ts3
0.8V
DDd
0.8VDDd
SCK
SEN
SEN
Symbol
ts1
th1
ts2
ts3
Definition
SSI setup time, activated by the rising edge of SCK
SSI hold time, activated by the rising edge of SCK
SCK setup time, activated by the rising edge of SEN
SEN setup time, activated by the rising edge of SCK
Min. Typ. Max.
20
20
20
20
Unit
ns
ns
ns
ns
Serial interface clock internal loading characteristics (1)
(Within the recommended operating conditions)
th1
Enlarged view
Example: During frame mode
0.2V
DDd
ts1
0.2V
DDd
V1A
VD
HD
HD
V1A
SEN
0.8V
DDd
Symbol
ts1
th1
Definition
SEN setup time, activated by the falling edge of HD
SEN hold time, activated by the falling edge of HD
Min. Typ. Max.
0
102
Unit
ns
µs
∗
Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Page 10
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CXD2497R
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2497R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD2497R and controlled at the rising edge of SEN. See "Description of Operation".
0.8VDDd
SEN
Output signal
tpdPULSE
Symbol
tpdPULSE
Definition
Output signal delay, activated by the rising edge of SEN
Min. Typ. Max.
1005
Unit
ns
(Within the recommended operating conditions)
Serial interface clock internal loading characteristics (2)
th1
Enlarged view
0.2V
DDd
ts1
0.2V
DDd
VD
HD
VD
HD
SEN
0.8V
DDd
Example: During frame mode
Symbol
ts1
th1
Definition
SEN setup time, activated by the falling edge of VD
SEN hold time, activated by the falling edge of VD
Min. Typ. Max.
0
200
Unit
ns
ns
∗
Be sure to maintain a constantly high SEN logic level near the falling edge of VD.
(Within the recommended operating conditions)
Page 11
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CXD2497R
RST
0.2VDDd
tw1
0.8VDDd
VD, HD
MCKO
ts1
th1
0.2V
DDd
0.8VDDd
0.2VDDd
RST loading characteristics
Symbol
tw1
Definition
RST pulse width
Min. Typ. Max.35Unit
ns
(Within the recommended operating conditions)
VD and HD loading characteristics
Symbol
ts1
th1
Definition
VD and HD setup time, activated by the rising edge of MCKO
VD and HD hold time, activated by the rising edge of MCKO
Min. Typ. Max.
20
5
Unit
ns
ns
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
0.8VDDd
MCKO
WEN, ID
tpd1
WEN and ID load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Time until the above outputs change after the rise of MCKO
Min. Typ. Max.
6020
Unit
ns
Output variation characteristics
Page 12
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CXD2497R
Description of Operation
Pulses output from the CXD2497R are controlled mainly by the RST pin and by the serial interface data. The
Pin Status Table is shown below, and the details of serial interface control are described on the following
pages.
Pin Status Table
∗1
It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45),
respectively, in the controlled status.
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS1
RST
SNCSL
ID
WEN
SSGSL
VDD1
VDD2
RG
VSS2
VSS3
H1
H2
VDD3
VDD4
XSHP
XSHD
XRS
PBLK
CLPDM
VSS4
OBCLP
ADCLK
VSS5
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
L
ACT
L
L
L
L
L
L
L
L
L
L
ACT
ACT
L
L
ACT
L
L
L
L
L
L
L
L
L
L
L
ACT
L
L
ACT
ACT
ACT
ACT
ACT
ACT
ACT
H
H
H
ACT
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CKO
CKI
OSCO
OSCI
VDD5
MCKO
SSI
SCK
SEN
VD
∗1
HD
∗1
VSS6
TEST1
VM
V2
V4
V1A
VH
V1B
V3A
VL
V3B
SUB
TEST2
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
L
VM
VM
VH
VH
VH
VH
VH
L
ACT
ACT
ACT
L
ACT
ACT
ACT
L
L
VM
VM
VH
VH
VH
VH
VH
ACT
ACT
ACT
ACT
ACT
DIS
DIS
DIS
H
H
VM
VL
VM
VM
VL
VL
VL
Symbol CAM SLP STB RST
Pin
No.
Symbol CAM
SLP STB
RST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Page 13
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CXD2497R
Serial Interface Control
The CXD2497R basically loads and reflects the serial interface data sent in the following format in the readout
portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and
V3A/B, etc. take the ternary value.
Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN.
SSI
SCK
SEN
00 01 02 03 04 05 06 07 41 42 43 44 45 46 47
There are two categories of serial interface data: CXD2497R drive control data (hereafter "control data") and
electronic shutter data (hereafter "shutter data").
The details of each data are described below.
Page 14
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CXD2497R
Control Data
Data
D00
to
D07
D08
to
D09
D10
to
D12
D13
to
D14
D15
D16
to
D23
D24
to
D33
D34
D35
D36
to
D37
D38
to
D39
D40
to
D47
Symbol
CHIP
CTG
MODE
SMD
PTSG
CDAT
—
—
—
LDAD
STB
—
Function
Chip enable
Category switching
Drive mode switching
Electronic shutter mode switching
Internal SSG output pattern switching
AF drive control data
—
—
—
ADCLK logic phase switching
Standby control
—
Data = 0 Data = 1
10000001 → Enabled
Other values → Disabled
See D08 to D09 CTG.
See D10 to D12 MODE.
See D13 to D14 SMD.
NTSC equivalent PAL equivalent
See D16 to D23 CDAT.
— —
— —
— —
See D36 to D37 LDAD.
See D38 to D39 STB.
— —
RST
All
0
All
0
All
0
All
0
0
All
0
All
0
1
0
All
0
All
0
1
0
Page 15
– 15 –
CXD2497R
Shutter Data
Data
D00
to
D07
D08
to
D09
D10
to
D19
D20
to
D31
D32
to
D41
D42
to
D47
Symbol
CHIP
CTG
SVD
SHD
SPL
—
Function
Chip enable
Category switching
Electronic shutter vertical period
specification
Electronic shutter horizontal period
specification
High-speed shutter position
specification
—
Data = 0 Data = 1
10000001 → Enabled
Other values → Disabled
See D08 to D09 CTG.
See D10 to D19 SVD.
See D20 to D31 SHD.
See D32 to D41 SPL.
— —
RST
All
0
All
0
All
0
All
0
All
0
All
0
Page 16
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CXD2497R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD2497R by the serial interface, the CXD2497R loads D10 and subsequent data
to each data register as shown in the table below according to the combination of D08 and D09 .
D09
0
0
1
D08
0
1
X
Description of operation
Loading to control data register
Loading to shutter data register
Test mode
Note that the CXD2497R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD2497R drive mode can be switched as follows. However, the drive mode bits are loaded to the
CXD2497R and reflected at the falling edge of VD.
D11
0
0
1
1
0
1
D12
0
0
0
0
1
1
D10
0
1
0
1
X
X
Description of operation
Draft mode (sextuple speed: default)
Frame mode (A field readout)
Frame mode (B field readout)
Frame mode
AF1 mode
AF2 mode
Control data: D15 PTSG [Internal SSG output pattern]
The CXD2497R internal SSG output pattern can be switched as follows. However, the drive mode bits are
loaded to the CXD2497R and reflected at the falling edge of VD.
D15
0
1
Description of Operation
NTSC equivalent pattern
PAL equivalent pattern
VD period in each pattern is defined as follows.
∗1
Only 944H and 945H are 1208ck period.
See the Timing Charts for the actual operation.
NTSC equivalent pattern
PAL equivalent pattern
Frame mode
918H + 1716ck
945H
∗1
Draft mode
262H + 1144ck
314H + 1568ck
AF1 mode
131H + 572ck
157H + 784ck
AF2 mode
65H + 1430ck
78H + 1536ck
Page 17
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CXD2497R
Control data: D36 to D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
Control data: D38 to D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD2497R and
control is applied immediately at the rising edge of SEN.
D37
0
0
1
1
D36
0
1
0
1
Degree of adjustment (°)
0
90
180
270
D39
X
0
1
D38
0
1
1
Symbol
CAM
SLP
STB
Operating mode
Normal operating mode
Sleep mode
Standby mode
See the Pin Status Table for the pin status in each mode.
Page 18
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CXD2497R
The frame shift data is expressed as shown in the table below using D16 to D23 CDAT.
MSB LSB
D23 D22 D21 D20 D19 D18 D17 D16
0 1 1 0
↓
6
1 0 0 1
↓
9
→ CDAT is expressed as 69h .
Its definition area is specified as follows.
AF1 mode: 00h ≤ CDAT ≤ FFh (11 to 23H)
AF2 mode: 00h ≤ CDAT ≤ FFh (14 to 27H)
Control data: [AF drive]
The CXD2497R controls the drive of the vertical cut-out area of line in AF1/AF2 mode by using control data
D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and this
mode cannot support operation such as electrical image stabilization.
AF drive bits are loaded to the CXD2497R and reflected at the falling edge of VD. As shown in the figure
below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then
normal transfer is performed equivalent to draft mode from the frame shift of the stage specified by the serial
interface data to the timing of the falling edge of the next VD.
Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for
its application.
The number of high-speed sweeps are different according to the selected mode. It is specified as follows.
AF1 mode: 138 stages (0 to 7H)
AF2 mode: 208 stages (0 to 11H)
VD
Frame shiftNormal transferHigh-speed sweep
V1A
Vck
MODE
CDAT
00h
40
FFh
0
00h
Page 19
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CXD2497R
Control data/shutter data: [Electronic shutter]
The CXD2497R realizes various electronic shutter functions by using control data D13 to D14 SMD and
shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 to D14 SMD.
D14
0
0
1
1
D13
0
1
0
1
Description of operation
Electronic shutter stopped mode
High-speed/low-speed shutter mode
HTSG control mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as dummy on this IC.
→ SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode]
During this mode, the shutter data items have the following meanings.
The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying
high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when
SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). However, in the frame
mode A field, it matches (number of SUB pulses + 1). This is a specification for flickerless when the same mode
is repeated. But this change may not occur because of flickerless by the conditions during low-speed shutter.
Note) The bit data definition area is assured in terms of the CXD2497R functions, and does not assure the
CCD characteristics.
Symbol
SVD
SHD
SPL
Data
D10 to D19
D20 to D31
D32 to D41
Description
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
MSB LSB
D29 D28D31 D30 D27 D26 D25 D24 D23 D22 D21 D20
1 1 0 0
↓
C
X 0 0 1
↓
1
0 0 1 1
↓
3
Page 20
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CXD2497R
VD
SHD
01
V1A
SUB
WEN
SMD
000h
002h
SVD
050h
10Fh
SHD
01
SVD
VD
SPL
SHD
01
V1A
SUB
WEN
SMD
000h
001h
SPL
000h
002h
SVD
0A3h
10Fh
SHD
10
SVD
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice versa.
Page 21
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CXD2497R
VD
V1A
SUB
WEN
01
11
Exposure time
01
SMD
Vck
[HTSG control mode]
During this mode, all shutter data items are invalid.
The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical period to the vertical period during which these readout
pulses are stopped as shown in the figure.
Page 22
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CXD2497R
Chart-1 Vertical Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
• ICX252/ICX262
VD
SUB
OBCLP
CLPDM
V1A
C
High-speed sweep blockHigh-speed sweep blockC
V1B
V2
V3A
V3B
V4
1547
1549
1542
1544
1546
1548
1550
1539
1541
1543
1545
3
1
5 7
2 4 6 8 2
6
4
8 10 121 3 5 7 9 11 13 15
PBLK
ID
WEN
A Field B Field
HD
918 1
29 34
1 28 34918810 810
A B
∗
The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
VD of this chart is NTSC equivalent pattern (918H + 1716ck units). For PAL equivalent pattern, it is 945H units, but 1208ck period as for 944H and 945H.
Page 23
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CXD2497R
Chart-2 Vertical Direction Timing Chart
MODE
Draft mode
Applicable CCD image sensor
• ICX252/ICX262
VD
HD
SUB
V1A
V2
V3A
V3B
V4
OBCLP
CLPDM
ID
PBLK
V1B
CCD OUT
15103
6
22 27 34
1381
4
20
546539534527
544537532525 549
25 32
10
3
6
15 22 27 34
8
1
4
13 20 25 32
546539534527
544537532525 549
WEN
2
1
262261
2
1262261
D D
∗
The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
VD of this chart is NTSC equivalent pattern (262H + 1144ck units). For PAL equivalent pattern, it is 314H + 1568ck units.
Page 24
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CXD2497R
Chart-3 Vertical Direction Timing Chart
MODE
AF1 mode
Applicable CCD image sensor
• ICX252/ICX262
VD
CCD OUT
6
4
6
4
WEN
HD
ID
OBCLP
CLPDM
PBLK
V1A
V1B
V2
V3B
V4
SUB
V3A
10 251
8
131
10 251
8131
Frame shift block
F D G Frame shift block
F
DG
High-speed sweep blockHigh-speed sweep block
∗
The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
138 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block.
∗
VD of this chart is NTSC equivalent pattern (131H + 572ck units). For PAL equivalent pattern, it is 157H + 784ck units.
Page 25
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CXD2497R
Chart-4 Vertical Direction Timing Chart
MODE
AF2 mode
Applicable CCD image sensor
• ICX252/ICX262
VD
CCD OUT
6
4
6
4
WEN
HD
ID
OBCLP
CLPDM
PBLK
V1A
V1B
V2
V3B
V4
SUB
V3A
F High-speed sweep block Frame shift blockD G F High-speed sweep block Frame shift blockD
G
14 291
12
65
14 291
1265
∗
The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
208 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block.
∗
VD of this chart is NTSC equivalent pattern (65H + 1430ck units). For PAL equivalent pattern, it is 78H + 1536ck units.
Page 26
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CXD2497R
Chart-5 Horizontal Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
• ICX252/ICX262
148
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(2288)
0 50
52
100 150
110
70
99
47
10
174
90
52
70
200 250
ID
WEN
198
172
198
157
128
110
110
138
52
∗
The HD of this chart indicates the actual CXD2497R load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
ID and WEN are output at the timing shown above at the position shown in Chart-1.
Page 27
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CXD2497R
Chart-6 Horizontal Direction Timing Chart
MODE
Draft/AF1/AF2 mode
Applicable CCD image sensor
• ICX252/ICX262
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(2288)
0 50
52
100 150
70 10693
66
47
10
174
52
200 250
ID
WEN
198
172
198
84 120
75
110
110
140
52 88
79 102 151
111 147
97 156
129
115
61
71
14257
138
124
133
∗
The HD of this chart indicates the actual CXD2497R load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
ID and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
Page 28
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CXD2497R
Chart-7 Horizontal Direction Timing Chart
(High-speed sweep: C)
MODE
Frame mode
Applicable CCD image sensor
• ICX252/ICX262
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(2288)
0 50
52
100 150
52
139
110
197
71
70
200 250
ID
WEN
172
100 129
138
52 81
100
129
110 168
187 274
158
168
226
158
139
#4#3#2
#1
81 255
274245216
187
71
216 245
197
255
226
∗
The HD of this chart indicates the actual CXD2497R load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 26H of 768ck (#1038).
Page 29
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CXD2497R
Chart-8 Horizontal Direction Timing Chart
(High-speed sweep: F)
(Frame shift: G)
MODE
AF1/AF2 mode
Applicable CCD image sensor
• ICX252/ICX262
HD
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(2288)
0 50
52
100 150
71
52
109
90
147
64
47
10
52
200 250
ID
WEN
172
83
121
140
71
105
110
140
52 90 128
83
102
140
159 197
254
109 147 166
102
159 178 216
223 261 280
273
128 204 242
121 235 273
261
216
223
178
185
166
64
185 204 242
197
#2#1
235 254
219
71
∗
The HD of this chart indicates the actual CXD2497R load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
WEN are output at the timing shown above at the position shown in Chart-3 and 4.
∗
High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 6H of 2056ck (#138) in AF1 mode and 10H of 884ck (#208) in AF2 mode.∗Frame shift of V1A/B, V2, V3A/B and V4 receives the output control by the serial interface data and it can specify up to #255 for both of AF1/AF2 mode.
∗
ID is output at the timing shown with dotted line during frame shift.
Page 30
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CXD2497R
Chart-9 Horizontal Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
• ICX252/ICX262
HD
[A Field]
[B Field]
[A]
[B]
V3B
V4
V3B
V4
V1A
V1B
V2
V3A
V1A
V1B
V2
V3A
(2288)
0
52
70
110
90
128
99
148
157
181
211
241
(2288)
0
52
70
128
90
148
99
110
157
1100
1130
1160
1190
1280
1310
1250
Logic alignment portion
∗
The HD of this chart indicates the actual CXD2497R load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing.
Page 31
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CXD2497R
Chart-10 Horizontal Direction Timing Chart
MODE
Draft /AF1/AF2 mode
Applicable CCD image sensor
• ICX252/ICX262
52
57
61
66
70
75
79
84
88
93
97
102
106
111
115
120
124
129
133
138
142
147
151
156
52
57
61
66
70
75
79
84
88
93
97
102
106
111
115
120
124
129
133
138
142
147
151
156
HD
[D]
V3B
V4
V1A
V1B
V2
V3A
(2288)
0
(2288)
0
1130
1160
1190
1010
1040
1070
1100
1220
1250
1280
1310
1340
1370
1400
1430
∗
The HD of this chart indicates the actual CXD2497R load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing.
Page 32
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CXD2497R
Chart-11 High-speed Phase Timing Chart
MODE
Applicable CCD image sensor
• ICX252/ICX262
HD
HD'
CKI
CKO
ADCLK
MCKO
H1
H2
RG
XSHP
XSHD
XRS
172
52
1
∗
HD' indicates the HD which is the actual CXD2497R load timing.
∗
The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗
The logical phase of ADCLK can be specified by the serial interface data.
Page 33
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CXD2497R
Chart-12 Vertical Direction Sequence Chart
MODE
Draft → Frame → Draft
Applicable CCD image sensor
• ICX252/ICX262
VD
V1A
V1B
V2
V3A
V3B
V4
SUB
Mechanical
shutter
Exposure
time
CCD OUT
MODE
SMD
SHD
Close Open
A B C
E E
F
0 0 0 0 0 3 3 0 0
01 01 01 01 01 00 00 01 01
050h 050h 050h 050h 050h 000h 000h 050h 050h
A B C D E F
∗
This chart is a drive timing chart example of electronic shutter normal operation.
∗
Data exposed at D includes blooming component. For details, see CCD image sensor specification.
∗
CXD2497R does not generate the pulse to control mechanical shutter operation.
∗
The switching timing of drive mode and electronic shutter data is not the same.
Page 34
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CXD2497R
Application Circuit Block Diagram
26 27 37 48 31 32
34
35
30
25
23
222019181716
MCKO
VD
HD
CKO
10
D0 to 9
ADCLK
OBCLP
CLPDM
PBLK
XRS
XSHD
XSHP
SCK
33
SEN
SSI
TEST2
TEST1
OSCO
CKI
28
OSCI
CCD OUT
V-Dr
VRT
DRVOUT
VRB
6
3
2
5
4
SSGSL
SNCSL
RST
WEN
ID
12
13
9
RG
H2
H1
41
43
39
V2
V1B
V1A
44
46
40
V4
47
SUB
V3B
V3A
CCD
ICX252/ICX262
S/H
CXA2006Q
TG
CXD2497R
A/D
CXD2311AR
Controller
Signal processor Block
Notes for Power-on
Of the three –7.5V, +15.0V and +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies
in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
t1
t2
15.0V
0V
–7.5V
20%
20%
t2 ≥ t1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 35
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CXD2497R
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗ 7.0 ± 0.1
1
12
13
24
25
36
37
48
(0.22)
0.18 – 0.03
+ 0.08
0.2g
LQFP-48P-L01
LQFP048-P-0707
(8.0)
0.5 ± 0.2
0.127 – 0.02
+ 0.05
A
1.5 – 0.1
+ 0.2
0.1
SOLDER/PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
DETAIL A
0.13
M
0.5
S
S
B
DETAIL B:SOLDER
(0.18)
(0.127)
DETAIL B:PALLADIUM
0.127 ± 0.04
0.18 – 0.03
+ 0.08
0.127 – 0.02
+0.05
0.18 ± 0.03
Package Outline Unit: mm
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