PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z90219/213/212/211/218 1
Z8® DIGITAL TELEVISION
CONTROLLERS
FEATURES
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ROM |
RAM* |
I/O |
Voltage |
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Device |
(KB) |
(Bytes) |
Lines |
Range |
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Z90211 |
16 (OTP) |
237 |
20 |
4.5V to 5.5V |
Z90218 |
8 |
237 |
20 |
4.5V to 5.5V |
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Z90212 |
12 |
237 |
20 |
4.5V to 5.5V |
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Z90213 |
16 |
237 |
20 |
4.5V to 5.5V |
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Z90219 |
32 (ext.) |
237 |
N/A |
4.5V to 5.5V |
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Note: OTP and Z9021x products under development
Z8-Based CMOS Microcontroller for Consumer Television, Cable Box, and Satellite Receiver Applications.
■42-Pin SDIP Package
■Z8® Microcontroller Core at 6 MHz
■Mask ROM sizes Available in 8, 12 and 16 Kbytes
■Eleven Pulse Width Modulators
■On-Chip Infrared (IR) Capture Registers
■Four Channel 3-bit Analog-to-Digital Converter
■Twenty General Purpose I/O Pins
■I2C Serial Communication Port)
On Screen Display (OSD) Section
■Supports Displays up to 10 rows by 24 Columns with 256 Characters
■Character Cell Resolution of 14 Pixels by 18 Scan lines
■Variable Inter-row Spacing from 0-15 Horizontal Scan Lines
■Foreground and Background Colors Fully Programmable by Character
GENERAL DESCRIPTION
The Z9021x Digital Television Controller (DTC) family is Zilog’s latest and most powerful Z8-based DTC product offering. These parts feature larger system RAM and ROM options, together with a host of new features including a new color palette system, flexible inter-row spacing, higher character cell resolution, background mesh effect, dedicated I.R. capture registers, on-chip Analog-to-Digital conversion, and a hardware Master mode I2C interface. The familiar Z8 core in combination with these advanced features makes the Z9021x family an ideal choice for low to midrange televisions in both PAL and NTSC markets.
The Z9021x family consists of two basic device types; Z9020x and Z9021x. The only difference between the two types is the presence of a hardware I2C serial communication port and half-tone OSD circuitry on the Z9021x family. Of course I2C communication is supported on the Z9020x family in software with the dedication of any two I/O pins to the task.
The Z9021x family takes full advantage of the Z8’s expanded register file space to offer greater flexibility in On Screen Display creation.
CP96TEL2400 |
P R E L I M I N A R Y |
1 |
Z90219/213/212/211 |
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Z8® Digital Television Controllers |
Zilog |
BLOCK DIAGRAM
XTAL1 |
Oscillator |
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XTAL2 |
WDT |
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/RESET |
RESET |
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Counter |
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Timer |
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Counter |
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Timer |
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ADC0 |
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ADC1 |
3-bit |
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ADC2 |
ADC |
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ADC3 |
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IRIN |
IR |
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Counter |
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P30 |
Port3 |
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P31 |
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P34 |
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P35 |
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PWM11 |
PWM 11 |
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(14-bit) |
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PWM1 |
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PWM2 |
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PWM3 |
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PWM4 |
PWM 1 |
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PWM5 |
to |
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PWM6 |
PWM 10 |
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PWM7 |
(6-bit) |
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PWM8 |
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PWM9 |
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PWM10 |
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P1 |
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P2 |
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P3 |
Output |
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P4 |
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Port |
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P5 |
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P6 |
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P7 |
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8/12/16K Byte
Program ROM
Z8 CPU
Core
Register File
256 Byte
Character RAM 240 by 11-bit & 10 by 8-bit
Character ROM
9K by 7-bit
P20
P21
P22 Port2 
P23 
P24 
P25 
P26 P27
P40
P41
P42 Port4 
P43
P44
P45
P46 P47
SCLK0 I2C 
SDATA0
Interface 
SCLK1
SDATA1
Z9021x ONLY
OSDX1
OSDX2 On Screen 
HSync
Display 
VSync
R
G
B VBlank
HLFTN
Z9021x ONLY
Figure 1. Functional Block Diagram
2 |
P R E L I M I N A R Y |
CP96TEL2400 |
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Z90219/213/212/211 |
Zilog |
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Z8® Digital Television Controllers |
PIN IDENTIFICATION |
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PWM11/P7 |
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1 |
42 |
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P27/SDATA1 |
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PWM6/P6 |
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P26/SCLK1 |
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PWM5/P5 |
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P25/SDATA0 |
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PWM4/P4 |
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P24/SCLK0 |
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PWM3/P3 |
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P23 |
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PWM2/P2 |
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P22 |
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PWM1/P1 |
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IRIN |
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P40 |
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P21 |
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P34/ADC3 |
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VCC |
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P35/ADC2 |
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/RESET |
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P41/ADC1 |
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Z9021x |
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XTAL2 |
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(Top View) |
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P31/ADC0 |
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XTAL1 |
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AGND |
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GND |
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P42 |
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OSDX2 |
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P43 |
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OSDX1 |
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P30 |
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VSYNC |
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P44/PWM7 |
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HSYNC |
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P45/PWM8 |
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VBLANK |
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P46/PWM9 |
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R |
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P47/PWM10 |
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21 |
22 |
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G |
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P20/HLFTN |
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B |
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CP96TEL2400 |
P R E L I M I N A R Y |
3 |
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