Loading...ZILOG Z86C7216FSC, Z86C7216PSC, Z86C7216VSC, Z86C9216VSC, Z86L7208FSC Datasheet
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PRODUCT SPECIFICATION
1
Z86C72/C92/L72/L92 1
IR MICROCONTROLLER
FEATURES
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ROM |
RAM* |
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Part |
(KB) |
(Bytes) |
I/O |
Voltage Range |
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Z86C72 |
16 |
748 |
31 |
4.5V to 5.5V |
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Z86C92 |
0 |
748 |
31 |
4.5V to 5.5V |
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Z86L72 |
16 |
748 |
31 |
2.0V to 3.9V |
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Z86L92 |
0 |
748 |
31 |
2.0V to 3.9V |
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Note: *General-Purpose
■Expanded Register File Control Registers
■Low Power Consumption - 40 mW (typical)
■Three Standby Modes:
–STOP
–HALT
–Low Voltage
■Automatic External ROM Access Beyond 16K (Z86LX2/C72 Version)
–Programmable Input Glitch Filter for Pulse Reception
■Five Priority Interrupts
–Three External
–Two Assigned to Counter/Timers
■Low Voltage Detection and Standby Mode
■Programmable Watch-Dog/Power-On Reset Circuits
■Two Independent Comparators with Programmable Interrupt Polarity
■On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC (mask option), or External Clock Drive
■Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3
–All Eight Port 2 Bits at one time or Not
–Pull-Ups Automatically Disabled Upon Selecting Individual Pins as Outputs
■Special Architecture to Automate Both Generation and Reception of Complex Pulses or Signals:
–One Programmable 8-Bit Counter/Timer with Two Capture Register
–One Programmable 16-Bit Counter/Timer with One Capture Register
■Maskable Mouse/Trackball Interface on P00 Through P03 is available on the L72 version.
■32 kHz Oscillator Mask Option
GENERAL DESCRIPTION
The Z86LX2/CX2 family of IR (Infrared) are ROM/ROM- less-based members of the Z8® MCU single-chip microcontroller family with 768 bytes of internal RAM. The differentiating factor between these devices is the availability of RAM, ROM and package options. The use of external memory enables these Z8 microcontrollers to be used where code flexibility is required. Offering the 5V versions (Z86CXX) and gives optimum performance in both the low and high voltage ranges. Zilog's CMOS microcontrollers
offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up resistors. The Z86LX2/CX2 product line offers easy hardware/software system expansion with cost-effective and low power consumption.
The Z86LX2/CX2 architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow
DS97LVO0900 |
P R E L I M I N A R Y |
6-1 |
Z86C72/C92/L72/L92 |
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IR Microcontroller |
Zilog |
GENERAL DESCRIPTION (Continued)
access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z86C72/C92/L72/L92 offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery operated hand-held applications.
Many applications demand powerful I/O capabilities. The Z86LX2/CX2 family fulfills this with three package options in which the L72 version provides 31 pins of dedicated input and output. These lines are grouped into four ports. Each port consists of eight lines (Port 3 has seven lines) and is configurable under software control to provide timing, status signals, parallel I/O with or without handshake, and an address/data bus for interfacing external memory.
There are five basic address spaces available to support a wide range of configurations: Program Memory, Register
File, Expanded Register File, Extended Data RAM and External Memory. The register file is composed of 256 bytes of RAM. It includes four I/O port registers, 16 control and status registers and the rest are General-Purpose registers. The Extended Data RAM adds 512 bytes of usable general-purpose registers. The Expanded Register FIle consists of two additional register groups (F and D).
To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Z86LX2/CX2 family offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two on-board comparators to process analog signals with separate reference voltages (Figure 2).
HI16 |
LO16 |
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8 |
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16-Bit |
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Timer 16 |
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T16 |
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8 |
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SCLK |
Clock |
TC16H |
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TC16L |
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Divider |
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And/Or |
Timer 8/16 |
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Logic |
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HI8 |
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LO8 |
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T8 |
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TC8H |
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TC8L |
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Figure 1. Counter/Timer Block Diagram
6-2 |
P R E L I M I N A R Y |
DS97LVO0900 |
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Z86C72/C92/L72/L92 |
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IR Microcontroller |
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P00 |
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Register File |
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P01 |
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P31 |
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P02 |
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P03 |
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P33 |
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Port 0 |
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Port 3 |
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P04 |
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P34 |
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Register Bus |
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P35 |
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P05 |
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Internal |
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P06 |
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Address Bus |
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P07 |
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ROM |
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P10 |
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16K/0K x 8 |
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Z8 Core |
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P11 |
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Internal Data Bus |
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P12 |
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P13 |
Port 1 |
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P14 |
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Expanded |
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Timing |
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P15 |
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Expanded |
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/AS |
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Register Bus |
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P16 |
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Register |
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Instruction |
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/DS |
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P17 |
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File |
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Control |
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R/W |
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512 x 8-Bit |
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P20 |
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P22 |
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VDD |
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P23 |
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P24 |
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P25 |
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P26 |
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Figure 2. Functional Block Diagram
Note: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection |
Circuit |
Device |
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Power |
VCC |
VDD |
Ground |
GND |
VSS |
DS97LVO0900 |
P R E L I M I N A R Y |
6-3 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
PIN DESCRIPTION
R//W |
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1 |
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40 |
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/DS |
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P25 |
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P14 |
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||
P15 |
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P12 |
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Z86C72/C92 |
|
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||
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||||
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||||
P07 |
|
|
Z86L72/L92 |
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VSS |
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|||||
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|||||
VDD |
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DIP |
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P02 |
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|||||
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P16 |
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P11 |
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P17 |
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P10 |
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XTAL2 |
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P01 |
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XTAL1 |
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P00 |
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P31 |
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Pref1 |
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||
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P32 |
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P36 |
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P33 |
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P37 |
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P34 |
|
20 |
|
21 |
|
P35 |
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||||
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||||
/AS |
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/RESET |
||
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||||||
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||||||
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|
|
Figure 3. 40-Pin DIP Pin Assignments
|
P20 |
P03 |
P13 |
P12 |
VSS VSS P02 |
P11 |
P10 |
P01 |
P00 |
|
|
6 |
|
|
|
1 |
|
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|
40 |
|
P21 |
7 |
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39 |
Pref1 |
P22 |
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P36 |
P23 |
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P37 |
P24 |
|
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|
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|
P35 |
/DS |
|
|
|
Z86C72/C92 |
|
|
|
/RESET |
||
R//RL |
|
|
|
Z86L72/L92 |
|
|
|
VSS |
||
R//W |
|
|
|
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|
|
/AS |
|||
|
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|
PLCC |
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||
P25 |
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P34 |
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||
P26 |
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P33 |
P27 |
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P32 |
P04 |
17 |
|
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|
29 |
P31 |
|
18 |
|
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|
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|
28 |
|
|
P05 |
P06 |
P14 |
P15 |
P07 VDD VDD |
P16 |
P17 |
XTAL2 |
XTAL1 |
|
Figure 4. 44-Pin PLCC Pin Assignments
6-4 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
|
P20 |
P03 |
P13 |
P12 |
VSS VSS P02 |
P11 |
P10 |
P01 |
P00 |
|
|
33 |
|
|
|
|
|
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|
23 |
|
P21 |
34 |
|
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|
|
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|
22 |
Pref1 |
P22 |
|
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|
P36 |
P23 |
|
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|
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|
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|
P37 |
P24 |
|
|
|
Z86C72/C92 |
|
|
|
P35 |
||
/DS |
|
|
|
|
|
|
/RESET |
|||
R//RL |
|
|
|
Z86L72/L92 |
|
|
|
VSS |
||
R//W |
|
|
|
|
QFP |
|
|
|
|
/AS |
P25 |
|
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|
|
|
|
|
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|
P34 |
P26 |
|
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P33 |
P27 |
|
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|
P32 |
P04 |
44 |
|
|
|
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|
12 |
P31 |
|
1 |
|
|
|
|
|
|
|
11 |
|
|
P05 |
P06 |
P14 |
P15 |
P07 VDD VDD |
P16 |
P17 |
XTAL2 |
XTAL1 |
|
Figure 5. 44-Pin QFP Pin Assignments
DS97LVO0900 |
P R E L I M I N A R Y |
6-5 |
Z86C72/C92/L72/L92 |
|
|
|
|
|
|
IR Microcontroller |
|
|
|
Zilog |
||
|
|
|
|
|
||
PIN DESCRIPTION (Continued) |
|
|
|
|
||
|
|
|
Table 1. Pin Identification |
|
|
|
|
|
|
|
|
|
|
40-Pin |
44-Pin |
44-Pin |
|
|
|
|
DIP # |
PLCC |
QFP# |
Symbol |
Direction |
Description |
|
|
|
|
|
|
|
|
26 |
40 |
23 |
P00 |
Input/Output |
Port 0 is Nibble Programmable |
|
27 |
41 |
24 |
P01 |
Input/Output |
Port 0 can be configured as A15-A8 |
|
30 |
44 |
27 |
P02 |
Input/Output |
external program ROM/DATA Address |
|
34 |
5 |
32 |
P03 |
Input/Output |
Bus. |
|
5 |
17 |
44 |
P04 |
Input/Output |
Port 0 can be configured as a |
|
6 |
18 |
1 |
P05 |
Input/Output |
mouse/trackball input. |
|
7 |
19 |
2 |
P06 |
Input/Output |
|
|
10 |
22 |
5 |
P07 |
Input/Output |
|
|
|
|
|
|
|
|
|
28 |
42 |
25 |
P10 |
Input/Output |
Port 1 is byte programmable |
|
29 |
43 |
26 |
P11 |
Input/Output |
Port 1 can be configured as multiplexed |
|
32 |
3 |
30 |
P12 |
Input/Output |
A7-A0/D7-D0 external program ROM |
|
33 |
4 |
31 |
P13 |
Input/Output |
Address/Data Bus. |
|
8 |
20 |
3 |
P14 |
Input/Output |
|
|
9 |
21 |
4 |
P15 |
Input/Output |
|
|
12 |
25 |
8 |
P16 |
Input/Output |
|
|
13 |
26 |
9 |
P17 |
Input/Output |
|
|
|
|
|
|
|
|
|
35 |
6 |
33 |
P20 |
Input/Output |
Port 2 pins are individually configurable |
|
36 |
7 |
34 |
P21 |
Input/Output |
as input or output. |
|
37 |
8 |
35 |
P22 |
Input/Output |
|
|
38 |
9 |
36 |
P23 |
Input/Output |
|
|
39 |
10 |
37 |
P24 |
Input/Output |
|
|
2 |
14 |
41 |
P25 |
Input/Output |
|
|
3 |
15 |
42 |
P26 |
Input/Output |
|
|
4 |
16 |
43 |
P27 |
Input/Output |
|
|
|
|
|
|
|
|
|
16 |
29 |
12 |
P31 |
Input |
IRQ2/Modulator Input |
|
17 |
30 |
13 |
P32 |
Input |
IRQ0 |
|
18 |
31 |
14 |
P33 |
Input |
IRQ1 |
|
19 |
32 |
15 |
P34 |
Output |
T8 output |
|
22 |
36 |
19 |
P35 |
Output |
T16 output |
|
24 |
38 |
21 |
P36 |
Output |
T8/T16 output |
|
23 |
37 |
20 |
P37 |
Output |
|
|
|
|
|
|
|
|
|
20 |
33 |
16 |
/AS |
Output |
Address Strobe |
|
40 |
11 |
38 |
/DS |
Output |
Data Strobe |
|
1 |
13 |
40 |
R//W |
Output |
Read/Write |
|
21 |
35 |
18 |
/RESET |
Input |
Reset |
|
15 |
28 |
11 |
XTAL1 |
Input |
Crystal, Oscillator Clock |
|
14 |
27 |
10 |
XTAL2 |
Output |
Crystal, Oscillator Clock |
|
11 |
23,24 |
6,7 |
VDD |
|
Power Supply |
|
31 |
1,2,34 |
17,28,29 |
VSS |
Input |
Ground |
|
25 |
39 |
22 |
Pref1 |
Comparator 1 Reference |
||
|
12 |
39 |
Input |
ROM/ROMless |
||
|
R//RL |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
6-6 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
ABSOLUTE MAXIMUM RATINGS
Symbol |
Description |
Min |
Max |
Units |
|
|
|
|
|
VCC |
Supply Voltage (*) |
-0.3 |
+7.0 |
V |
TSTG |
Storage Temp. |
-65° |
+150° |
C |
TA |
Oper. Ambient |
|
† |
C |
|
Temp. |
|
|
|
|
|
|
|
|
Notes:
* Voltage on all pins with respect to GND
† See Ordering Information
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 6). From Output Under Test
I |
|
|
|
|
|
|
|
150 pF |
|
|
|
|
|
|
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||
|
||||||||
|
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|
|
|
|
|
Figure 6. Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter |
Max |
|
|
Input capacitance |
12 pF |
|
|
Output capacitance |
12 pF |
|
|
I/O capacitance |
12 pF |
|
|
DS97LVO0900 |
P R E L I M I N A R Y |
6-7 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
DC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary
|
|
|
TA = 0°C to +70°C |
Typ @ |
|
|
|
|
Sym |
Parameter |
VCC |
Min |
Max |
25°C |
Units |
Conditions |
Notes |
|
Max Input Voltage 2.0V |
|
7 |
|
V |
IIN <250 A |
|
|
|
|
3.9V |
|
7 |
|
V |
IIN <250 A |
|
VCH |
Clock Input |
2.0V |
0.8 VCC |
VCC + 0.3 |
|
V |
Driven by External |
|
|
High Voltage |
|
|
|
|
|
Clock Generator |
|
|
|
3.9V |
0.8 VCC |
VCC + 0.3 |
|
V |
Driven by External |
|
|
|
|
|
|
|
|
Clock Generator |
|
VCL |
Clock Input |
2.0V |
VSS – 0.3 |
0.2 VCC |
|
V |
Driven by External |
|
|
Low Voltage |
|
|
|
|
|
Clock Generator |
|
|
|
3.9V |
VSS– 0.3 |
0.2 VCC |
|
V |
Driven by External |
|
|
|
|
|
|
|
|
Clock Generator |
|
VIH |
Input High Voltage2.0V |
0.7 VCC |
VCC + 0.3 |
0.5VCC |
V |
|
|
|
|
|
3.9V |
0.7 VCC |
VCC + 0.3 |
0.5VCC |
V |
|
|
VIL |
Input Low Voltage 2.0V |
VSS – 0.3 |
0.2 VCC |
0.5VCC |
V |
|
|
|
|
|
3.9V |
VSS – 0.3 |
0.2 VCC |
0.5VCC |
V |
|
|
VOH1 |
Output High |
2.0V |
VCC – 0.4 |
|
1.7 |
V |
IOH = –0.5 mA |
|
|
Voltage |
3.9V |
VCC – 0.4 |
|
3.7 |
V |
IOH = –0.5 mA |
|
VOH2 |
Output High |
2.0V |
VCC - 0.8 |
|
|
V IOH = –7 mA |
|
|
|
Voltage (P36, |
3.9V |
VCC - 0.8 |
|
|
V |
IOH = –7 mA |
|
|
P37,P00, P01) |
|
|
|
|
|
|
|
6-8 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
|
|
|
|
|
|
Z86C72/C92/L72/L92 |
||
Zilog |
|
|
|
|
|
|
IR Microcontroller |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TA = 0°C to +70°C |
Typ @ |
|
|
|
|
|
Sym |
Parameter |
VCC |
Min |
Max |
25°C |
Units |
Conditions |
Notes |
|
VOL1 |
Output Low |
2.0V |
|
0.4 |
0.1 |
V |
IOL = 1.0 mA |
|
|
|
Voltage |
3.9V |
|
0.4 |
0.2 |
V |
IOL = 4.0 mA |
|
|
VOL2* |
Output Low |
2.0V |
|
0.8 |
0.5 |
V |
IOL = 5.0 mA |
|
|
|
Voltage |
|
|
|
|
|
|
|
|
|
|
3.9V |
|
0.8 |
0.3 |
V |
IOL = 7.0 mA |
|
|
|
|
|
|
|
|
|
|
|
|
VOL2 |
Output Low |
2.0V |
|
0.8 |
0.3 |
V |
IOL = 10 mA |
|
|
|
Voltage(P36, |
3.9V |
|
0.8 |
0.2 |
V |
IOL = 10 mA |
|
|
|
P37,P00,P01) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VRH |
Reset Input |
2.0V |
0.8 VCC |
VCC |
1.5 |
V |
|
|
|
|
High Voltage |
3.9V |
0.8 VCC |
VCC |
2.0 |
V |
|
|
|
VRl |
Reset Input |
2.0V |
VSS – 0.3 |
0.2 VCC |
0.5 |
V |
|
|
|
|
Low Voltage |
3.9V |
VSS – 0.3 |
0.2 VCC |
0.9 |
V |
|
|
|
VOFFSET |
Comparator Input 2.0V |
|
25 |
10 |
mV |
|
|
|
|
|
Offset Voltage |
3.9V |
|
25 |
10 |
mV |
|
|
|
|
|
|
|
|
|
|
|
|
|
IIL |
Input Leakage |
2.0V |
-1 |
1 |
< 1 |
A |
VIN = OV, VCC |
|
|
|
|
3.9V |
-1 |
1 |
< 1 |
A |
VIN = OV, VCC |
|
|
IOL |
Output Leakage |
2.0V |
–1 |
1 |
< 1 |
A |
VIN = OV, VCC |
|
|
|
|
3.9V |
–1 |
1 |
< 1 |
A |
VIN = OV, VCC |
|
|
IIR |
Reset Input Pull- |
2.0V |
|
–230 |
-50 |
A |
VIN = OV |
|
|
|
Up Current |
3.9V |
|
–400 |
–90 |
A |
VIN = OV |
|
|
ICC |
Supply Current |
2.0V |
|
10 |
4 |
mA |
@ 8.0 MHz |
1,2 |
|
|
|
3.9V |
|
15 |
10 |
mA |
@ 8.0 MHz |
1,2 |
|
|
|
2.0V |
|
250 |
100 |
A |
@ 32 kHz |
1,2,8 |
|
|
|
3.9V |
|
850 |
500 |
A |
@ 32 kHz |
|
|
|
|
|
|
|
|
|
|
|
|
DS97LVO0900 |
P R E L I M I N A R Y |
6-9 |
Z86C72/C92/L72/L92 |
|
|
|
|
|
|
|
|
IR Microcontroller |
|
|
|
|
|
|
Zilog |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TA = 0°C to +70°C |
Typ @ |
|
|
|
|
Sym |
Parameter |
VCC |
Min |
Max |
25°C |
Units |
Conditions |
Notes |
ICC1 |
Standby Current |
2.0V |
|
3 |
1 |
mA |
HALT Mode |
1,2 |
|
(WDT Off) |
|
|
|
|
|
VIN = OV, VCC @ |
|
|
|
3.9V |
|
5 |
4 |
mA |
8.0 MHz |
1,2 |
|
|
|
HALT Mode |
|||||
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
2.0V |
|
2 |
0.8 |
mA |
@ 8.0 MHz |
1,2 |
|
|
|
Clock Divide-by- |
|||||
|
|
3.9V |
|
4 |
2.5 |
mA |
16 @ 8.0 MHz |
1,2 |
|
|
|
Clock Divide-by- |
|||||
|
|
|
|
|
|
|
16 @ 8.0 MHz |
|
|
|
|
|
|
|
|
|
|
ICC2 |
Standby Current |
2.0V |
|
8 |
2 |
A |
STOP Mode |
3,5 |
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
|
|
|
|
|
WDT is not |
|
|
|
3.9V |
|
10 |
3 |
A |
Running |
3,5 |
|
|
|
STOP Mode |
|||||
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
|
|
|
|
|
WDT is not |
|
|
|
2.0V |
|
500 |
310 |
A |
Running |
|
|
|
|
STOP Mode |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
|
|
|
|
|
WDT is not |
|
|
|
3.9V |
|
800 |
600 |
A |
Running |
|
|
|
|
STOP Mode |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
|
|
|
|
|
WDT is not |
|
|
|
|
|
|
|
|
Running |
|
|
|
|
|
|
|
|
|
|
TPOR |
Power-On Reset |
2.0V |
12 |
75 |
18 |
ms |
|
|
|
|
3.9V |
5 |
20 |
7 |
ms |
|
|
|
|
|
|
|
|
|
|
|
VRAM |
Static RAM Data |
Vram |
0.8 |
|
0.5 |
V |
|
6 |
|
Retention Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VLV |
VCC Low Voltage |
|
|
2.15 |
1.7 |
V |
8 MHz max |
4 |
(VBO) |
Protection |
|
|
|
|
|
Ext. CLK Freq. |
|
Notes: |
ICC1 |
Typ |
Max |
Unit |
Frequency |
|
|
|
|
Crystal/Resonator |
3.0 mA |
5 |
mA |
8.0 MHz |
|
|
|
|
External Clock Drive |
0.3 mA |
5 |
mA |
8.0 MHz |
|
|
|
1.All outputs unloaded, inputs at rail
2.CL1 = CL2 = 100 pF
3.Same as note [4] except inputs at VCC
4.The VLV increases as the temperature decreases
5.Oscillator stopped
6.Oscillator stops when VCC falls below VLV limit
7.32 kHz clock driver input
*All Outputs excluding P00, P01, P36, and P37
6-10 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
DC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS)
Preliminary
|
|
|
TA = 0°C to +70°C |
Typ @ |
|
|
|
|
Sym |
Parameter |
VCC |
Min |
Max |
25°C |
Units |
Conditions |
Notes |
|
Max Input |
4.5V |
|
7 |
|
V |
IIN 250 A |
|
|
Voltage |
5.5V |
|
7 |
|
V |
IIN 250 A |
|
VCH |
Clock Input |
4.5V |
0.9 VCC |
VCC + 0.3 |
|
V |
Driven by |
|
|
High Voltage |
5.5V |
0.9 VCC |
VCC + 0.3 |
|
|
External Clock |
|
|
|
|
|
|
|
|
Generator |
|
VCL |
Clock Input |
4.5V |
VSS – 0.3 |
0.2 VCC |
|
V |
Driven by |
|
|
Low Voltage |
5.5V |
VSS –0.3 |
0.2 VCC |
|
|
External Clock |
|
|
|
|
|
|
|
|
Generator |
|
VIH |
Input High |
4.5V |
0.7 VCC |
VCC + 0.3 |
0.5Vcc |
V |
Driven by |
|
|
Voltage |
5.5V |
0.7 VCC |
VCC + 0.3 |
0.5Vcc |
|
External Clock |
|
|
|
|
|
|
|
|
Generator |
|
VIL |
Input Low |
4.5V |
VSS – 0.3 |
|
0.5Vcc |
V |
|
|
|
Voltage |
5.5V |
VSS – 0.3 |
|
0.5Vcc |
|
|
|
VOH1 |
Output High |
4.5V |
VCC – 0.4 |
|
4.4 |
V |
IOH = –0.5 mA |
|
|
Voltage |
5.5V |
VCC – 0.4 |
|
5.4 |
|
IOH = –0.5 mA |
|
VOH2 |
Output High |
4.5V |
VCC – 0.8 |
|
|
V |
IOH = –7 mA |
|
|
Voltage |
5.5V |
VCC – 0.8 |
|
|
V |
IOH = –7 mA |
|
|
(P36, P37) |
|
|
|
|
|
|
|
VOL1 |
Output Low |
4.5V |
|
0.4 |
0.1 |
V |
IOL = 1.0 mA |
|
|
Voltage |
5.5V |
|
0.4 |
0.2 |
V |
IOL = 4.0 mA |
|
VOL2* |
Output Low |
4.5V |
|
0.8 |
0.3 |
V |
IOL = 5.0 mA |
|
|
Voltage |
3.9 V |
|
0.8 |
0.4 |
V |
IOL = 7.0 mA |
|
VOL2 |
Output Low |
4.5V |
|
0.8 |
0.3 |
V |
IOL = 10 mA |
|
|
Voltage |
5.5V |
|
0.8 |
0.2 |
|
|
|
|
(P00, P01, |
|
|
|
|
|
|
|
|
P36,P37) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VRH |
Reset Input |
4.5V |
0.8 VCC |
VCC |
2.5 |
V |
|
|
|
High Voltage |
5.5V |
0.8 VCC |
VCC |
3.0 |
V |
|
|
VRl |
Reset Input |
4.5V |
VSS – 0.3 |
0.2 VCC |
0.5 |
|
|
|
|
Low Voltage |
5.5V |
VSS – 0.3 |
0.2 VCC |
0.9 |
|
|
|
VOFFSET |
Comparator |
4.5V |
|
25 |
10 |
mV |
|
|
|
Input |
5.5V |
|
25 |
10 |
mV |
|
|
|
Offset Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IIL |
Input Leakage |
4.5V |
-1 |
1 |
<1 |
A |
VIN = OV, VCC |
|
|
|
5.5V |
-1 |
1 |
<1 |
A |
VIN = OV, VCC |
|
IOL |
Output Leakage |
4.5V |
-1 |
1 |
<1 |
A |
VIN = OV, VCC |
|
|
|
5.5V |
-1 |
1 |
<1 |
A |
VIN = OV, VCC |
|
IIR |
Reset Input |
4.5V |
|
-500 |
|
A |
|
|
|
Current |
5.5V |
|
-800 |
|
A |
|
|
|
|
|
|
|
|
|
|
|
ICC |
Supply Current |
4.5V |
|
20 |
|
mA |
@8.0 MHz |
1,2 |
|
|
5.5V |
|
30 |
|
mA |
@8.0 MHz |
1.2 |
|
|
|
|
|
|
|
|
|
|
WDT Off |
4.5V |
|
1000 |
|
A |
@ 32 kHz |
1,2,8 |
|
|
5.5V |
|
1250 |
|
A |
@ 32 kHz |
1,2,8 |
|
|
|
|
|
|
|
|
|
DS97LVO0900 |
P R E L I M I N A R Y |
6-11 |
Z86C72/C92/L72/L92 |
|
|
|
|
|
|
|
|
IR Microcontroller |
|
|
|
|
|
|
Zilog |
|
|
|
|
||||||
DC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS) (Continued) |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
TA = 0°C to +70°C |
Typ @ |
|
|
|
|
Sym |
Parameter |
VCC |
Min |
Max |
25°C |
Units |
Conditions |
Notes |
ICC1 |
Standby Current |
4.5V |
|
6 |
2 |
mA |
HALT Mode |
1,2 |
|
(WDT Off) |
|
|
|
|
|
VIN = OV, VCC @ |
|
|
|
5.5V |
|
8 |
5 |
mA |
8.0 MHz |
1,2 |
|
|
|
HALT Mode |
|||||
|
|
4.5V |
|
5 |
1.0 |
mA |
VIN = OV, VCC |
1,2 |
|
|
5.5V |
|
7 |
3.0 |
mA |
@ 8.0 MHz |
1,2 |
|
|
|
Clock Divide-by- |
|||||
|
|
|
|
|
|
|
16 @ 8.0 MHz |
|
|
|
|
|
|
|
|
Clock Divide-by- |
|
|
|
|
|
|
|
|
16 @ 8.0 MHz |
|
|
|
|
|
|
|
|
|
|
ICC2 |
Standby Current |
4.5V |
|
8 |
2 |
A |
STOP Mode |
3,5 |
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
|
|
|
|
|
WDT is not |
|
|
|
5.5V |
|
10 |
3 |
A |
Running |
3,5 |
|
|
|
STOP Mode |
|||||
|
|
4.5V |
|
500 |
310 |
A |
VIN = OV, VCC |
3,5 |
|
|
5.5V |
|
800 |
600 |
A |
WDT is not |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Running |
|
|
|
|
|
|
|
|
STOP Mode |
|
|
|
|
|
|
|
|
VIN = OV, VCC |
|
|
|
|
|
|
|
|
WDT is Running |
|
|
|
|
|
|
|
|
|
|
TPOR |
Power-On Reset |
4.5V |
5.0 |
75 |
8.0 |
ms |
|
|
|
|
5.5V |
4.0 |
20 |
6.0 |
ms |
|
|
|
|
|
|
|
|
|
|
|
VRAM |
Static RAM Data |
Vram |
0.8 |
|
0.5 |
V |
|
6 |
|
Retention Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VLV |
VCC Low Voltage |
|
|
2.15 |
1.7 |
V |
8 MHz max |
4 |
(VBO) |
Protection |
|
|
|
|
|
Ext. CLK Freq. |
|
Notes: |
ICC1 |
Typ |
Max |
Unit |
Frequency |
|
|
|
|
Crystal/Resonator |
3.5 mA |
5 |
mA |
8.0 MHz |
|
|
|
|
External Clock Drive |
0.8 mA |
5 |
mA |
8.0 MHz |
|
|
|
1.All outputs unloaded, inputs at rail
2.CL1 = CL2 = 100 pF
3.Same as note [4] except inputs at VCC
4.The VLV increases as the temperature decreases
5.Oscillator stopped
6.Oscillator stops when VCC falls below VLV limit
7.32 kHz clock driver input
*All Outputs excluding P00, P01, P36, and P37
6-12 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
R//W |
|
|
|
|
|
|
|
|
13 |
12 |
|
|
|
19 |
|
|
|
|
|
Port 0, /DM |
|
|
|
|
|
16 |
|
|
20 |
18 |
3 |
|
|
|
Port 1 |
A7 - A0 |
|
D7 - D0 |
IN |
|
|
|||
1 |
2 |
|
|
9 |
/AS |
|
|
|
|
|
|
8 |
|
11 |
4 |
|
|
|
|
|
5 |
6 |
|
|
/DS |
|
|
|
|
(Read) |
17 |
|
|
|
|
|
|
|
10 |
Port 1 |
A7 - A0 |
D7 - D0 |
OUT |
|
|
|
|||
|
14 |
|
|
15 |
|
|
|
7 |
|
/DS |
|
|
|
|
(Write) |
|
|
|
|
Figure 7. External I/O or Memory Read/Write Timing
DS97LVO0900 |
P R E L I M I N A R Y |
6-13 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary
External I/O or Memory Read and Write Timing Table
|
|
|
|
TA = 0°C to +70°C |
|
|
|
|
|
|
|
8.0MHz |
|
|
|
No |
Symbol |
Parameter |
VCC |
Min |
Max |
Units |
Notes |
1 |
TdA(AS) |
Address Valid to |
2.0V |
55 |
|
ns |
2 |
|
|
/AS Rising Delay |
3.9V |
55 |
|
ns |
|
|
|
|
|
|
|
|
|
2 |
TdAS(A) |
/AS Rising to Address |
2.0V |
70 |
|
ns |
2 |
|
|
Float Delay |
3.9V |
70 |
|
ns |
2 |
|
|
|
|
|
|
|
|
3 |
TdAS(DR) |
/AS Rising to Read |
2.0V |
|
400 |
ns |
1,2 |
|
|
Data Required Valid |
3.9V |
|
400 |
ns |
|
|
|
|
|
|
|
|
|
4 |
TwAS |
/AS Low Width |
2.0V |
80 |
|
ns |
2 |
|
|
|
3.9V |
80 |
|
ns |
|
|
|
|
|
|
|
|
|
5 |
Td |
Address Float to |
2.0V |
0 |
|
ns |
|
|
|
/DS Falling |
3.9V |
0 |
|
ns |
|
|
|
|
|
|
|
|
|
6 |
TwDSR |
/DS (Read) Low Width |
2.0V |
300 |
|
ns |
1,2 |
|
|
|
3.9V |
300 |
|
ns |
|
|
|
|
|
|
|
|
|
7 |
TwDSW |
/DS (Write) Low Width |
2.0V |
165 |
|
ns |
1,2 |
|
|
|
3.9V |
165 |
|
ns |
|
|
|
|
|
|
|
|
|
8 |
TdDSR(DR) |
/DS Falling to Read |
2.0V |
|
260 |
ns |
1,2 |
|
|
Data Required Valid |
3.9V |
|
260 |
ns |
|
|
|
|
|
|
|
|
|
9 |
ThDR(DS) |
Read Data to /DS Rising |
2.0V |
0 |
|
ns |
2 |
|
|
Hold Time |
3.9V |
0 |
|
ns |
|
|
|
|
|
|
|
|
|
10 |
TdDS(A) |
/DS Rising to Address |
2.0V |
85 |
|
ns |
2 |
|
|
Active Delay |
3.9V |
95 |
|
ns |
|
|
|
|
|
|
|
|
|
11 |
TdDS(AS) |
/DS Rising to /AS |
2.0V |
60 |
|
ns |
2 |
|
|
Falling Delay |
3.9V |
70 |
|
ns |
|
|
|
|
|
|
|
|
|
12 |
TdR/W(AS) |
R//W Valid to /AS |
2.0V |
70 |
|
ns |
2 |
|
|
Rising Delay |
3.9V |
70 |
|
ns |
|
|
|
|
|
|
|
|
|
13 |
TdDS(R/W) |
/DS Rising to |
2.0V |
70 |
|
ns |
2 |
|
|
R//W Not Valid |
3.9V |
70 |
|
ns |
|
|
|
|
|
|
|
|
|
14 |
TdDW(DSW) |
Write Data Valid to /DS |
2.0V |
80 |
|
ns |
2 |
|
|
Falling (Write) Delay |
3.9V |
80 |
|
ns |
|
|
|
|
|
|
|
|
|
15 |
TdDS(DW) |
/DS Rising to Write |
2.0V |
70 |
|
ns |
2 |
|
|
Data Not Valid Delay |
3.9V |
80 |
|
ns |
|
|
|
|
|
|
|
|
|
16 |
TdA(DR) |
Address Valid to Read |
2.0V |
|
475 |
ns |
1,2 |
|
|
Data Required Valid |
3.9V |
|
475 |
ns |
|
|
|
|
|
|
|
|
|
17 |
TdAS(DS) |
/AS Rising to |
2.0V |
100 |
|
ns |
2 |
|
|
/DS Falling Delay |
3.9V |
100 |
|
ns |
|
|
|
|
|
|
|
|
|
18 |
TdDM(AS) |
/DM Valid to /AS |
2.0V |
55 |
|
ns |
2 |
|
|
Falling Delay |
3.9V |
55 |
|
ns |
|
|
|
|
|
|
|
|
|
19 |
TdDS(DM) |
/DS Rise to |
2.0V |
70 |
|
ns |
|
|
|
/DM Valid Delay |
3.9V |
70 |
|
ns |
|
|
|
|
|
|
|
|
|
20 |
ThDS(A) |
/DS Rise to Address |
2.0V |
70 |
|
ns |
|
|
|
Valid Hold Time |
3.9V |
70 |
|
|
|
|
|
|
|
|
|
|
|
Notes:
1.When using extended memory timing add 2 TpC
2.Timing numbers given are for minimum TpC
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0
6-14 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
AC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS)
Preliminary
External I/O or Memory Read and Write Timing Table
|
|
|
|
TA = 0°C to +70°C |
|
|
|
|
|
|
|
|
16.0 MHz |
|
|
No |
Symbol |
Parameter |
VCC |
Min |
Max |
Units |
Notes |
1 |
TdA(AS) |
Address Valid to /AS |
4.5V |
25 |
|
ns |
2 |
|
|
Rising Delay |
5.5V |
25 |
|
ns |
|
|
|
|
|
|
|
|
|
2 |
TdAS(A) |
/AS Rising to Address |
4.5V |
35 |
|
ns |
2 |
|
|
Float Delay |
5.5V |
35 |
|
ns |
|
|
|
|
|
|
|
|
|
3 |
TdAS(DR) |
/AS Rising to Read |
4.5V |
|
180 |
ns |
1,2 |
|
|
Data Required Valid |
5.5V |
|
180 |
ns |
|
|
|
|
|
|
|
|
|
4 |
TwAS |
/AS Low Width |
4.5V |
40 |
|
ns |
2 |
|
|
|
5.5V |
40 |
|
ns |
|
|
|
|
|
|
|
|
|
5 |
Td |
Address Float to /DS |
4.5V |
0 |
|
ns |
|
|
|
Falling |
5.5V |
0 |
|
ns |
|
|
|
|
|
|
|
|
|
6 |
TwDSR |
/DS (Read) Low Width |
4.5V |
135 |
|
ns |
1,2 |
|
|
|
5.5V |
135 |
|
ns |
|
|
|
|
|
|
|
|
|
7 |
TwDSW |
/DS (Write) Low Width |
4.5V |
80 |
|
ns |
1,2 |
|
|
|
5.5V |
80 |
|
ns |
|
|
|
|
|
|
|
|
|
8 |
TdDSR(DR) |
/DS Falling to Read |
4.5V |
|
75 |
ns |
1,2 |
|
|
Data Required Valid |
5.5V |
|
75 |
ns |
|
|
|
|
|
|
|
|
|
9 |
ThDR(DS) |
Read Data to |
4.5V |
0 |
|
ns |
2 |
|
|
/DS Rising Hold Time |
5.5V |
0 |
|
ns |
|
|
|
|
|
|
|
|
|
10 |
TdDS(A) |
/DS Rising to Address |
4.5V |
50 |
|
ns |
2 |
|
|
Active Delay |
5.5V |
50 |
|
ns |
|
|
|
|
|
|
|
|
|
11 |
TdDS(AS) |
/DS Rising to /AS |
4.5V |
35 |
|
ns |
2 |
|
|
|
5.5V |
35 |
|
ns |
|
|
|
|
|
|
|
|
|
12 |
TdR/W(AS) |
R//W Valid to /AS |
4.5V |
25 |
|
ns |
2 |
|
|
Rising Delay |
5.5V |
25 |
|
ns |
|
|
|
|
|
|
|
|
|
13 |
TdDS(R/W) |
/DS Rising to |
4.5V |
35 |
|
ns |
2 |
|
|
R//W Not Valid |
5.5V |
35 |
|
ns |
|
|
|
|
|
|
|
|
|
14 |
TdDW(DSW) |
Write Data Valid to |
4.5V |
25 |
|
ns |
2 |
|
|
/DS Falling (Write) |
5.5V |
25 |
|
ns |
|
|
|
Delay |
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
TdDS(DW) |
/DS Rising to Write |
4.5V |
35 |
|
ns |
2 |
|
|
Data Not Valid Delay |
5.5V |
35 |
|
ns |
|
|
|
|
|
|
|
|
|
16 |
TdA(DR) |
Address Valid to Read |
4.5V |
|
230 |
ns |
1,2 |
|
|
Data Required Valid |
5.5V |
|
230 |
ns |
|
|
|
|
|
|
|
|
|
17 |
TdAS(DS) |
/AS Rising to /DS |
4.5V |
45 |
|
ns |
2 |
|
|
Falling Delay |
5.5V |
45 |
|
ns |
|
|
|
|
|
|
|
|
|
18 |
TdM(AS) |
/DM Valid to /AS |
4.5V |
30 |
|
ns |
2 |
|
|
Falling Delay |
5.5V |
30 |
|
ns |
|
|
|
|
|
|
|
|
|
19 |
TdDS(DM) |
/DS Rise to /DM Valid |
4.5V |
70 |
|
ns |
|
|
|
Delay |
5.5V |
70 |
|
ns |
|
|
|
|
|
|
|
|
|
20 |
ThDS(A) |
/DS Rise to Address |
4.5V |
70 |
|
ns |
|
|
|
Valid Hold Time |
5.5V |
70 |
|
ns |
|
|
|
|
|
|
|
|
|
Notes:
1.When using extended memory timing add 2 TpC.
2.Timing numbers given are for minimum TpC. Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
DS97LVO0900 |
P R E L I M I N A R Y |
6-15 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
AC CHARACTERISTICS
Additional Timing Diagram
|
1 |
|
3 |
Clock |
|
|
|
|
2 |
2 |
3 |
7 |
7 |
|
|
TIN
4 5
6
IRQ N
8 |
9 |
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 8. Additional Timing
6-16 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary
Additional Timing Table
|
|
|
|
TA = 0°C to +70°C |
|
|
|
|
|
|
|
8.0MHz |
|
|
|
No |
Sym |
Parameter |
VCC |
Min |
Max |
Units |
Notes |
1 |
TpC |
Input Clock Period |
2.0V |
121 |
DC |
ns |
1 |
|
|
|
3.9V |
121 |
DC |
ns |
1 |
|
|
|
|
|
|
|
|
2 |
TrC,TfC |
Clock Input Rise |
2.0V |
|
25 |
ns |
1 |
|
|
and Fall Times |
3.9V |
|
25 |
ns |
1 |
|
|
|
|
|
|
|
|
3 |
TwC |
Input Clock Width |
2.0V |
37 |
|
ns |
1 |
|
|
|
3.9V |
37 |
|
ns |
1 |
|
|
|
|
|
|
|
|
4 |
TwTinL |
Timer Input |
2.0V |
100 |
|
ns |
1 |
|
|
Low Width |
3.9V |
70 |
|
ns |
1 |
|
|
|
|
|
|
|
|
5 |
TwTinH |
Timer Input |
2.0V |
3TpC |
|
|
1 |
|
|
High Width |
3.9V |
3TpC |
|
|
1 |
|
|
|
|
|
|
|
|
6 |
TpTin |
Timer Input |
2.0V |
8TpC |
|
|
1 |
|
|
Period |
3.9V |
8TpC |
|
|
1 |
|
|
|
|
|
|
|
|
7 |
TrTin,TfTin |
Timer Input Rise |
2.0V |
|
100 |
ns |
1 |
|
|
and Fall Timers |
3.9V |
|
100 |
ns |
1 |
|
|
|
|
|
|
|
|
8A |
TwIL |
Interrupt Request |
2.0V |
100 |
|
ns |
1,2 |
|
|
Low Time |
3.9V |
70 |
|
ns |
1,2 |
|
|
|
|
|
|
|
|
8B |
TwIL |
Interrupt Request |
2.0V |
5TpC |
|
|
1,3 |
|
|
Low Time |
3.9V |
5TpC |
|
|
1,3 |
|
|
|
|
|
|
|
|
9 |
TwIH |
Interrupt Request |
2.0V |
5TpC |
|
|
1,2 |
|
|
Input High Time |
3.9V |
5TpC |
|
|
1,2 |
|
|
|
|
|
|
|
|
10 |
Twsm |
Stop-Mode Recovery |
2.0V |
12 |
|
ns |
7 |
|
|
Width Spec |
3.9V |
12 |
|
ns |
7 |
|
|
|
2.0V |
5 TpC |
|
ns |
6 |
|
|
|
3.9V |
5 TpC |
|
ns |
6 |
|
|
|
|
|
|
|
|
11 |
Tost |
Oscillator |
2.0V |
|
5TpC |
|
4 |
|
|
Start-Up Time |
3.9V |
|
5TpC |
|
4 |
|
|
|
|
|
|
|
|
12 |
Twdt |
Watch-Dog Timer |
2.0V |
12 |
75 |
ms |
|
|
|
Delay Time (5 ms) |
3.9V |
5 |
20 |
ms |
|
|
|
(10 ms) |
2.0V |
25 |
150 |
ms |
|
|
|
|
3.9V |
10 |
40 |
ms |
|
|
|
(20 ms) |
2.0V |
50 |
300 |
ms |
|
|
|
|
3.9V |
20 |
80 |
ms |
|
|
|
(80 ms) |
2.0V |
225 |
1200 |
ms |
|
|
|
|
3.9V |
80 |
320 |
ms |
|
|
|
|
|
|
|
|
|
Notes:
1.Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2.Interrupt request through Port 3 (P33-P31).
3.Interrupt request through Port 3 (P30).
4.SMR bit D5 = 0
DS97LVO0900 |
P R E L I M I N A R Y |
6-17 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
AC CHARACTERISTICS(Z86C72/C92 SPECIFICATIONS)
Preliminary
Additional Timing Table
|
|
|
|
TA = 0°C to +70°C |
|
|
|
|
|
|
|
16.0 MHz |
|
|
|
No |
Symbol |
Parameter |
VCC |
Min |
Max |
Units |
Notes |
1 |
TpC |
Input Clock Period |
4.5V |
63 |
DC |
ns |
1 |
|
|
|
5.5V |
63 |
DC |
ns |
1 |
|
|
|
|
|
|
|
|
2 |
TrC, TfC |
Clock Input Rise and |
4.5V |
|
15 |
ns |
1 |
|
|
Fall Times |
5.5V |
|
15 |
ns |
1 |
|
|
|
|
|
|
|
|
3 |
TwC |
Input Clock Width |
4.5V |
31 |
|
ns |
1 |
|
|
|
5.5V |
31 |
|
ns |
1 |
|
|
|
|
|
|
|
|
4 |
TwTinL |
Timer Input Low |
4.5V |
100 |
|
ns |
1 |
|
|
Width |
5.5V |
70 |
|
ns |
1 |
|
|
|
|
|
|
|
|
5 |
TwTinH |
Timer Input High |
4.5V |
5TpC |
|
|
1 |
|
|
Width |
5.5V |
5TpC |
|
|
1 |
|
|
|
|
|
|
|
|
6 |
TpTin |
Timer Input Period |
4.5V |
8TpC |
|
|
1 |
|
|
|
5.5V |
8TpC |
|
|
1 |
|
|
|
|
|
|
|
|
7 |
TrTin, TfTin |
Timer Input Rise |
4.5V |
|
100 |
ns |
1 |
|
|
|
5.5V |
|
100 |
ns |
1 |
|
|
|
|
|
|
|
|
8A |
TwIL |
Interrupt Request |
4.5V |
100 |
|
ns |
1,2 |
|
|
Low Time |
5.5V |
70 |
|
ns |
1,2 |
|
|
|
|
|
|
|
|
8B |
TwIL |
Int. Request Low |
4.5V |
5TpC |
|
|
1,3 |
|
|
Time |
5.5V |
5TpC |
|
|
1,3 |
|
|
|
|
|
|
|
|
9 |
TwIH |
Interrupt Request |
4.5V |
5TpC |
|
|
1,2 |
|
|
Input High Time |
5.5V |
5TpC |
|
|
1,2 |
|
|
|
|
|
|
|
|
10 |
Twsm |
Stop-Mode |
4.5V |
12 |
|
ns |
8 |
|
|
Recovery Width |
5.5V |
12 |
|
ns |
8 |
|
|
Spec |
4.5V |
5TpC |
|
|
7 |
|
|
|
|
5TpC |
|
|
7 |
|
|
|
|
|
|
|
|
11 |
Tost |
Oscillator Start-up |
4.5V |
|
5TpC |
|
4 |
|
|
Time |
5.5V |
|
5TpC |
|
4 |
|
|
|
|
|
|
|
|
12 |
Twdt |
Watch-Dog Timer |
4.5V |
2.0 |
|
ms |
D0=0, 5 |
|
|
Delay Time |
5.5V |
2.0 |
|
ms |
D1=0, 5 |
|
|
(2.0 ms) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4.0 ms |
4.5V |
4.0 |
|
ms |
D0=1, 5 |
|
|
|
5.5V |
4.0 |
|
ms |
D1=0, 8 |
|
|
|
|
|
|
|
|
|
|
8.0 ms |
4.5V |
8.0 |
|
ms |
D0=1, 5 |
|
|
|
5.5V |
8.0 |
|
ms |
D1=0, 8 |
|
|
|
|
|
|
|
|
|
|
32 ms |
4.5V |
32 |
|
ms |
D0=1, 5 |
|
|
|
5.5V |
32 |
|
ms |
D1=0, 8 |
|
|
|
|
|
|
|
|
Notes:
1.Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2.Interrupt request through Port 3 (P33-P31).
3.Interrupt request through Port 3 (P30).
4.SMR bit D5 = 0
5.Reg. WDTMR bit D0=1
6.Reg. SMR bit D5 = 0
7.Reg. SMR bit D5 = 1
8.Reg. WDTMR bit D1-0
6-18 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
AC CHARACTERISTICS
Handshake Timing Diagrams
Data In |
Data In Valid |
Next Data In Valid |
|
|
|
2 |
|
|
1 |
|
|
|
3 |
|
|
/DAV |
|
Delayed DAV |
|
(Input) |
|
|
|
|
4 |
5 |
6 |
RDY |
|
Delayed RDY |
|
(Output) |
|
|
|
Figure 9. Port I/O with Input Handshake Timing
Data Out |
Data Out Valid |
|
Next Data Out Valid |
|
7 |
|
|
/DAV |
|
|
Delayed DAV |
(Output) |
|
|
|
|
8 |
9 |
11 |
|
|
10 |
|
RDY |
|
|
Delayed RDY |
(Input) |
|
|
|
Figure 10. Port I/O with Output Handshake Timing
DS97LVO0900 |
P R E L I M I N A R Y |
6-19 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary
Handshake Timing Table
|
|
|
|
TA = 0°C to +70°C |
Data |
|
No |
Sym |
Parameter |
VCC |
Min |
Max |
Direction |
1 |
TsDI(DAV) |
Data In Setup Time |
2.0V |
0 |
|
IN |
|
|
|
3.9V |
0 |
|
IN |
|
|
|
|
|
|
|
2 |
ThDI(DAV) |
Data In Hold Time |
2.0V |
0 |
|
IN |
|
|
|
3.9V |
0 |
|
IN |
|
|
|
|
|
|
|
3 |
TwDAV |
Data Available Width |
2.0V |
155 |
|
IN |
|
|
|
3.9V |
110 |
|
IN |
|
|
|
|
|
|
|
4 |
TdDAVI(RDY) |
DAV Falling to RDY |
2.0V |
|
160 |
IN |
|
|
Falling Delay |
3.9V |
|
115 |
IN |
|
|
|
|
|
|
|
5 |
TdDAVId(RDY) |
DAV Rising to RDY |
2.0V |
|
120 |
IN |
|
|
Falling Delay |
3.9V |
|
80 |
IN |
|
|
|
|
|
|
|
6 |
TdRDYO(DAV) |
RDY Rising to DAV |
2.0V |
0 |
|
IN |
|
|
Falling Delay |
3.9V |
0 |
|
IN |
|
|
|
|
|
|
|
7 |
TdDO(DAV) |
Data Out to DAV |
2.0V |
63 |
|
OUT |
|
|
Falling Delay |
3.9V |
63 |
|
OUT |
|
|
|
|
|
|
|
8 |
TdDAV0(RDY) |
DAV Falling to RDY |
2.0V |
0 |
|
OUT |
|
|
Falling Delay |
3.9V |
0 |
|
OUT |
|
|
|
|
|
|
|
9 |
TdRDY0(DAV) |
RDY Falling to DAV |
2.0V |
|
160 |
OUT |
|
|
Rising Delay |
3.9V |
|
115 |
OUT |
|
|
|
|
|
|
|
10 |
TwRDY |
RDY Width |
2.0V |
110 |
|
OUT |
|
|
|
3.9V |
80 |
|
OUT |
|
|
|
|
|
|
|
11 |
TdRDY0d(DAV) |
RDY Rising to DAV |
2.0V |
|
110 |
OUT |
|
|
Falling Delay |
3.9V |
|
80 |
OUT |
|
|
|
|
|
|
|
6-20 |
P R E L I M I N A R Y |
DS97LVO0900 |
|
Z86C72/C92/L72/L92 |
Zilog |
IR Microcontroller |
|
|
AC CHARACTERISTICS(Z86C72/C92 SPECIFICATIONS)
Preliminary
Handshake Timing Table
|
|
|
|
TA = 0°C to +70°C |
|
|
|
|
|
|
|
16.0 MHz |
|
No |
Symbol |
Parameter |
VCC |
Min |
Max |
Data Direction |
1 |
TSD(DAV) |
Data in Setup Time |
4.5V |
0 |
|
IN |
|
|
|
5.5V |
0 |
|
IN |
|
|
|
|
|
|
|
2 |
ThD(DAV) |
Data in Hold Time |
4.5V |
160 |
|
IN |
|
|
|
5.5V |
115 |
|
IN |
|
|
|
|
|
|
|
3 |
TwDAV |
Data Available Width |
4.5V |
155 |
|
IN |
|
|
|
5.5V |
110 |
|
IN |
|
|
|
|
|
|
|
4 |
TdDAVI(RDY) |
DAV Falling to RDY |
4.5V |
|
160 |
IN |
|
|
Falling Delay |
5.5V |
|
115 |
IN |
|
|
|
|
|
|
|
5 |
TdDAVId(RDY) |
DAV Rising to RDY |
4.5V |
|
120 |
IN |
|
|
Falling Delay |
5.5V |
|
80 |
IN |
|
|
|
|
|
|
|
6 |
TdRDY)(DAV) |
RDY Rising to DAV |
4.5V |
0 |
|
IN |
|
|
Falling Delay |
5.5V |
0 |
|
IN |
|
|
|
|
|
|
|
7 |
TdD0(DAV) |
Data Out to DAV |
4.5V |
31 |
|
OUT |
|
|
Falling Delay |
5.5V |
31 |
|
OUT |
|
|
|
|
|
|
|
8 |
TdDAV0(RDY) |
DAV Falling to RDY |
4.5V |
0 |
|
OUT |
|
|
Falling Delay |
5.5V |
0 |
|
OUT |
|
|
|
|
|
|
|
9 |
TdRDY0(DAV) |
RDY Falling to DAV |
4.5V |
|
160 |
OUT |
|
|
|
5.5V |
|
115 |
OUT |
|
|
|
|
|
|
|
10 |
TwRDY |
RDY Width |
4.5V |
110 |
|
OUT |
|
|
|
5.5V |
80 |
|
OUT |
|
|
|
|
|
|
|
11 |
TdRDY0d(DAV) |
RDY Rising to DAV |
4.5V |
|
110 |
OUT |
|
|
Falling Dealy |
5.5V |
|
80 |
OUT |
|
|
|
|
|
|
|
DS97LVO0900 |
P R E L I M I N A R Y |
6-21 |
Z86C72/C92/L72/L92 |
|
IR Microcontroller |
Zilog |
PIN FUNCTIONS
/DS (Output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid.
/AS (Output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write.
XTAL1 Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network or an external single-phase clock to the on-chip oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output.
R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory.
R//RL (input). This pin, when connected to GND, disables the internal ROM and forces the device to function as a ROMless Z8. (Note that, when left unconnected or pulled high to VCC, the part functions normally as a Z8 ROM version.)
Port 0 (P07-P00). Port 0 is an 8-bit, bi-directional, CMOS compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The output drivers are push-pull. Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0. Handshake signal direction is dictated by the I/O direction to Port 0 of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble.
For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port.
Port 0 is set in the high-impedance mode (if selected as an address output) along with Port 1 and the control signals /AS, /DS, and R//W through P3M bits D4 and D3(Figure 11).
A ROM mask option is available to program 0.4 VDD CMOS trip inputs on P00-P03 of the L72. This allows direct interface to mouse/trackball IR sensors.
An optional 200 kOhm pull-up is available as a mask option on all Port 0 bits with nibble select. These pull-ups are disabled when configured (bit by bit) as an output.
6-22 |
P R E L I M I N A R Y |
DS97LVO0900 |
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