ZiLOG Z8 User Manual

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Z8 Family of Microcontrollers

Z8 CPU

User Manual

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ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com

Z8 Family of Microcontrollers

User Manual

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact:

ZiLOG Worldwide Headquarters

532 Race Street San Jose, CA 95126

Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com

Document Disclaimer

ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated.

©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or ﬁtness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

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Revision History

Each instance in Table 1 reﬂects a change to this document from its previous revision. To see more detail, click the appropriate link in the table.

Table 1. Revision History of this Document

	Revision
Date	Level	Section	Description	Page #

Sept.	02	Formatted to current publication standards		All
2004

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Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Z8 CPU Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Z8 CPU Standard Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RAM Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Working Register Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Z8 Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Z8 Control and Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Standard Z8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Expanded Z8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Z8 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Z8 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SCLK ÷ TCLK Divide-By-16 Select . . . . . . . . . . . . . . . . . . . . . . . . . 34

External Clock Divide-By-Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Indications of an Unreliable Design . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Crystals and Resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

LC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Reset Pin, Internal POR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Watch–Dog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Input and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

General I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

General I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Handshake Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

General Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

General Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Port Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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I/O Port Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Full Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Comparator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Comparator Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Comparator Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Open-Drain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Low EMI Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Z8 CMOS Autolatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Autolatch Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Counters and Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	115
Prescalers and Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
Counter/Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120
Load and Enable Count Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120
Prescaler Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	122
TOUT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	124
TIN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	127
External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	129
Gated Internal Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	129
Triggered Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	130
Retriggerable Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	131
Cascading Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	132
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	132

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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

External Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Internal Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Interrupt Request Register Logic and Timing . . . . . . . . . . . . . . . . . . . . . 141

Interrupt Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Interrupt Priority Register Initialization . . . . . . . . . . . . . . . . . . . . . . 143

Interrupt Mask Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . 145

Interrupt Request Register Initialization . . . . . . . . . . . . . . . . . . . . . . 147

IRQ Software Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Vectored Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Vectored Interrupt Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Nesting of Vectored Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Polled Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Halt Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Serial Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

UART Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

UART Bit-Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

UART Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Receiver Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

UART Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

SPI Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

SPI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Receive Character Available and Overrun . . . . . . . . . . . . . . . . . . . . . . . 182

External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

External Addressing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

External Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Extended Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Z8 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Processor Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Sign Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Decimal Adjust Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Half Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Notation and Binary Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Z8 Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

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Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Customer Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

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List of Figures
Figure 1.	Z8 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .	. 3
Figure 2.	16-Bit Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . .	9
Figure 3.	Accessing Individual Bits (Example) . . . . . . . . . . . . . . . . .	9
Figure 4.	Working Register Addressing Examples . . . . . . . . . . . . .	12
Figure 5.	Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 6.	Expanded Register File Architecture . . . . . . . . . . . . . . . .	15
Figure 7.	Register Pointer Example . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 8.	Z8 Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 9.	External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 10.	Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 11.	Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 12.	Z8® CPU Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 13.	Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . .	34
Figure 14.	External Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 15.	Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . .	36
Figure 16.	Pierce Oscillator with Internal Feedback Circuit . . . . . . .	37
Figure 17.	Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 18.	Crystal/Ceramic Resonator Oscillator . . . . . . . . . . . . . . . .	41
Figure 19.	LC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 20.	External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 21.	RC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
Figure 22.	Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49

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Figure 23. Example of External Power-On Reset Circuit . . . . . . . . . .		50
Figure 24. Example of Z8 Reset with RESET Pin, WDT, SMR,
	and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Figure 25. Example of Z8 Reset with WDT, SMR, and POR . . . . . .		54
Figure 26. Example of Z8 Watch–Dog Timer Mode Register . . . . . .		56
Figure 27. Example of Z8 with Simple SMR and POR . . . . . . . . . . .		59
Figure 28. I/O Ports and Mode Registers . . . . . . . . . . . . . . . . . . . . . .		62
Figure 29. Ports 0, 1, 2 Generic Block Diagram . . . . . . . . . . . . . . . .		64
Figure 30. Port 0 Configuration with Open-Drain Capability,
	Autolatch, and Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . .	66
Figure 31. Port 0 Configuration with TTL Level Shifter . . . . . . . . . .		67
Figure 32. Port 0 I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		69
Figure 33. Port 0 Handshake Operation . . . . . . . . . . . . . . . . . . . . . . .		69
Figure 34. Port 1 Configuration with Open-Drain Capability,
	Autolatch, and Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . .	70
Figure 35. Port 1 Configuration with TTL Level Shifter . . . . . . . . . .		71
Figure 36. Port 1 I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		72
Figure 37.	Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73
Figure 38. Port 2 I/O Mode Configuration . . . . . . . . . . . . . . . . . . . . .		74
Figure 39. Port 2 Configuration with Open-Drain Capability,
	Autolatch, and Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . .	75
Figure 40. Port 2 Configuration with TTL Level Shifter . . . . . . . . . .		76
Figure 41. Port 2 Configuration with Open-Drain Capability,
	Autolatch, Schmitt-Trigger and SPI . . . . . . . . . . . . . . . . .	77
Figure 42.	Port 2 Handshake Configuration . . . . . . . . . . . . . . . . . . . .	79

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Figure 43. Port 2 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 79
Figure 44. Port 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 81
Figure 45. Port 3 Configuration with Comparator, Autolatch, and
	Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 83
Figure 46. Port 3 Configuration with Comparator . . . . . . . . . . . . . .		. 84
Figure 47. Port 3 Configuration with SPI and Comparator Outputs		. 86
Figure 48. Port 3 Configuration with TTL Level Shifter and
	Autolatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 87
Figure 49. Port 3 Mode Register Configuration . . . . . . . . . . . . . . . .		. 88
Figure 50. Z8 Input Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 92
Figure 51. Z8 Output Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 93
Figure 52. Output Strobed Handshake on Port 2 . . . . . . . . . . . . . . .		. 94
Figure 53. Input Strobed Handshake on Port 2 . . . . . . . . . . . . . . . .		. 94
Figure 54. Port 0/1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 96
Figure 55.	Port 2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 97
Figure 56. Port 3 Mode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 98
Figure 57. Port 3 Input Analog Selection . . . . . . . . . . . . . . . . . . . . .		. 99
Figure 58. Port 3 Comparator Output Selection . . . . . . . . . . . . . . . .		100
Figure 59. Port Configuration of Comparator Inputs on P31, P32,
	and P33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	101
Figure 60. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .		102
Figure 61. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .		105
Figure 62. Port Configuration Register . . . . . . . . . . . . . . . . . . . . . .		106
Figure 63. Diode Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . .		109
Figure 64.	OTP Diode Input Protection . . . . . . . . . . . . . . . . . . . . . .	110

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Figure 65. Simplified CMOS Z8 I/O Circuit . . . . . . . . . . . . . . . . . . 111 Figure 66. Autolatch Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . 113 Figure 67. Effect of Pulldown Resistors on Autolatches . . . . . . . . . 114 Figure 68. Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . 116 Figure 69. Counter/Timer Register Map . . . . . . . . . . . . . . . . . . . . . . 118 Figure 70. Prescaler 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 71. Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 72. Counter/Timer 0 and 1 Registers . . . . . . . . . . . . . . . . . . . 119 Figure 73. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 74. Starting The Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 75. Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 76. Timer Mode Register (TOUT Operation) . . . . . . . . . . . . . 124 Figure 77. Port 3 Mode Register (TOUT Operation) . . . . . . . . . . . . . 125 Figure 78. T0 and T1 Output Through TOUT . . . . . . . . . . . . . . . . . . 126 Figure 79. Internal Clock Output Through TOUT . . . . . . . . . . . . . . . 127 Figure 80. Timer Mode Register (TIN Operation) . . . . . . . . . . . . . . 128 Figure 81. Prescaler 1 Register (TIN Operation) . . . . . . . . . . . . . . . . 128 Figure 82. External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 83. Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 84. Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 85. Cascaded Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 86. Counter/Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 87. Prescaler 1 Register Reset . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 88. Prescaler 0 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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Figure 89.	Timer Mode Register Reset . . . . . . . . . . . . . . . . . . . . . .	135
Figure 90.	Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . .	137
Figure 91.	Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .	138
Figure 92.	Interrupt Sources IRQ0-IRQ2 Block Diagram . . . . . . . .	140
Figure 93.	Interrupt Source IRQ3 Block Diagram . . . . . . . . . . . . . .	141
Figure 94.	IRQ Register Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	142
Figure 95.	Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . .	143
Figure 96.	Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . .	144
Figure 97.	Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . .	146
Figure 98.	Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . .	148
Figure 99.	IRQ Reset Functional Logic Diagram . . . . . . . . . . . . . . .	149
Figure 100.	Effects of an Interrupt on the Stack . . . . . . . . . . . . . . . . .	151
Figure 101.	Interrupt Vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	152
Figure 102.	Z8 Interrupt Acknowledge Timing . . . . . . . . . . . . . . . . .	153
Figure 103.	Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . .	160
Figure 104.	Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . .	163
Figure 105.	UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .	165
Figure 106.	Port 3 Mode Register and Bit-Rate Generation . . . . . . .	167
Figure 107.	Bit Rate Divide Chain . . . . . . . . . . . . . . . . . . . . . . . . . . .	167
Figure 108.	Prescaler 0 Register Bit-Rate Generation . . . . . . . . . . . .	169
Figure 109.	Timer Mode Register Bit Rate Generation . . . . . . . . . . .	169
Figure 110.	Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	171
Figure 111.	Receiver Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . .	172
Figure 112.	Port 3 Mode Register Parity . . . . . . . . . . . . . . . . . . . . . .	173

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Figure 113. Transmitter Data Formats . . . . . . . . . . . . . . . . . . .	. . . . . 175
Figure 114. SIO Register Reset . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 175
Figure 115. P3M Register Reset . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 176
Figure 116. SPI Control Register . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 178
Figure 117. SPI System Configuration . . . . . . . . . . . . . . . . . . .	. . . . . 181
Figure 118. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 182
Figure 119. SPI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 183
Figure 120. SPI Data In/Out Configuration . . . . . . . . . . . . . . .	. . . . . 184
Figure 121. SPI Clock/SPI Slave Select Output Configuration	. . . . . 185
Figure 122. Z8 CPU External Interface Pins . . . . . . . . . . . . . .	. . . . . 187
Figure 123. External Address Configuration . . . . . . . . . . . . . .	. . . . . 190
Figure 124. Z8 Stack Selection . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 191
Figure 125. Port 3 Data Memory Operation . . . . . . . . . . . . . . .	. . . . . 192
Figure 126. External Instruction Fetch or Memory Read Cycle	. . . . . 193
Figure 127. External Memory Write Cycle . . . . . . . . . . . . . . . .	. . . . . 194
Figure 128. Extended External Instruction Fetch or Memory Read
Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 196
Figure 129. Extended External Memory Write Cycle . . . . . . .	. . . . . 197
Figure 130. Extended Bus Timing . . . . . . . . . . . . . . . . . . . . . .	. . . . . 198
Figure 131. Instruction Cycle Timing (1-Byte Instructions) . .	. . . . . 199
Figure 132. Instruction Cycle Timing (2- and 3-Byte Instructions) . . 200
Figure 133. Z8 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 205
Figure 134. Op Code Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 222

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List of Tables

Table 1.	Revision History of this Document . . . . . . . . . . . . . . . . .	. . iii
Table 2.	ZiLOG General-Purpose Microcontroller Product Family . 4
Table 3.	Z8 Standard Register File . . . . . . . . . . . . . . . . . . . . . . . .	. . 7
Table 4.	Working Register Groups . . . . . . . . . . . . . . . . . . . . . . . .	. 11
Table 5.	ERF Bank Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 17
Table 6.	Register Pointer Access Example . . . . . . . . . . . . . . . . . .	. 18
Table 7.	ERF Bank C Access Example . . . . . . . . . . . . . . . . . . . . .	. 20
Table 8.	Z8 Expanded Register File Bank Layout . . . . . . . . . . . .	. 20
Table 9.	Expanded Register File Register Bank C . . . . . . . . . . . .	. 23
Table 10.	Expanded Register File Bank 0 . . . . . . . . . . . . . . . . . . . .	. 24
Table 11.	Expanded Register File Bank F . . . . . . . . . . . . . . . . . . . .	. 25
Table 12.	Crystal/Resonator Characteristics . . . . . . . . . . . . . . . . . .	. 41
Table 13.	Sample Control and Peripheral Register Reset Values
	(ERF Bank 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 48
Table 14.	Expanded Register File Bank 0 Reset Values at RESET	. 51
Table 15.	Sample Expanded Register File Bank C Reset Values . .	. 51
Table 16.	Sample Expanded Register File Bank F Reset Values . . . 52
Table 17.	Time-Out Period of the WDT . . . . . . . . . . . . . . . . . . . . .	. 57
Table 18.	Port 3 Line Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 89
Table 19.	Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . .	139
Table 20.	Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	144
Table 21.	Interrupt Group Priority . . . . . . . . . . . . . . . . . . . . . . . . .	145
Table 22.	IRQ Register Configuration . . . . . . . . . . . . . . . . . . . . . .	149
Table 23.	Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . .	161
Table 24.	UART Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166
Table 25.	Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	168

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Table 26. SPI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 27. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 28. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 29. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 30. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . 202 Table 31. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . 203 Table 32. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . 203 Table 33. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . 204 Table 34. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 35. Z8 Flag Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 36. Flag Settings Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 37. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 38. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 39. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 40. Summary of Z8 Instruction Set . . . . . . . . . . . . . . . . . . . . 213 Table 41. Summary of Z8 Address Modes . . . . . . . . . . . . . . . . . . . 221 Table 42. Process Manipulation Functions . . . . . . . . . . . . . . . . . . . 223

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Z8 CPU Product Overview

The ZiLOG Z8 microcontroller (MCU) product line continues to expand with new product introductions. ZiLOG MCU products are targeted for cost-sensitive, high-volume applications including consumer, automotive, security, and HVAC. It includes ROM-based products geared for highvolume production (where software is stable) and one-time programmable (OTP) equivalents for prototyping as well as volume production where time to market or code ﬂexibility is critical (see Table 1 on page 4). A variety of packaging options are available including plastic DIP, SOIC, PLCC, and QFP.

A generalized Z8 CPU® block diagram is shown in Figure 1. The same on-chip peripherals are used across the MCU product line with the primary differences being the amount of ROM/RAM, number of I/O lines present, and packaging/temperature ranges available. This allows code written for one MCU device to be easily ported to another family member.

Key Features

General-Purpose Register File. Every RAM register acts like an accumulator, speeding instruction execution and maximizing coding efﬁciency. Working register groups allow fast context switching.

Flexible I/O. I/O byte, nibble, and/or bit programmable as inputs or outputs. Outputs are software programmable as open-drain or push–pull on a port basis. Inputs are Schmitt-triggered with autolatches to hold unused inputs at a known voltage state.

Analog Inputs. Three input pins are software programmable as digital or analog inputs. When in analog mode, two comparator inputs are provided with a common reference input. These inputs are ideal for a variety of common functions, including threshold level detection, analog-to-digital

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User Manual

conversion, and short circuit detection. Each analog input provides a unique maskable interrupt input.

Timer/Counter. The Timer/Counter (T/C) consists of a programmable 6- bit prescaler and 8-bit downcounter, with maskable interrupt upon end-of- count. Software controls T/C load/start/stop, countdown read (at any time on the ﬂy), and maskable end-of-count interrupt. Special functions available include TIN (external counter input, external gate input, or external trigger input) and TOUT (external access to timer output or the internal system clock.) These special functions allow accurate hardware input pulse measurement and output waveform generation.

Interrupts. There are six vectored interrupt sources with software-pro- grammable enable and priority for each of the six sources.

Watch–Dog Timer. An internal Watch–Dog Timer (WDT) circuit is included as a fail-safe mechanism so that if software strays outside the bounds of normal operation, the WDT will time-out and reset the MCU. To maximize circuit robustness and reliability, the default WDT clock source is an internal RC circuit (isolated from the device clock source).

Auto Reset/Low-Voltage Protection. All family devices have internal Power-On Reset. ROM devices add low-voltage protection. Low-voltage protection ensures the MCU is in a known state at all times (in active RUN mode or RESET) without external hardware (or a device reset pin).

Low-EMI Operation. Mode is programmable via software or as a mask option. This new option provides for reduced radiated emission via clock and output drive circuit changes.

Low-Power. CMOS with two standby modes; STOP and HALT.

Full Z8 Instruction Set. Forty-eight basic instructions, supported by six addressing modes with the ability to operate on bits, nibbles, bytes, and words.

Z8 CPU Product Overview

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Output Input

Port 3

Counter/

Timers (2)

Interrupt

Control

Analog

Comparators

(2)

Port 2

I/O

(Bit Programmable)

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User Manual

VCC GND

ALU

FLAG

Pointer

256 x 8-Bit

Port 0

Address or I/O (Nibble Programmable)

XTAL AS DS R/W RESET

Machine Timing

& Instruction Control

RESET, WDT,

POR

Prg. Memory 512/K x 8-Bit

Program

Counter

Port 1

Address/Data or I/O (Byte Programmable)

Figure 1. Z8 CPU Block Diagram

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Product Development Support

The Z8® MCU product line is fully supported with a range of cross assemblers, C compilers, ICEBOX emulators, single and gang OTP/ EPROM programmers, and software simulators.

The Z86CCP01ZEM low-cost Z8 CCP™ real-time emulator/programmer kit was designed speciﬁcally to support all of the products outlined in Table 1.

Table 1. ZiLOG General-Purpose Microcontroller Product Family

	ROM/									Speed	Pin
Product	RAM	I/0	T/C	AN	INT	WDT	POR	VBO	RC	(MHz)	Count
Z86C03	512/60	14	1	2	6	F	Y	Y	Y	8	18

Z86E03	512/60	14	1	2	6	F	Y	N	Y	8	18

Z86C04	1K/124	14	2	2	6	F	Y	Y	Y	8	18

Z86E04	1K/124	14	2	2	6	F	Y	N	Y	8	18

Z86C06	1K/124	14	2	2	6	P	Y	Y	Y	12	18

Z86E06	1K/124	14	2	2	6	P	Y	N	Y	12	18

Z86C08	2K/124	14	2	2	6	F	Y	Y	Y	12	18

Z86E08	2K/124	14	2	2	6	F	Y	N	Y	12	18

Z86C30	4K/236	24	2	2	6	P	Y	Y	Y	12	28

Z86E30	4K/236	24	2	2	6	P	Y	N	Y	12	28

Z86C31	2K/124	24	2	2	6	P	Y	Y	Y	8	28

Z86E31	2K/124	24	2	2	6	P	Y	N	Y	8	28

Z86C40	4K/236	32	2	2	6	P	Y	Y	Y	16	40/44

Z86E40	4K/236	32	2	2	6	P	Y	N	Y	16	40/44

*Note: Z86Cxx signify ROM devices; 86xx signify EPROM devices; F = fixed; P = programmable

Z8 CPU Product Overview

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The Z86CCP01ZEM kit comes with:

•Z8 CCP Evaluation Board

•Z8 CCP Power Cable

•ZiLOG Developer’s Studio (ZDS) CD-ROM , Including WindowsBased GUI Host Software

•1999 ZiLOG Technical Library

•Z8 CCP User Manual

A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also available and provides an RS-232 cable and power cable along with the 28and 40pin ZIF sockets and 28and 40pin target connector cables required to emulate/program 28/40 pin devices.

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Z8 CPU Product Overview

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Address Space

Introduction

Four address spaces are available for the Z8® CPU:

•The Z8® Standard Register File contains addresses for peripheral, control, all general-purpose, and all I/O port registers. This is the default register ﬁle speciﬁcation.

•The Z8® Expanded Register File (ERF) contains addresses for control and data registers for additional peripherals/features.

•Z8 external program memory contains addresses for all memory locations having executable code and/or data.

•Z8 external data memory contains addresses for all memory locations that hold data only, whether internal or external.

Z8 CPU Standard Register File

The Z8® Standard Register File totals up to 256 consecutive bytes (Registers). The register ﬁle consists of 4 I/O ports (00h–03h), 236 GeneralPurpose Registers (04h–EFh), and 16 control registers (F0h–FFh). Table 2 shows the layout of the register ﬁle, including register names, locations, and identiﬁers.

Table 2. Z8 Standard Register File

Hex Address	Register Identifier	Register Description

FF	SPL	Stack Pointer Low Byte

FE	SPH	Stack Pointer High Byte

FD	RP	Register Pointer

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Table 2. Z8 Standard Register File (Continued)

Hex Address	Register Identifier	Register Description

FC	FLAGS	Program Control Flags

FB	IMR	Interrupt Mask Register

FA	IRQ	Interrupt Request Register

F9	IPR	Interrupt Priority Register

F8	P01M	Port 0–1 Mode Register

F7	P3M	Port 3 Mode Register

F6	P2M	Port 2 Mode Register

F5	PRE0	T0 Prescaler

F4	T0	Timer/Counter 0

F3	PRE1	T1 Prescaler

F2	T1	Timer/Counter 1

F1	TMR	Timer Mode

F0	SIO	Serial I/O

EF	R239

General-Purpose Registers (GPR)
04	R4

03	P3	Port 3

02	P2	Port 2

01	P1	Port 1

00	P0	Port 0

Registers can be accessed as either 8-bit or 16-bit registers using Direct, Indirect, or Indexed Addressing. All 236 general-purpose registers can be

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referenced or modiﬁed by any instruction that accesses an 8-bit register, without the requirement for special instructions. Registers accessed as 16 bits are treated as even-odd register pairs (there are 118 valid pairs). In this case, the data’s Most Signiﬁcant Byte (MSB) is stored in the even numbered register, while the Least Signiﬁcant Byte (LSB) goes into the next higher odd numbered register. See Figure 2.

MSB LSB

Rn Rn+1

n = Even Address

Figure 2. 16-Bit Register Addressing

By using a logical instruction and a mask, individual bits within registers can be accessed for bit set, bit clear, bit complement, or bit test operations. For example, the instruction AND R15, MASK performs a bit clear operation. Figure 3 shows this example.

0	1		1		1		0		0		0		0		R15
															MASK

1		1		0		1		1		1		1		1

AND R15, DFh									;Clear Bit 5 of Working Register 15
															R15
0	1		0		1		0		0		0		0		R15

Figure 3. Accessing Individual Bits (Example)

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When instructions are executed, registers are read when deﬁned as sources and written when deﬁned as destinations. All General-Purpose Registers function as accumulators, address pointers, index registers, stack areas, or scratch pad memory.

General-Purpose Registers

General-Purpose Registers (GPR) are undeﬁned after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-speciﬁed operating range. It will not keep its last state from a VLV reset if VCC drops below 1.8v.

Note: Registers in Bank E0-EF may only be accessed through the working register and indirect addressing modes. Direct access cannot be used because the 4-bit working register address mode already uses the format [E | dst], where dst represents the working register number from 0h to Fh.

RAM Protect

The upper portion of the register ﬁle address space 80h to EFh (excluding the control registers) may be protected from reading and writing. The RAM Protect bit option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask option is selected, the user activates this feature from the internal ROM code to turn off/on the RAM Protect by loading either a 0 or 1 into the IMR register, bit D6. A 1 in D6 enables RAM Protect. Only devices that use registers 80h to EFh offer this feature.

Working Register Groups

Z8 instructions can access 8-bit registers and register pairs (16-bit words) using either 4-bit or 8-bit address ﬁelds. 8-bit address ﬁelds refer to the actual address of the register. For example, Register 58h is accessed by calling upon its 8-bit binary equivalent, 01011000 (58h).

With 4-bit addressing, the register ﬁle is logically divided into 16 Working Register Groups of 16 registers each, as shown in Table 3. These 16

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registers are known as Working Registers. A Register Pointer (one of the control registers, FDh) contains the base address of the active Working Register Group. The high nibble of the Register Pointer determines the current Working Register Group.

When accessing one of the Working Registers, the 4-bit address of the Working Register is combined within the upper four bits (high nibble) of the Register Pointer, thus forming the 8-bit actual address. Figure 4 illustrates this operation. Because working registers are typically speciﬁed by short format instructions, there are fewer bytes of code required, which reduces execution time. In addition, when processing interrupts or changing tasks, the Register Pointer speeds context switching. A special Set Register Pointer (SRP) instruction sets the contents of the Register Pointer.

Table 3. Working Register Groups

Register Pointer	Working Register	Actual Registers
(FDh) High Nibble	Group (Hex)	(Hex)

1111b	F	F0–FF

1110b	E	E0–EF

1101b	D	D0–DF

1100b	C	C0–CF

1011b	B	B0–BF

1010b	A	A0–AF

1001b	9	90–9F

1000b	8	80–8F

0111b	7	70–7F

0110b	6	60–6F

0101b	5	50–5F

0100b	4	40–4F

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Table 3. Working Register Groups (Continued)

Register Pointer	Working Register	Actual Registers
(FDh) High Nibble	Group (Hex)	(Hex)

0011b	3	30–3F

0010b	2	20–2F

0001b	1	10–1F

0000b	0	00–0F

0	1	1	1	0	0	0	0	Register Pointer (FDh), Standard Register File

1	1	0	1	1	1	1	1	INC R6 (instruction, short format)

0	1	1	1	0	1	1	0	Actual register address (76h)

Figure 4. Working Register Addressing Examples

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