ZILOG Z86C2116PSC, Z86C2116VSC, Z86C2112PEC, Z86C2112PSC, Z86C2112VEC Datasheet

Z86C21 MCU

WITH 8K ROM

PRODUCT S PECIFICA TION

	Z86C21
	8K ROM Z8® CMOS
	MICROCONTROLLER
FEATURES
■ 8-Bit CMOS MCU with 8 Kbytes of ROM	■ Full-Duplex UART
■ 256 Byte Register File	■ All Digital Inputs are TTL Levels
- 236 Bytes of General-Purpose RAM
- 16 Bytes Control/Status Registers	■ Auto Latches
- 4 Bytes for Ports
	■ RAM and ROM Protect

■40-Pin DIP, 44-Pin PLCC or 44-Pin QFP Package

		■	Two Programmable 8-Bit Counter/Timers each with
■	4.5V to 5.5V Operating Range		6-Bit Programmable Prescaler.
■	Low Power Consumption: 220 mW (max) @ 16 MHz	■	Six Vectored, Priority Interrupts from Eight Different
			Sources

■Fast instruction pointer: 1.0 μs @ 12 MHz

■ Clock Speeds: 12 and 16 MHz

■Two Standby Modes: STOP and HALT

	■ On-Chip Oscillator that Accepts a Crystal, Ceramic
■ 32 Input/Output Lines	Resonator, LC, or External Clock Drive.

GENERAL DESCRIPTION

The Z86C21 microcontroller is a member of the Z8 singlechip microcontroller family with 8 Kbytes of ROM and 236 bytes of RAM. The device is packaged in a 40-pin DIP, 44-pin PLCC, or a 44-pin QFP with a ROMless pin option available on the 44-pin versions only. With the ROM/ ROMless feature selectively, the Z86C21 offers both external memory and preprogrammed ROM, making it wellsuited for high-volume applications or where code flexibility is required.

Zilog’s CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption.

The Z86C21 architecture is characterized by Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications.

For applications demanding powerful I/O capabilities, the Z86C21 provides 32 pins dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are three basic address spaces available to support this configuration: Program Memory, Data Memory, and 236 general-pur- pose registers.

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Z86C21 MCU WITH 8K ROM

GENERAL DESCRIPTION (Continued)

To unburden the program from coping with the real-time tasks, such as counting/timing and serial data communication, the Z86C21 offers two on-chip counter/timers with a large number of user selectable modes, and an on-board UART.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection	Circuit	Device
Power	VCC	VDD
Ground	GND	VSS

Output Input

Port 3

UART

Counter/

Timers

(2)

Interrupt

Control

Port 2

I/O

(Bit Programmable)

Vcc GND

ALU

FLAGS

Register

Pointer

Register File

256 x 8-Bit

Port 0

4 4

Address or I/O (Nibble Programmable)

XTAL /AS /DS R//W /RESET

Machine Timing and

Instruction Control

Prg. Memory

8192 x 8-Bit

Program

Counter

Port 1

8

Address/Data or I/O (Byte Programmable)

Figure 1. Z86C21 Functional Block Diagram

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Z86C21 MCU

WITH 8K ROM

PIN DESCRIPTION

VCC		1		40		P36
XTAL2		2		39		P31
		3		38		P27
XTAL1
P37		4		37		P26
				36
P30		5				P25
/RESET		6		35		P24
				34
R//W		7				P23
/DS		8		33		P22
		9		32		P21
/AS			Z86C21
P35		10		31		P20
			DIP
				30
GND		11				P33
P32		12		29		P34
				28
P00		13				P17
P01		14		27		P16
		15		26
P02						P15
P03		16		25		P14
				24
P04		17				P13
P05		18		23		P12
				22
P06		19				P11
P07		20		21		P10

Figure 2. 40-Pin DIP Pin Assignments

	Table 1. 40-Pin DIP Pin Identification
Pin # Symbol Function	Direction		Pin # Symbol Function	Direction

1	VCC	Power Supply	Input
2	XTAL2	Crystal, Oscillator Clock	Output
3	XTAL1	Crystal, Oscillator Clock	Input
4	P37	Port 3, Pin 7	Output
5	P30	Port 3, Pin 0	Input
6	/RESET	Reset	Input
7	R//W	Read/Write	Output
8	/DS	Data Strobe	Output
9	/AS	Address Strobe	Output
10	P35	Port 3, Pin 5	Output

11	GND	Ground	Input
12	P32	Port 3, Pin 2	Input
13-20 P00-P07		Port 0, Pins 0,1,2,3,4,5,6,7	In/Output
21-28 P10-P17		Port 1, Pins 0,1,2,3,4,5,6,7	In/Output
29	P34	Port 3, Pin 4	Output
30	P33	Port 3, Pin 3	Input
31-38 P20-P27		Port 2, Pins 0,1,2,3,4,5,6,7	In/Output
39	P31	Port 3, Pin 1	Input
40	P36	Port 3, Pin 6	Output

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Z86C21 MCU

WITH 8K ROM

PIN DESCRIPTION (Continued)

N/C		P30

6 5

/RESET 7

R//W 8

/DS 9 /AS 10

P35 11

GND 12

P32 13

P00 14

P01 15

P02 16

R//RL 17

18	19
P03	P04

P37	XTAL1	XTAL2	VCC	P36	P31	P27	P26	P25
4	3	2	1	44	43	42	41	40
								39	N/C
								38	P24
								37	P23
								36	P22
		Z86C21						35	P21
								34	P20
		PLCC
								33	P33
								32	P34
								31	P17
								30	P16
								29	P15
20	21	22	23	24	25	26	27	28
P05	P06	P07	P10	P11	P12	P13	P14	N/C

Figure 3. 44-Pin PLCC Pin Assignments

	Table 2. 44-Pin PLCC Pin Identification
Pin # Symbol Function	Direction		Pin # Symbol Function	Direction

1	VCC	Power Supply	Input
2	XTAL2	Crystal, Oscillator Clock	Output
3	XTAL1	Crystal, Oscillator Clock	Input
4	P37	Port 3, Pin 7	Output
5	P30	Port 3, Pin 0	Input
6	N/C	Not Connected	Input
7	/RESET	Reset	Input
8	R//W	Read/Write	Output
9	/DS	Data Strobe	Output
10	/AS	Address Strobe	Output
11	P35	Port 3, Pin 5	Output
12	GND	Ground	Input
13	P32	Port 3, Pin 2	Input

14-16 P00-P02		Port 0, Pins 0,1,2	In/Output
17	R//RL	ROM/ROMless control	Input
18-22 P03-P07		Port 0, Pins 3,4,5,6,7	In/Output
23-27 P10-P14		Port 1, Pins 0,1,2,3,4	In/Output
28	N/C	Not Connected	Input
29-31 P15-P17		Port 1, Pins 5,6,7	In/Output
32	P34	Port 3, Pin 4	Output
33	P33	Port 3, Pin 3	Input
34-38 P20-P24		Port 2, Pins 0,1,2,3,4	In/Output
39	N/C	Not Connected	Input
40-42 P25-P27		Port 2, Pins 5,6,7	In/Output
43	P31	Port 3, Pin 1	Input
44	P36	Port 3, Pin 6	Output

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Z86C21 MCU

WITH 8K ROM

						P30		P37			XTAL1					XTAL2				VCC		GND			P36		P31			P27			P26			P25
	33							32			31					30			29			28		27		26		25			24				23
/RESET				34																															22							GND
R//W				35																															21							P24
/DS				36																															20							P23
/AS				37																															19							P22
P35				38																Z86C21															18							P21
GND				39																															17							P20
P32				40																QFP
P00				41																															16							P33
																																			15							P34
P01				42																															14							P17
P02				43																															13							P16
R//RL				44																															12							P15
	1							2			3					4			5			6		7		8		9			10				11
						P03		P04					P05				P06			P07		GND			P10		P11			P12			P13			P14

Figure 4. 44-Pin QFP Pin Assignments

	Table 3. 44-Pin QFP Pin Identification
Pin # Symbol Function	Direction		Pin # Symbol Function	Direction

1-5	P03-P07	Port 0, Pins 3,4,5,6,7	In/Output
6	GND	Ground	Input
7-14	P10-P17	Port 1, Pins 0 through 7	In/Output
15	P34	Port 3, Pin 4	Output
16	P33	Port 3, Pin 3	Input
17-21	P20-P24	Port 2, Pins 0,1,2,3,4	In/Output
22	GND	Ground	Input
23-25	P25-P27	Port 2, Pins 5,6,7	In/Output
26	P31	Port 3, Pin 1	Input
27	P36	Port 3, Pin 6	Output
28	GND	Ground	Input
29	VCC	Power Supply	Input
30	XTAL2	Crystal, Oscillator Clock	Output

31	XTAL1	Crystal, Oscillator Clock	Input
32	P37	Port 3, Pin 7	Output
33	P30	Port 3, Pin 0	Input
34	/RESET	Reset	Input
35	R//W	Read/Write	Output
36	/DS	Data Strobe	Output
37	/AS	Address Strobe	Output
38	P35	Port 3, Pin 5	Output
39	GND	Ground	Input
40	P32	Port 3, Pin 2	Input
41-43 P00-P02		Port 0, Pins 0,1,2	In/Output
44	R//RL	ROM/ROMless control	Input

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Z86C21 MCU WITH 8K ROM

PIN FUNCTIONS

/ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C91 ROMless Z8. For more details on the ROMless version, refer to the Z86C91 product specification. (Note: When left unconnected or pulled high to VCC, the part functions as a normal Z86C21 ROM version). This pin is only available on the 44-pin versions of the Z86C21.

/DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid.

/AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/ Write.

XTAL1, XTAL2 Crystal 1, Crystal 2 (time-based input and output, respectively). These pins connect a parallel-reso- nant crystal, ceramic resonator, LC, or any external singlephase clock to the on-chip oscillator and buffer.

R//W (output, write Low). The Read/Write signal is Low when the MCU is writing to the external program or data memory.

/RESET (input, active Low). To avoid asynchronous and noisy reset problems, the Z86C21 is equipped with a reset filter of four external clocks (4TpC). If the external /RESET signal is less than 4TpC in duration, no reset occurs.

On the fifth clock after the /RESET is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external /RESET, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC2. When /RESET is deactivated, program execution begins at location 000C (HEX). Power-up reset time must be held Low for 50 ms, or until VCC is stable, whichever is longer.

Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. When used as an I/O port, Port 0 may be placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0 (Data Available and Ready). Handshake signal assignment is dictated by the I/O direction of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble to be under handshake control.

For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 is programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 Mode register.

In ROMless mode, after a hardware reset, Port 0 lines are defined as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine includes reconfiguration to eliminate this extended timing mode (Figure 5).

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Z86C21 MCU

WITH 8K ROM

	4
	Port 0 (I/O)
Z86C21	4
MCU
	Handshake Controls
	/DAV0 and RDY0
	(P32 and P35)

OEN

PAD

Out

TTL Level Shifter

In

Auto Latch

R ≈ 500 KΩ

Figure 5. Port 0 Configuration

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Z86C21 MCU

WITH 8K ROM

PIN FUNCTIONS (Continued)

Port 1 (P17-P10). Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Address (A7-A0) and Data (D7-D0) ports. For Z86C21, these eight I/O lines can be programmed as Input or Output lines or can be configured under software control as an address/data port for interfacing external memory. When used as an I/O port, Port 1 can be placed under handshake control. In this configuration, Port 3 line P33 and P34 are used as the handshake controls RDY1 and /DAV1.

Memory locations greater than 8192 are referenced through Port 1. To interface external memory, Port 1 is programmed

for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 must output the additional lines.

Port 1 can be placed in a high-impedance state along with Port 0, /AS, /DS and R//W, allowing the MCU to share common resource in multiprocessor and DMA applications. Data transfers are controlled by assigning P33 as a Bus Acknowledge input, and P34 as a Bus request output (Figure 6).

	8	Port 1
		(AD7-AD0)
	Z86C21
	MCU
		Handshake Controls
		/DAV1 and RDY1
		(P33 and P34)

OEN

PAD

Out

TTL Level Shifter

In

Auto Latch

R ≈ 500 KΩ

Figure 6. Port 1 Configuration

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Z86C21 MCU WITH 8K ROM

Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bidirectional, CMOS compatible port. Each of these eight I/O lines can be independently programmed as an input or output or globally as an open-drain output. Port 2 is always available for I/O operation. When used as an I/O port, Port 2 may be placed under handshake control. In this

configuration, Port 3 lines P31 and P36 are used as the handshake control lines /DAV2 and RDY2. The handshake signal assignment for Port 3 lines P31 and P36 is dictated by the direction (input or output) assigned to P27 (Figure 7).

Port 2 (I/O)

Z86C21

MCU

Handshake Controls

/DAV2 and RDY2

(P31 and P36)

Open-Drain

OEN

PAD

Out

TTL Level Shifter

In

Auto Latch

R ≈ 500 KΩ

Figure 7. Port 2 Configuration

9

Z86C21 MCU

WITH 8K ROM

PIN FUNCTIONS (Continued)

Port 3 (P37-P30). Port 3 is an 8-bit, CMOS compatible four- fixed-input and four-fixed-output port. These eight I/O lines have four-fixed input (P33-P30) and four fixed output (P37-P34) ports. Port 3, when used as serial I/O, is programmed as serial in and serial out, respectively (Figure 8 and Table 4) Port 3 pins have Auto Latches only.

Port 3 is configured under software control to provide the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); four external interrupt request signals (IRQ3-IRQ0); timer input and output signals (TIN and TOUT), and Data Memory Select (/DM).

UART Operation. Port 3 lines P30 and P37, are be programmed as serial I/O lines for full-duplex serial asynchro-

nous receiver/transmitter operation. The bit rate is controlled by the Counter/Timer0.

The Z86C21 automatically adds a start bit and two stop bits to transmitted data (Figure 9). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters.

Received data must have a start bit, eight data bits and at least one stop bit. If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters generate the IRQ3 interrupt request.

Z86C21

MCU Port 3

(I/O or Control)

PAD

Out

Port 3 Output Configuration	PAD

In

Auto Latch

R ≈ 500 KΩ

Port 3 Input Configuration

Figure 8. Port 3 Configuration

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								Z86C21 MCU
								WITH 8K ROM
			Table 4. Port 3 Pin Assignments
Pin	I/O	CTC1	Int.	P0 HS	P1 HS	P2 HS	UART	Ext
P30	IN		IRQ3				Serial In
P31	IN	TIN	IRQ2	D/R		D/R
P32	IN		IRQ0
P33	IN		IRQ1		D/R
P34	OUT				R/D			DM
P35	OUT			R/D
P36	OUT	TOUT				R/D
P37	OUT						Serial Out
T0			IRQ4
T1			IRQ5

Notes:

HS = Handshake Signals; D = Data Available; R = Ready

Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally driven. This reduces excessive supply current flow in the input buffer when it is not been driven by any source.

Low EMI Option. The Z86C21 is available in a Low EMI option. This option is mask-programmable, to be selected by the customer at the time when the ROM code is submitted. Use of this feature results in:

■The pre-drivers slew rate reduced to 10 ns typical.

■Low EMI output drivers have resistance of 200 Ohms typical.

■Oscillator divide-by-two circuitry is eliminated.

■Internal SCLK/TCLK operation is limited to a maximum of 4 MHz (250 ns cycle time)

Transmitted Data (No Parity)		Received Data (No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST		SP D7 D6 D5 D4 D3 D2 D1 D0 ST
	Start Bit		Start Bit
	Eight Data Bits		Eight Data Bits
	Two Stop Bits		One Stop Bit

Transmitted Data (With Parity)		Received Data (With Parity)
SP SP P D6 D5 D4 D3 D2 D1 D0 ST		SP P D6 D5 D4 D3 D2 D1 D0 ST
	Start Bit		Start Bit
	Seven Data Bits		Seven Data Bits
	Odd Parity		Parity Error Flag
	Two Stop Bits		One Stop Bit

Figure 9. Serial Data Formats

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