SST/U401NL Series
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New Product |
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Vishay Siliconix |
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Monolithic N-Channel JFET Duals |
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SST404NL |
U401NL |
U406NL |
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SST406NL |
U404NL |
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PRODUCT SUMMARY |
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Part Number |
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VGS(off) (V) |
V(BR)GSS Min (V) |
gfs Min (mS) |
IG Typ (pA) |
jVGS1 - VGS2j Max (mV) |
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U401NL |
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-0.5 to -2.5 |
-40 |
1 |
-2 |
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5 |
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SST/U404NL |
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-0.5 to -2.5 |
-40 |
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-2 |
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15 |
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SST/U406NL |
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-0.5 to -2.5 |
-40 |
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-2 |
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40 |
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FEATURES |
BENEFITS |
APPLICATIONS |
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D Anti Latchup Capability |
D External Substrate Bias—Avoids Latchup |
D Wideband Differential Amps |
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D Monolithic Design |
D Tight Differential Match vs. Current |
D High-Speed,Temp-Compensated, |
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D High Slew Rate |
D Improved Op Amp Speed, Settling Time Accuracy |
Single-Ended Input Amps |
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D Low Offset/Drift Voltage |
D Minimum Input Error/Trimming Requirement |
D High-Speed Comparators |
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D Impedance Converters |
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D Low Gate Leakage: 2 pA |
D Insignificant Signal Loss/Error Voltage |
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D Low Noise |
D High System Sensitivity |
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D High CMRR: 102 dB |
D Minimum Error with Large Input Signal |
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DESCRIPTION |
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The SST/U401NL series of high-performance monolithic dual JFETs features extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications. This series has a wide selection of offset and drift specifications with the U401NL featuring a 5-mV offset and 10-mV/_C drift.
Pins 4 and 8 of the SST series, and pin 4 of the U series part
numbers enable the substrate to be connected to a positive polarity, external bias (VDD) to avoid latchup.
The U series, hermetically sealed TO-78 package is available with full military processing. The SST series SO-8 package provides ease of manufacturing, and the symmetrical pinout prevents improper orientation. The SO-8 package is available with tape-and-reel options for compatibility with automatic assembly methods.
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TO-78 |
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Narrow Body SOIC |
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S1 |
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G2 |
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S1 |
1 |
8 |
SUBSTRATE |
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1 |
7 |
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D1 |
2 |
7 |
G2 |
D1 |
2 |
6 |
D2 |
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G1 |
3 |
6 |
D2 |
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SUBSTRATE |
4 |
5 |
S2 |
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3 |
5 |
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G1 |
4 |
S2 |
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Top View |
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CASE, SUBSTRATE |
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Marking Codes: |
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Top View |
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SST404NL - 404NL |
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U401NL |
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SST406NL - 406NL |
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U404NL |
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U406NL |
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ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Lead Temperature (1/16” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C
Storage Temperature : U Prefix . . . . . . . . . . . . . . . . . . . . . -65 to 200_C SST Prefix . . . . . . . . . . . . . . . . . . . -55 to 150_C
For applications information see AN106.
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C
Power Dissipation : Per Sidea . . . . . . . . . . . . . . . . . . . . . . . . 300 mW Totalb . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Notes
a.Derate 2.4 mW/_C above 25_C
b.Derate 4 mW/_C above 25_C
Document Number: 72055 |
www.vishay.com |
S-22448—Rev. A, 17-Feb-03 |
7-1 |
SST/U401NL Series
Vishay Siliconix |
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New Product |
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SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED) |
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Limits |
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U401NL |
SST/U404NL |
SST/U406NL |
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Typa |
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Parameter |
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Symbol |
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Test Conditions |
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Min |
Max |
Min |
Max |
Min |
Max |
Unit |
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Static |
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Gate-Source |
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V(BR)GSS |
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IG = -1 mA, VDS = 0 V |
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-58 |
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-40 |
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-40 |
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-40 |
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Breakdown Voltage |
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V(BR)G1 - G2 |
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IG = "1 mA, VDS = 0 V, VGS = 0 V |
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"45 |
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"30 |
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"30 |
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"30 |
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V |
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Gate-Source |
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VGS(off) |
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VDS = 15 V, ID = 1 nA |
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-1.5 |
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-0.5 |
-2.5 |
-0.5 |
-2.5 |
-0.5 |
-2.5 |
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Cutoff Voltage |
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Saturation |
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IDSS |
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VDS = 10 V, VGS = 0 V |
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3.5 |
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0.5 |
10 |
0.5 |
10 |
0.5 |
10 |
mA |
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Drain Currentb |
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Gate Reverse Current |
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IGSS |
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VGS = -30 V, VDS = 0 V |
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-2 |
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-25 |
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-25 |
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-25 |
pA |
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TA = 125_C |
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-1 |
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nA |
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Gate Operating |
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IG |
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VDG = 15 V, ID = 200 mA |
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-2 |
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-15 |
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-15 |
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-15 |
pA |
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Current |
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-0.8 |
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-10 |
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-10 |
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-10 |
nA |
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TA = 125 C |
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Drain-Source |
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rDS(on) |
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VGS = 0 V, ID = 0.1 mA |
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250 |
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W |
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On-Resistance |
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Gate-Source Voltage |
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VGS |
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VDG = 15 V, ID = 200 mA |
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-1 |
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-2.3 |
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-2.3 |
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-2.3 |
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Gate-Source |
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VGS(F) |
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IG = 1 mA , VDS = 0 V |
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0.7 |
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Forward Voltage |
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Dynamic |
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Common-Source |
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gfs |
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1.5 |
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1 |
2 |
1 |
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mS |
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Forward |
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VDS = 15 V, ID = 200 mA |
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Transconductance |
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f = 1 kHz |
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Common-Source |
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gos |
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1.3 |
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2 |
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mS |
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Output Conductance |
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Common-Source |
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gfs |
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7 |
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7 |
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mS |
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Forward |
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VDS = 10 V, VGS = 0 V |
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Transconductance |
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f = 1 kHz |
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Common-Source |
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gos |
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5 |
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30 |
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30 |
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30 |
mS |
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Output Conductance |
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Common-Source |
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Ciss |
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4 |
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8 |
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8 |
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8 |
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Input Capacitance |
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VDS = 15 V, ID = 200 mA |
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pF |
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Common-Source |
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Crss |
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f = 1 MHz |
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1.5 |
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3 |
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3 |
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3 |
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Reverse Transfer |
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Capacitance |
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Equivalent Input |
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VDS = 15 V, ID = 200 mA |
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nV⁄ |
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en |
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10 |
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20 |
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20 |
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20 |
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Noise Voltage |
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f = 10 Hz (U Only) |
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√Hz |
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Matching |
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Differential |
|VGS1 – VGS2| |
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VDG = 10 V, ID = 200 mA |
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5 |
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15 |
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40 |
mV |
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Gate-Source Voltage |
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Gate-Source Voltage |
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D|V |
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– V |
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VDG = 10 V |
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SST404NL |
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20 |
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GS1 |
GS2 |
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Differential Change |
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ID = 200 mA |
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SST406NL |
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40 |
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mV/_C |
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DT |
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with Temperature |
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TA = -55 to 125_C |
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All U |
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10 |
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25 |
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80 |
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Common Mode |
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CMRR |
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VDG = 10 to 20 V, ID = 200 mA |
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102 |
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95 |
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95 |
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dB |
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Rejection Ratio |
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a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. |
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NNR |
b.Pulse test: PW v300 ms duty cycle v3%.
www.vishay.com |
Document Number: 72055 |
7-2 |
S-22448—Rev. A, 17-Feb-03 |