TFDS6402
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Fast Infrared Transceiver Module Family (FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation
Description
The TFDU6102E, TFDS6402, TFDS6502E, TFDT6502E are a family of low±power infrared transceiver modules compliant to the IrDA physical layer standard for fast infrared data communication, supporting IrDA speeds up to 4.0 Mbit/s (FIR), HP-SIR, Sharp ASK and carrier based remote control modes up to 2 MHz. Integrated within the transceiver modules are a photo PIN diode, an infrared emitter (IRED), and a low±power CMOS control IC to provide a total front±end solution in a single package.
Vishay Telefunken's FIR transceivers are available in four package options, including our Baby Face package (TFDU610xE), the standard setting, once
smallest FIR transceiver available on the market. This wide selection provides flexibility for a variety of applications and space constraints. The transceivers are capable of directly interfacing with a wide variety of I/O devices which perform the modulation/ demodulation function, including National Semiconductor's PC87338, PC87108 and PC87109, SMC's FDC37C669, FDC37N769 and CAM35C44, and Hitachi's SH3. At a minimum, a current±limiting resistor in series with the infrared emitter and a VCC bypass capacitor are the only external components required implementing a complete solution.
Features
Compliant to the IrDA physical layer specification
(Up to 4 Mbit/s),
HP±SIR , Sharp ASK and TV Remote Control
For 3.0 V and 5.0 V Applications
Operates from 2.6 V to 5.5 V within specification, operational down to 2.4 V
Low Power Consumption (3 mA Supply Current)
Power Shutdown Mode (1 A Shutdown Current)
Four Surface Mount Package Options
±Universal (9.7 × 4.7 × 4.0 mm)
±Side View (13.0 × 5.95 × 5.3 mm)
±Top View (13.0 × 7.6 × 5.95 mm)
±Dracula (11.2 × 5.6 × 2.2 mm)
Push-Pull-Receiver Output, grounded in shutdown mode
High Efficiency Emitter
Baby Face (Universal) Package Capable of Surface Mount Soldering to Side and Top View Orientation
Directly Interfaces with Various Super I/O and Controller Devices
Built±In EMI Protection ± No External Shielding Necessary
Few External Components Required
Backward Pin to Pin Compatible to all Vishay Telefunken SIR and FIR Infrared Transceivers
Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements, thus saving costs
Applications
Notebook Computers, Desktop PCs, |
Telecommunication Products |
Palmtop Computers (Win CE, Palm PC), PDAs |
(Cellular Phones, Pagers) |
Digital Still and Video Cameras |
Internet TV Boxes, Video Conferencing Systems |
Printers, Fax Machines, Photocopiers, |
External Infrared Adapters (Dongles) |
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Screen Projectors |
Medical and Industrial Data Collection Devices |
Document Number 82526 |
www.vishay.com |
Rev. B1.6, 02±Nov±00 |
1 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Package Options
TFDU6102E |
TFDS6402 |
TFDS6502E |
TFDT6502E |
Baby Face (Universal) |
Dracula Side View |
Side View |
Top View |
weight 0.20 g |
weight 0.30 g |
weight 0.39 g |
weight 0.39 g |
Ordering Information
Part Number |
Qty / Reel |
Description |
TFDU6102E±TR3 |
1000 pcs |
Oriented in carrier tape for side view surface mounting |
TFDU6102E±TT3 |
1000 pcs |
Oriented in carrier tape for top view surface mounting |
TFDS6402±TR3 |
1000 pcs |
Side View |
TFDS6502E±TR3 |
750 pcs |
Side View |
TFDT6502E±TR3 |
750 pcs |
Top View |
Functional Block Diagram
VCC
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Driver |
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Amplifier |
Comparator |
Rxd |
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AGC |
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IRED Anode |
SD/Mode |
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Logic |
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Txd |
Open Drain Driver |
IRED Cathode |
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GND |
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Figure 1. Functional Block Diagram
www.vishay.com |
Document Number 82526 |
2 |
Rev. B1.6, 02±Nov±00 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Pin Description
Pin Number |
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Function |
Description |
I/O |
Active |
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ªUº and ªTº Optio |
nªSº Option |
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1 |
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8 |
IRED Anode |
IRED anode, to be externally connected |
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to VCC through a current control resistor. |
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This pin is allowed to be supplied from |
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an uncontrolled power supply separated |
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from the controlled VCC supply |
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2 |
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1 |
IRED Cathode |
IRED cathode, internally connected to |
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driver transistor |
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3 |
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7 |
Txd |
Transmit Data Input |
I |
HIGH |
4 |
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2 |
Rxd |
Received Data Output, push-pull CMOS |
O |
LOW |
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driver output capable of driving a stan- |
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dard CMOS or TTL load. No external |
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pull-up or pull-down resistor is required. |
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Pin is floating when |
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device is in shutdown mode |
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5 |
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6 |
SD/Mode |
Shutdown/ Mode |
I |
HIGH |
6 |
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3 |
VCC |
Supply Voltage |
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7 |
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5 |
Mode |
HIGH: High speed mode; |
I |
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LOW: Low speed mode, SIR only |
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(see chapter ªMode Switchingº) |
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8 |
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4 |
GND |
Ground |
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ªUº Option Baby Face (Universal) |
ªSº Option Side View |
ªTº Option Top View |
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and Dracula |
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IRED |
Detector |
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IRED |
Detector |
14885 |
IRED |
Detector |
Figure 2. Pinnings
Document Number 82526 |
www.vishay.com |
Rev. B1.6, 02±Nov±00 |
3 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Absolute Maximum Ratings
Reference point Pin: GND unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters |
Test Conditions |
Symbol |
Min. |
Typ. |
Max. |
Unit |
Supply Voltage Range, |
0 V <VCC2 <6 V |
VCC1 |
± 0.5 |
|
6 |
V |
Transceiver |
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Supply Voltage Range, |
0 V <VCC1 <6 V |
VCC2 |
± 0.5 |
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6 |
V |
Transmitter |
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Input Currents |
For all Pins, Except IRED |
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10 |
mA |
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Anode Pin |
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Output Sinking Current |
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25 |
mA |
Power Dissipation |
See Derating Curve |
PD |
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350 |
mW |
Junction Temperature |
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TJ |
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125 |
°C |
Ambient Temperature |
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Tamb |
±25 |
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+85 |
°C |
Range (Operating) |
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Storage Temperature |
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Tstg |
±25 |
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+85 |
°C |
Range |
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Soldering Temperature |
See Recommended Solder |
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240 |
°C |
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Profile (see Figure 11) |
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Average Output Current |
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IIRED (DC) |
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130 |
mA |
Repetitive Pulsed Output |
<90 μs, ton <20% |
IIRED (RP) |
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600 |
mA |
Current |
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IRED Anode Voltage |
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VIREDA |
± 0.5 |
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6 |
V |
Transmitter Data Input |
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VTxd |
± 0.5 |
|
VCC1 +0.5 |
V |
Voltage |
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Receiver Data Output |
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VRxd |
± 0.5 |
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VCC1 +0.5 |
V |
Voltage |
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Virtual Source Size |
Method: |
d |
2.5 |
2.8 |
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mm |
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(1±1/e) encircled energy |
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Maximum Intensity for |
EN60825, 1997, |
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320 |
mW/sr |
Class 1 Operation of |
unidirectional operation, |
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IEC825±1 or EN60825±1 |
worst case test mode |
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(worst case IrDA FIR |
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pulse pattern) |
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www.vishay.com |
Document Number 82526 |
4 |
Rev. B1.6, 02±Nov±00 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Electrical Characteristics
Tamb = 25_C, VCC = 2.6V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
|
Parameters |
Test Conditions / Pins |
Symbol |
Min. |
Typ. |
Max. |
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Unit |
Transceiver |
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Supply Voltage |
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VCC |
2.6 |
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5.5 |
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V |
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Dynamic Supply Current |
Receive mode only. |
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In transmit mode, add additional 85 mA (typ) for IRED current |
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SD = Low, Ee = 0 klx |
ICC |
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3 |
4.5 |
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mA |
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SD = Low, Ee = 1 klx *) |
ICC |
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3 |
4.5 |
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mA |
Standby Supply Current |
SD = High, |
ISD |
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Mode = Floating, |
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T = 25°C, Ee = 0 klx |
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1 |
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μA |
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T = 25°C, Ee = 1 klx *) |
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1.5 |
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μA |
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SD = High, T = 85°C, |
ISD |
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5 |
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μA |
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Mode = Floating, |
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Not Ambient Light |
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Sensitive |
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Operating Temperature |
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TA |
±25 |
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+85 |
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°C |
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Range |
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Output Voltage Low |
Rload = 2.2 kW, |
VOL |
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0.5 |
0.8 |
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V |
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Cload = 15 pF |
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Output Voltage High |
Rload = 2.2 kW, |
VOH |
VCC±0.5 |
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V |
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Cload = 15 pF |
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Input Voltage Low |
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VIL |
0 |
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0.8 |
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V |
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(Txd, SD/ Mode, Mode) |
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Input Voltage High |
CMOS level **) |
VIH |
0.9 x VCC |
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V |
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(Txd, SD/ Mode, Mode) |
TTL level, VCC ≥ 4.5 V |
VIH |
2.4 |
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V |
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Input Leakage Current |
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IL |
±10 |
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+10 |
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μA |
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(Txd, SD/ Mode) |
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Input Leakage Current, |
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IL |
±80 |
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+80 |
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μA |
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Mode |
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Input Capacitance |
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CI |
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5 |
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pF |
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*) |
Standard Illuminant A |
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**) |
The typical threshold level is between 0.5 x VCC/2 (VCC = 3 V) and 0.4 x VCC (VCC = 5.5 V) . |
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It is recommended to use the specified min/ max values to avoid increased operating current. |
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Document Number 82526 |
www.vishay.com |
Rev. B1.6, 02±Nov±00 |
5 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Optoelectronic Characteristics
Tamb = 25_C, VCC = 2.6 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Parameters |
Test Conditions |
Symbol |
Min. |
Typ. |
Max. |
Unit |
Receiver |
|
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Minimum Detection |
TFDS6502E/ TFDT6502E |
Ee |
|
20 |
35 |
mW/m2 |
Threshold Irradiance, |
9.6 kbit/s to 115.2 kbit/s |
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SIR Mode |
l = 850 nm to 900 nm |
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TFDU6102E, TFDS6402 |
Ee |
|
25 |
40 |
mW/m2 |
|
9.6 kbit/s to 115.2 kbit/s |
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l = 850 nm to 900 nm |
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Minimum Detection |
TFDS6502E/ TFDT6502E |
Ee |
|
50 |
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mW/m2 |
Threshold Irradiance, |
1.152 Mbit/s |
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MIR Mode |
l = 850 nm to 900 nm |
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TFDU6102E, TFDS6402 |
Ee |
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65 |
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mW/m2 |
|
1.152 Mbit/s |
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l = 850 nm to 900 nm |
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Minimum Detection |
TFDS6502E/ TFDT6502E |
Ee |
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65 |
100 |
mW/m2 |
Threshold Irradiance, |
4.0 Mbit/s |
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FIR Mode |
l = 850 nm to 900 nm |
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TFDU6102E, TFDS6402 |
Ee |
|
85 |
100 |
mW/m2 |
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4.0 Mbit/s |
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l = 850 nm to 900 nm |
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Maximum Detection |
l = 850 nm to 900 nm |
Ee |
5 |
10 |
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kW/m2 |
Threshold Irradiance |
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Logic LOW Receiver |
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Ee |
4 |
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mW/m2 |
Input Irradiance |
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Rise Time of Output |
10% to 90%, @2.2 kΩ, 15 pF |
tr (Rxd) |
10 |
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40 |
ns |
Signal±±,,,,klll |
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Fall Time of Output |
90% to 10%, @2.2 kΩ, 15 pF |
tf (Rxd) |
10 |
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40 |
ns |
Signal |
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Rxd Pulse Width of |
Input pulse length 20 μs, 9.6 kbit/s |
tPW |
1.2 |
10 |
20 |
μs |
Output Signal, 50% |
Input pulse length 1.41 ms, |
tPW |
1.2 |
|
1/2 bit |
μs |
SIR Mode |
115.2 kbit/s |
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length |
|
Rxd Pulse Width of |
Input pulse length 217 ns, |
tPW |
110 |
|
260 |
ns |
Output Signal, 50% |
1.152 Mbit/s |
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MIR Mode |
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Rxd Pulse Width of |
Input pulse length 125 ns, 4.0 Mbit/s |
tPW |
100 |
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160 |
ns |
Output Signal, 50% |
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Input pulse length 250 ns, 4.0 Mbit/s |
tPW |
200 |
|
290 |
ns |
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FIR Mode |
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Stochastic Jitter, |
Input Irradiance = 100 mW/m2, |
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±10 |
|
ns |
Leading Edge, |
4.0 Mbit/s |
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FIR Mode |
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Latency |
|
tL |
|
120 |
300 |
μs |
www.vishay.com |
Document Number 82526 |
6 |
Rev. B1.6, 02±Nov±00 |
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