UCC5950
10-Bit Serial D/A Converter
FEATURES
∙10 Bit Resolution
∙1.1μs Output Rise Time
∙2.5μs Settling Time to 1%
∙Single +5V Supply
∙Monotonic
∙Low Power Sleep Mode
∙Three-wire Serial Interface
∙20MHz Data Rate
∙8 Pin SOIC and DIL Package
DESCRIPTION
The UCC5950 is a self-contained, microprocessor-compatible 10-bit D/A converter. It contains all of the functions required to take data directly from a threewire serial data bus and convert it to a precise voltage, including: an input shift register, data latches, a precision voltage reference, a precision 10-bit digital to analog converter, and an output buffer amplifier.
The serial data interface is capable of clock frequencies as high as 20MHz, allowing update rates as high as two words per microsecond. The UCC5950 accepts commands encoded as 2’s-complement binary.
The data converter in the UCC5950 is inherently monotonic, making this part ideal for use in closed-loop servo control systems as well as open-loop data conversion. The UCC5950 uses a unique segmented data converter which offers differential linearity better than 1 LSB, integral linearity better than 2 LSB, and fast conversion.
BLOCK DIAGRAM
UDG-95034 |
2/95 |
UCC5950
ABSOLUTE MAXIMUM RATINGS
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Input Voltage, Any Input . . . . . . . . . . . . . . . . –0.3V to VDD+0.3V Output Current, Any Output . . . . . . . . . . . . . . . . . . . . . . . . ±5mA
Operating Temperature . . . . . . . . . . . . . . . . . . −55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
All voltages with respect to GND. All currents are positive into, negative out of, the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
CONNECTION DIAGRAM
DIL-8, SOIC-8 (Top View) N or J, D Package
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for 4.5V < VDD < 5.5V, REFOUT Load < 100pF, DACOUT Load < 100pF, 0°C < TA < +70°C, and TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN. |
TYP. |
MAX. |
UNITS |
OVERALL SECTION |
|
|
|
|
|
Supply Current |
SLEEP = 0V |
|
1.5 |
5 |
mA |
Supply Current |
SLEEP = 5V |
|
0.1 |
10 |
μA |
REFERENCE SECTION |
|
|
|
|
|
REFOUT Output Voltage |
|
2.10 |
2.15 |
2.20 |
V |
REFOUT Change with VDD |
4.5V < VDD < 5.5V |
|
1 |
10 |
mV |
REFOUT Change with Load |
–1mA < IREFOUT < 1mA |
|
1 |
10 |
mV |
D/A SECTION |
|
|
|
|
|
Integral Nonlinearity |
(Note 1) |
|
|
2 |
LSB |
Differential Nonlinearity |
|
|
|
1 |
LSB |
Full Scale Difference from 1.4924 x REF |
|
–8 |
|
8 |
LSB |
Zero Scale Difference from 0.5089 x REF |
|
–8 |
|
8 |
LSB |
DACOUT Full Scale Rise/Fall Time |
From 10% to 90% of swing (Note 4) |
|
0.7 |
1.1 |
μs |
DACOUT Full Scale Settling Time (TS) |
(Note 2, 3, 4) |
|
1.4 |
2.5 |
μs |
DACOUT Change with VDD |
4.5V < VDD < 5.5V |
|
1.5 |
10 |
mV |
DACOUT Change with Load |
–1mA < IDACOUT < 1mA |
|
1.2 |
10 |
mV |
LOGIC SECTION |
|
|
|
|
|
Logic Input Threshold |
|
1.5 |
2.5 |
3.5 |
V |
Logic Input Current |
0V < VIN < VDD |
|
|
5 |
μA |
Logic Input Capacitance |
(Note 4) |
|
2.7 |
10 |
pF |
SLOD Setup Time to SCLK low (TSLS) |
(Note 4) |
50 |
|
|
ns |
SLOD Hold Time from SCLK high (TSLH) |
From 10TH SCLK high (Note 4) |
50 |
|
|
ns |
SDIO Setup Time to SCLK high (TDS) |
(Note 4) |
15 |
|
|
ns |
SDIO Hold Time from SCLK high (TDH) |
(Note 4) |
7 |
|
|
ns |
Note 1: Integral nonlinearity is defined as the worst deviation of the converter output from the best-fit straight line through all converter output codes.
Note 2: From 10TH Rising Edge of SCLK. Note 3: Settling time is to 1% of final value.
Note 4: Guaranteed by design. Not 100% tested in production.
2
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