Sharp LH52256CT-70LL, LH52256CN-70LL, LH52256CH-70LL, LH52256CD-70LL, LH52256CHT-70LL Datasheet

LH52256C/CH CMOS 256K (32K × 8) Static RAM

FEATURES

∙32,768 × 8 bit organization

∙Access time: 70 ns (MAX.)

∙Supply current:

Operating: 45 mA (MAX.)

10 mA (MAX.) (tRC, tWC = 1 μs)

Standby: 40 μA (MAX.)

∙Data retention current: 1.0 μA (MAX.) (VCCDR = 3 V, TA = 25°C)

∙Wide operating voltage range:

4.5V ± 5.5 V

∙Operating temperature:

Commerical temperature 0°C to +70°C Industrial temperature -40° to +85°C

∙Fully-static operation

∙Three-state outputs

∙Not designed or rated as radiation hardened

∙Package:

28-pin, 600-mil DIP

28-pin, 450-mil SOP

28-pin, 300-mil SK-DIP

28-pin, 8 × 3 mm2 TSOP (Type I)

∙ N-type bulk silicon

DESCRIPTION

The LH52256C is a Static RAM organized as 32,768 × 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology.

PIN CONNECTIONS

28-PIN DIP																						TOP VIEW
28-PIN SK-DIP
28-PIN SOP
								A14							1		28				VCC
								A12					2				27
																					WE
								A7						3			26				A13
								A6							4		25				A8
								A5							5		24				A9
								A4							6		23			A11
								A3							7		22				OE
								A2					8				21				A10
								A1							9		20
																				CE
								A0					10				19			I/O8
								I/O1									18			I/O7
															11
								I/O2							12		17			I/O6
								I/O3								13	16			I/O5
								GND							14		15			I/O4						52256C-1
								Figure 1. Pin Connections
28-PIN TSOP (Type I)
																			28
		OE				1																			A10
		A11						2											27
																									CE
		A9				3													26						I/O8
		A8					4												25						I/O7
	A13							5											24						I/O6
WE								6											23						I/O5
VCC								7											22						I/O4
	A14							8											21						GND
	A12							9											20						I/O3
		A7						10											19						I/O2
		A6						11											18						I/O1
		A5						12											17						A0
		A4						13											16						A1
		A3						14											15						A2

NOTE: Reverse bend available on request.

52256C-8

Figure 2. TSOP (Type I) Pin Connections

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LH52256C/CH							CMOS 256K (32K × 8) Static RAM
A8	25
A14	1
A13	26
A12	2	ROW	MEMORY
A7	3			ARRAY				28 VCC
		DECORDER
A6	4		(512 x 512)					14 GND
A5	5
A4	6
A3	7							11	I/O1
						8		12	I/O2
			COLUMN I/O					13 I/O3
				CIRCUIT			OUTPUT	15	I/O4
				COLUMN		8	BUFFERS	16 I/O5
			DECODER					17 I/O6
								18	I/O7
								19	I/O8
							INPUT
							DATA
							CONTROL
WE 27
OE 22
CE	20
		10	9	8	21 24	23
		A0 A1 A2 A10 A9 A11
									52256C-2

Figure 3. LH52256C Block Diagram

PIN DESCRIPTION

SIGNAL	PIN NAME	SIGNAL	PIN NAME
A0 - A14	Address inputs	I/O1 - I/O8	Data inputs and outputs
CE	Chip enable	VCC	Power supply
WE	Write enable	GND	Ground
OE	Output enable

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CMOS 256K (32K ´ 8) Static RAM LH52256C/CH

TRUTH TABLE

CE

WE

OE

MODE

I/O1 - I/O8

SUPPLY CURRENT

NOTE

H	X	X	Standby	High impedance	Standby (ISB)	1
L	H	L	Read	Data output	Active (ICC)	1
L	H	H	Output disable	High impedance	Active (ICC)	1
L	L	X	Write	Data input	Active (ICC)	1
NOTE:

1. X = Don’t care, L = Low, H = High

ABSOLUTE MAXIMUM RATINGS

PARAMETER	SYMBOL	RATING	UNIT	NOTE
Supply voltage	VCC	–0.5 to +7.0	V	1
Input voltage	VIN	–0.5 to VCC + 0.5	V	1, 2
Operating temperature	TOPR	0 to +70	°C	¾
Storage temperature	TSTG	–65 to +150	°C	¾

NOTES:

1.The maximum applicable voltage on any pin with respect to GND.

2.Undershoot of -3.0 V is allowed width of pulse below 50 ns.

RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C)

PARAMETER	SYMBOL	MIN.	TYP.	MAX.	UNIT	NOTE
Supply voltage	VCC	4.5	5.0	5.5	V	¾
Input voltage	VIH	2.2	¾	VCC + 0.5	V	¾
	VIL	–0.5	¾	0.8	V	1

NOTE:

1. Undershoot of -3.0 V is allowed width of pulse below 50 ns.

3

LH52256C/CH	CMOS 256K (32K ´ 8) Static RAM

DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)

PARAMETER

SYMBOL

	Input leakage	ILI
	current
	Output leakage	ILO
	current
	Operating supply	ICC
	current
		ICC1
	Standby current	ISB
		ISB1
	Output voltage	VOL
		VOH
	NOTE:

CONDITIONS

VIN = 0 V to VCC

CE = VIH or OE = VIH

VI/O = 0 V to VCC

Minimum cycle, VIN = VIL or VIH II/O = 0 mA, CE = VIL

tRC, tWC = 1 ms, VIN = VIL or VIH, II/O = 0 mA, CE = VIL

CE ³ VCC – 0.2 V

CE = VIH

IOL = 2.1 mA

IOH = -1.0 mA

MIN.	TYP.	MAX.	UNIT
–1.0	¾	1.0	mA
–1.0	¾	1.0	mA
¾	25	45.0
			mA
¾	¾	10.0
¾	0.6	40.0	mA
¾	¾	3.0	mA
¾	¾	0.4	V
	¾	¾
2.4

Typical values at VCC = 5.0 V, TA = 25°C

AC ELECTRICAL CHARACTERISTICS

AC Test Conditions

PARAMETER

MODE

NOTE

Input pulse level	0.6 V to 2.4 V	¾
Input rise and fall time	10 ns	¾
Input and output timing Ref. level	1.5 V	¾
Output load	1 TTL + CL (100 pF)	1

NOTE:

1. Including scope and jig capacitance.

READ CYCLE (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)

PARAMETER	SYMBOL	MIN.	MAX.	UNIT	NOTE
Read cycle time	tRC	70	¾	ns	¾
Address access time	tAA	¾	70	ns	¾
CE access time	tACE	¾	70	ns	¾
Output enable to output valid	tOE	¾	35	ns	¾
Output hold from address change	tOH	10	¾	ns	¾
CE Low to output active	tLZ	10	¾	ns	1
OE Low to output active	tOLZ	5	¾	ns	1
CE High to output in High impedance	tHZ	0	30	ns	1
OE High to output in High impedance	tOHZ	0	30	ns	1

NOTES:

1.Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load.

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