Sharp LH28F160BGHR-TTL12, LH28F160BGHR-TTL10, LH28F160BGHR-BTL10, LH28F160BGHE-TTL12, LH28F160BGHE-TTL10 Datasheet

	LH28F160BG-TL/BGH-TL
LH28F160BG-TL/BGH-TL	Flash Memories
	16 M-bit (1 MB x 16) Smart 3

DESCRIPTION

The LH28F160BG-TL/BGH-TL flash memories with

• Enhanced automated suspend options

Smart 3 technology are high-density, low-cost,

– Word write suspend to read

nonvolatile, read/write storage solution for a wide

– Block erase suspend to word write

range of applications. The LH28F160BG-TL/

– Block erase suspend to read

BGH-TL can operate at VCC and VPP = 2.7 V.

• SRAM-compatible write interface

Their low voltage operation capability realizes

• Optimized array blocking architecture

longer battery life and suits for cellular phone

– Two 4 k-word boot blocks

application. Their boot, parameter and main-blocked

– Six 4 k-word parameter blocks

architecture, flexible voltage and enhanced cycling

– Thirty-one 32 k-word main blocks

capability provide for highly flexible component

Y

– Top or bottom boot location

suitable for portable terminals and personal

• Enhanced cycling capability

computers. Their enhanced suspend capabilities

– 100 000 block erase cycles

provide for an ideal solution for code + data storage

R

• Low power management

applications. For secure code storage applications,

– Deep power-down mode

such as networking, where code is either directly

– Automatic power saving mode decreases ICC

A

executed out of flash or downloaded to DRAM, the

in static mode

LH28F160BG-TL/BGH-TL offer two levels of

• Automated word write and block erase

protection : absolute protection with VPP at GND,

–

NCommand user interface

selective hardware boot block locking. These

I

– Status register

alternatives give designers ultimate control of their

• ETOXTM V nonvolatile flash technology

code security needs.

• Packages

M

– 48-pin TSOP Type I (TSOP048-P-1220)

FEATURES

Normal bend/Reverse bend

I

• Smart 3 technology

L

– 60-ball CSP (FBGA060/048-P-0811)

– 2.7 to 3.6 V VCC

– 2.7 to 3.6 V or 12 V VPP

ETOX is a trademark of Intel Corporation.

• High performance read access time

LH28F160BG-TL10/BGH-TL10

– 100 ns (2.7 to 3.6 V) E

LH28F160BG-TL12/BGH-TL12

– 120 ns (2.7 to 3.6 V)

R

COMPARISON TABLE

P

VERSIONS

BIT CONFIGURATION

OPERATING TEMPERATURE

LH28F160BG-TL

1 MB x 16

0 to +70°C

LH28F160BGH-TL

1 MB x 16

–25 to +85°C

LH28F160BV-TL

2 MB x 8/1 MB x 16

0 to +70°C

LH28F160BVH-TL

2 MB x 8/1 MB x 16

–40 to +85°C

Refer to the datasheet of LH28F160BV-TL/BVH-TL.

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

- 1 -

LH28F160BG-TL/BGH-TL

PIN CONNECTIONS

48-PIN TSOP (Type I)

TOP VIEW

A15

A16

1

48

A14

NC

2

47

A13

GND

3

46

A12

DQ15

4

45

A11

DQ7

5

44

A10

DQ14

6

43

A9

DQ6

7

42

A8

DQ13

8

41

NC

DQ5

9

40

Y

RY/BY#

DQ12

10

39

WE#

DQ4

11

38

RP#

VCC

12

37

VPP

DQ11

13

36

R

WP#

DQ3

14

35

A19

DQ10

15

34

A18

DQ2

16

33

A17

17

32

DQ9

A7

DQ1

18

31

A

A6

19

30

DQ8

A5

DQ0

20

29

A4

OE#

21

28

A3

GND

22

27

A2

N

CE#

23

26

A1

A0

24

25

(TSOP048-P-1220)

NOTE :

I

M

Reverse bend available on request.

60-BALL CSP

I

1

2

3

4

5

6

7

8

9

10

11

12

A

NC

NC

NC

A14

A13

A15

A16

GND

NC

NC

NC

NC

E

A11

A10

A12

DQ15

DQ14

DQ7

B

C

L A8

NC

A9

DQ6

DQ5

DQ13

D

WE#

RP#

RY/BY#

DQ12

VCC

DQ4

P

E

WP#

VPP

A19

DQ10

DQ11

DQ3

F

A17

A18

A7

DQ1

DQ2

DQ9

R G

A5

A6

A4

OE#

DQ8

DQ0

H

NC

NC

NC

A2

A3

A1

A0

GND

CE#

NC

NC

NC

(FBGA060/048-P-0811)

- 2 -

LH28F160BG-TL/BGH-TL

BLOCK ORGANIZATION

This product features an asymmetrically-blocked

Parameter Blocks : The boot block architecture

architecture providing system memory integration.

includes parameter blocks to facilitate storage of

Each erase block can be erased independently of

frequently update small parameters that would

the others up to 100 000 times. For the address

normally require an EEPROM. By using software

locations of the blocks, see the memory map in

techniques, the byte-rewrite functionality of

Fig. 1.

EEPROMs can be emulated. Each boot block

component contains six parameter blocks of 4 k

Boot Blocks : The two boot blocks are intended to

words (4 096 words) each. The parameter blocks

replace a dedicated boot PROM in a micro-

are not write-protectable.

Y

processor or microcontroller-based system. The

boot blocks of 4 k words (4 096 words) feature

Main Blocks : The reminder is divided into main

hardware controllable write-protection to protect the

R

blocks for data or code storage. Each 16 M-bit

crucial microprocessor boot code from accidental

device contains thirty-one 32 k words (32 768

modification. The protection of the boot blocks is

words) blocks.

A

controlled using a combination of the VPP, RP# and

WP# pins.

N

BLOCK DIAGRAM

DQ0-DQ15

INPUT

OUTPUT

I

BUFFER

BUFFER

I

IDENTIFIER

I/O

VCC

L

LOGIC

REGISTER

DATA

REGISTER

OE#

OUTPUT

MULTIPLEXER

REGISTERM

CE#

STATUS

COMMAND

WE#

USER

E

INTERFACE

RP#

WP#

R

DATA

31

COMPARATOR

RY/BY#

INPUT

Y

Y GATING

WRITE

A0-A19

DECODER

VPP

BUFFER

STATE

PROGRAM/ERASE

P

BLOCKBOOT0

BLOCKBOOT1

BLOCKPARAMETER0

BLOCKPARAMETER1

BLOCKPARAMETER2

BLOCKPARAMETER3

BLOCKPARAMETER4

BLOCKPARAMETER5

BLOCKMAIN0

BLOCKMAIN1

BLOCKMAIN29

BLOCKMAIN30

MACHINE

VOLTAGE SWITCH

VCC

ADDRESS

X

LATCH

32 k-WORD

GND

DECODER

MAIN BLOCKS

ADDRESS

COUNTER

- 3 -

CE#

RP#

OE#

WE#

WP#

RY/BY#

VPP

VCC

GND

NC

A0-A19

DQ0-DQ15

SYMBOL

PIN DESCRIPTION

LH28F160BG-TL/BGH-TL

		TYPE				NAME AND FUNCTION
		INPUT		ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
				are internally latched during a write cycle.
				DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
		INPUT/		data during memory array, status register and identifier code read cycles. Data pins float
		OUTPUT		to high-impedance when the chip is deselected or outputs are disabled. Data is
				internally latched during a write cycle.
				CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
		INPUT		amplifiers. CE#-high deselects the device and reduces power consumption to standby
				levels.
				RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
				internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
		INPUT							Y
				write operations which provide data protection during power transitions. Exit from deep
				power-down sets the device to read array mode. Block erase or word write with VIH <
				RP# < VHH produce spurious results and should not be attempted.
								R
		INPUT		OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
		INPUT		WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
				latched on the rising edge of the WE# pulse.			A
		INPUT		WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot
				blocks cannot be erased and programmed.
				N
				READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
						I
				performing an internal operation (block erase or word write). RY/BY#-high-impedance
		OUTPUT		indicates that the WSM is ready for new commands, block erase is suspended, and
				word write is inactive, word write is suspended, or the device is in deep power-down
				mode.		M
				BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
					I
		SUPPLY		writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase and
				word write with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce
				spurious results and should not be attempted.
					L
				DEVICE POWER SUPPLY : 2.7 to 3.6 V. Do not float any power pins. With VCC ≤
		SUPPLY		VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid
				VECC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
				and should not be attempted.
		SUPPLY		GROUND : Do not float any ground pins.
			R
	P			NO CONNECT : Lead is not internal connected; recommend to be floated.

- 4 -

The status register indicates when the WSM’s block erase or word write operation is finished.

The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal

1 INTRODUCTION

LH28F160BG-TL/BGH-TL

This datasheet contains LH28F160BG-TL/BGH-TL					A Command User Interface (CUI) serves as the
specifications. Section 1 provides a flash memory					interface between the system processor and
overview. Sections 2, 3, 4 and 5 describe the					internal operation of the device. A valid command
memory organization and functionality. Section 6					sequence written to the CUI initiates device
covers electrical specifications. LH28F160BG-TL/					automation. An internal Write State Machine (WSM)
BGH-TL flash memories documentation also					automatically executes the algorithms and timings
includes ordering information which is referenced in					necessary for block erase and word write
Section 7.					operations.
1.1	New Features				A block erase operation erases one of the device’s
Key enhancements of LH28F160BG-TL/BGH-TL					32 k-word blocks typically within 1.2 second (3.0 V
Smart 3 flash memories are :					VCC and VPP), independent of other blocks. Each
							Y
					block can be independently erased 100 000 times.
• 2.7 V VCC and VPP Write/Erase Operation					Block erase suspend mode allows system software
• Enhanced Suspend Capabilities					to suspend block erase to read data from, or write
• Boot Block Architecture					data to any other block.	R
Note following important differences :					Writing memory data is performed in word
					A
					increments of the device’s 32 k-word blocks
• VPPLK has been lowered to 1.5 V to support					typically within 55 µs, 4 k-word blocks typically
2.7 V block erase and word write operations.					within N60 µs (3.0 V VCC and VPP). Word write
Designs that switch VPP off during read					I
					suspend mode enables the system to read data
operations should make sure that the VPP					from, or write data to any other flash memory array
voltage transitions to GND.					location.
• To take advantage of Smart 3 technology, allow
VPP connection to 2.7 V or 12 V.				M
			I		The boot block is located at either the top or the
					bottom of the address map in order to
1.2	Product Overview				accommodate different micro-processor protect for
The LH28F160BG-TL/BGH-TL are high-performance					boot code location. The hardware-lockable boot
		L			block provides complete code security for the
16 M-bit Smart 3 flash memories organized as
1 024 k-word of 16 bits. The 1 024 k-word of data					kernel code required for system initialization.
is arranged in two 4 k-wordEboot blocks, six 4 k-					Locking and unlocking of the boot block is
word parameter blocks and thirty-one 32 k-word					controlled by WP# and/or RP# (see Section 4.9 for
main blocks which are individually erasable in-					details). Block erase or word write for boot block
system. The memoryRmap is shown in Fig. 1.					must not be carried out by WP# to low and RP# to
	P

VIH.

VPP at 2.7 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and word write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK.

- 5 -

- 6 -

IN IM L

LH28F160BG-TL/BGH-TL

of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase or word write. RY/BY#-High-impedance indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep power-down mode.

The access time is 100 ns or 120 ns (tAVQV) at the VCC supply voltage range of 2.7 to 3.6 V over the temperature range, 0 to +70°C (LH28F160BG-TL)/

–25 to +85°C (LH28F160BGH-TL).

The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 3 mA at 2.7 V VCC.

When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP#

pin is at GND, deep power-down mode is enabled which minimizes power consumptionYand provides

write protection during reset. A reset time (tPHQV) is

required from RP# switching high until outputs are valid. Likewise, the deviceRhas a wake time (tPHEL)

from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status registerAis cleared.

	R	E
P

LH28F160BG-TL/BGH-TL

Top Boot

Bottom Boot

FFFFF

4 k-Word Boot Block

0

FFFFF

32 k-Word Main Block

30

FF000

F8000

FEFFF

4 k-Word Boot Block

1

F7FFF

32 k-Word Main Block

29

FE000

F0000

FDFFF

4 k-Word Parameter Block

0

EFFFF

32 k-Word Main Block

28

FD000

E8000

FCFFF

4 k-Word Parameter Block

1

D7FFF

32 k-Word Main Block

27

FC000

D0000

FBFFF

4 k-Word Parameter Block

2

DFFFF

32 k-Word Main Block

26

FB000

D8000

FAFFF

4 k-Word Parameter Block

3

D7FFF

32 k-Word Main Block

25

FA000

D0000

F9FFF

4 k-Word Parameter Block

4

CFFFF

32 k-Word Main Block

24

F9000

C8000

F8FFF

4 k-Word Parameter Block

5

C7FFF

32 k-Word Main Block

23

F8000

C0000

F7FFF

32 k-Word Main Block

0

BFFFF

32 k-Word Main Block

22

F0000

B8000

EFFFF

32 k-Word Main Block

1

B7FFF

32 k-Word Main Block

21

E8000

B0000

E7FFF

32 k-Word Main Block

2

AFFFF

32 k-Word Main Block

20

E0000

A8000

DFFFF

32 k-Word Main Block

3

A7FFF

32 k-Word Main Block

19

D8000

A0000

D7FFF

32 k-Word Main Block

4

9FFFF

32 k-Word Main BlockY18

D0000

98000

CFFFF

32 k-Word Main Block

5

97FFF

32 k-Word Main Block

17

C8000

90000

C7FFF

8FFFF

A

C0000

32 k-Word Main Block

6

88000

32 k-Word Main Block

16

BFFFF

32 k-Word Main Block

7

87FFF

32 k-Word Main Block

15

B8000

80000

R

B7FFF

32 k-Word Main Block

8

7FFFF

32 k-Word Main Block

14

B0000

78000

AFFFF

77FFF

N

A8000

32 k-Word Main Block

9

70000

32 k-Word Main Block

13

A7FFF

32 k-Word Main Block

10

6FFFF

32 k-Word Main Block

12

A0000

68000

9FFFF

32 k-Word Main Block

11

67FFF

32 k-Word Main Block

11

98000

60000

97FFF

32 k-Word Main Block

12

5FFFF

32 k-Word Main Block

10

90000

58000

8FFFF

32 k-Word Main Block

13

57FFF

32 k-Word Main Block

9

M

88000

50000

87FFF

32 k-Word Main Block

14

4FFFF

32 k-Word Main Block

8

I

80000

48000

7FFFF

32 k-Word Main Block

15

47FFF

32 k-Word Main Block

7

78000

40000

77FFF

32 k-Word Main Block

16

3FFFF

32 k-Word Main Block

6

70000

38000

6FFFF

32 k-Word Main Block

17

37FFF

32 k-Word Main Block

5

68000

30000

67FFF

L

18

2FFFF

32 k-Word Main Block

4

60000

32 k-Word Main Block

28000

5FFFF

32 k-Word Main Block I19

27FFF

32 k-Word Main Block

3

58000

20000

57FFF

32 k-Word Main Block

20

1FFFF

32 k-Word Main Block

2

50000

18000

4FFFF

E

21

17FFF

32 k-Word Main Block

1

48000

32 k-Word Main Block

10000

47FFF

32 k-Word Main Block

22

0FFFF

32 k-Word Main Block

0

40000

08000

3FFFF

32 k-Word Main Block

23

07FFF

4 k-Word Parameter Block

5

38000

07000

37FFF

32 k-Word Main Block

24

06FFF

4 k-Word Parameter Block

4

30000

06000

2FFFF

32 k-Word Main Block

25

05FFF

4 k-Word Parameter Block

3

28000

05000

27FFF

32 k-Word Main Block

26

04FFF

4 k-Word Parameter Block

2

20000

04000

P

03FFF

1FFFF

32 k-Word Main Block

27

4 k-Word Parameter Block

1

18000

03000

17FFF

32 k-Word Main Block

28

02FFF

4 k-Word Parameter Block

0

10000

R

02000

0FFFF

32 k-Word Main Block

29

01FFF

4 k-Word Boot Block

1

08000

01000

07FFF

32 k-Word Main Block

30

00FFF

4 k-Word Boot Block

0

00000

00000

NOTES :

BLOCK CONFIGURATION

VERSIONS

LH28F160BG-TTL

Top Boot

LH28F160BGH-TTL

LH28F160BG-BTL

Bottom Boot

LH28F160BGH-BTL

Fig. 1 Memory Map

- 7 -

				LH28F160BG-TL/BGH-TL
2 PRINCIPLES OF OPERATION
The LH28F160BG-TL/BGH-TL Smart 3 flash			software to suspend a word write to read data from
memories include an on-chip WSM to manage			any other flash memory array location.
block erase and word write functions. It allows for :			2.1	Data Protection
fixed power supplies during block erasure and word
write, and minimal processor overhead with RAM-			Depending on the application, the system designer
like interface timings.			may choose to make the VPP power supply
			switchable (available only when memory block
After initial device power-up or return from deep			erases or word writes are required) or hardwired to
power-down mode (see Table 1 "Bus Operations"),			VPPH1/2. The device accommodates either design
the device defaults to read array mode.			practice and encourages optimization of the
Manipulation of external memory control pins allow			processor-memory interface.			Y
array read, standby and output disable operations.
			When VPP ≤ VPPLK, memory contents cannot be
Status register and identifier codes can be			altered. The CUI, with two-step block erase or word
accessed through the CUI independent of the VPP			write command sequences, provides protection
voltage. High voltage on VPP enables successful					R
			from unwanted operations even when high voltage
block erasure and word writing. All functions			is applied to VPP. All write functions are disabled
associated with altering memory contents—block			when VCC is below the write lockout voltage VLKO
				A
erase, word write, status and identifier codes—are			or when RP# is at VIL. The device’s blocks locking
accessed via the CUI and verified through the			capability provides additional protection from
status register.			inadvertentNcode or data alteration by gating erase
			I
			and word write operations.
Commands are written using standard micro-			3 BUS OPERATION
processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase			The local CPU reads and writes flash memory in-
		M
and word write. The internal algorithms are			system. All bus cycles to or from the flash memory
	I
regulated by the WSM, including pulse repetition,			conform to standard microprocessor bus cycles.
internal verification and margining of data.			3.1	Read
Addresses and data are internally latched during
	L		Information can be read from any block, identifier
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or			codes or status register independent of the VPP
outputs status register data.E			voltage. RP# can be at either VIH or VHH.
Interface software that initiates and polls progress			The first task is to write the appropriate read mode
of block erase andRword write can be stored in any			command (Read Array, Read Identifier Codes or
block. This code is copied to and executed from			Read Status Register) to the CUI. Upon initial
system RAM during flash memory updates. After			device power-up or after exit from deep power-
P			down mode, the device automatically resets to read
successful completion, reads are again possible via
the Read Array command. Block erase suspend			array mode. Five control pins dictate the data flow
allows system software to suspend a block erase to			in and out of the component : CE#, OE#, WE#,
read/write data from/to blocks other than that which			RP# and WP#. CE# and OE# must be driven
is suspended. Word write suspend allows system			active to obtain data at the outputs. CE# is the

- 8 -

device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 9 illustrates read cycle.

3.2 Output Disable

LH28F160BG-TL/BGH-TL

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase or word write modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be

With OE# at a logic-high level (VIH), the device

providing status information instead of array data.

outputs are disabled. Output pins (DQ0-DQ15) are

SHARP’s flash memories allow proper CPU

placed in a high-impedance state.

initialization following a system reset through the

3.3 Standby

use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that resets

CE# at a logic-high level (VIH) places the device in

the system CPU.

Y

standby mode which substantially reduces device

3.5

Read Identifier Codes

power consumption. DQ0-DQ15 outputs are placed

in a high-impedance state independent of OE#. If

R

The read identifier codes operation outputs the

deselected during block erase or word write, the

manufacture code and device code (see Fig. 2).

device continues functioning, and consuming active

Using the

manufacture and device codes, the

power until the operation completes.

A

system CPU can automatically match the device

with its proper algorithms.

3.4 Deep Power-Down

IN

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,

FFFFF

Reserved for

places output drivers in a high-impedance state and

Future Implementation

M

turns off all internal circuits. RP# must be held low

I

00002

for a minimum of 100 ns. Time tPHQV is required

00001

Device Code

after return from power-down until initial memory

00000

Manufacture Code

access outputs are valid. After this wake-up

L

interval, normal operation is restored. The CUI is

reset to read array mode and status register is set

Fig. 2 Device Identifier Code Memory Map

to 80H.

E

3.6

Write

During block erase or word write modes, RP#-low

Writing commands to the CUI enable reading of

will abort the operation.RRY/BY# remains low until

device data and identifier codes. They also control

the reset operation is complete. Memory contents

inspection and clearing of the status register.

being altered are no longer valid; the data may be

P

The Block Erase command requires appropriate

partially erased or written. Time tPHWL is required

after RP# goes to logic-high (VIH) before another

command data and an address within the block to

command can be written.

be erased. The Word Write command requires the

command and address of the location to be written.

- 9 -

LH28F160BG-TL/BGH-TL

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 10 and Fig. 11 illustrate WE# and CE# controlled write operations.

4 COMMAND DEFINITIONS

When the VPP ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled.

Device operations are selected by writing specific commands into the CUI. Table 2 defines these commands.

Table 1 Bus Operations

MODE

NOTE

RP#

CE#

OE#

WE#

ADDRESS

VPP

DQ0-15

RY/BY#

Read

1, 2, 3, 8

VIH or VHH

VIL

VIL

VIH

X

X

DOUT

X

Output Disable

3

VIH or VHH

VIL

VIH

VIH

X

X

High Z

X

Y

Standby

3

VIH or VHH

VIH

X

X

X

X

High Z

X

Deep Power-Down

4

VIL

X

X

X

X

X

High Z

High Z

Read Identifier Codes

8

VIH or VHH

VIL

VIL

VIH

See Fig. 2

X

(NOTE 5)

High Z

R

Write

3, 6, 7, 8

VIH or VHH

VIL

VIH

VIL

X

X

DIN

X

NOTES :

4. RP# at GND±0.2AV ensures the lowest deep power-

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".

When VPP ≤ VPPLK, memory contents can be read, but

down current.

not altered.

5.

See Section 4.2 for read identifier code data.

2. X can be VIL or VIH for control pins and addresses, and

6. VIH < RP# < VHH produce spurious results and should

VPPLK or VPPH1/2 for

VPP. See

Section 6.2.3 "DC

N

I

not be attempted.

CHARACTERISTICS" for VPPLK and VPPH1/2 voltages.

7. Refer to Table 2 for valid DIN during a write operation.

3. RY/BY# is VOL when the WSM is executing internal

8.

Don’t use the timing both OE# and WE# are VIL.

block erase or word write algorithm. It is high-impedance

when the WSM is not busy, in block erase suspend

M

mode (with word write inactive), word writeIsuspend

mode or deep power-down mode.

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LH28F160BG-TL/BGH-TL

Table 2 Command Definitions (NOTE 7)

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE

SECOND BUS CYCLE

REQ’D.

Oper (NOTE 1)

Addr (NOTE 2)

Data (NOTE 3)

Oper (NOTE 1)

Addr (NOTE 2)

Data (NOTE 3)

Read Array/Reset

1

Write

X

FFH

Read Identifier Codes

≥ 2

4

Write

X

90H

Read

IA

ID

Read Status Register

2

Write

X

70H

Read

X

SRD

Clear Status Register

1

Write

X

50H

Block Erase

2

5

Write

BA

20H

Write

BA

D0H

Word Write

2

5, 6

Write

WA

40H or 10H

Write

WA

WD

Block Erase and

1

5

Write

X

B0H

Word Write Suspend

Block Erase and

1

5

Write

X

D0H

Y

Word Write Resume

NOTES :

1. Bus operations are defined in Table 1.

5.

If the block is boot block, WP# must be at VIH or RP#

2. X = Any valid address within the device.

must be at VHH to enable block erase or word write

IA = Identifier code address : see Fig. 2.

R

operations. Attempts to issue a block erase or word write

BA = Address within the block being erased.

to a boot block while WP# is VIH or RP# is VIH.

WA = Address of memory location to be written.

6. Either 40H or 10H is recognized by the WSM as the

3. SRD = Data read from status register. See Table 5 for a

A

word write setup.

description of the status register bits.

7. Commands other than those shown above are reserved

WD = Data to be written at location WA. Data is latched

by SHARP for future device implementations and should

on the rising edge of WE# or CE# (whichever

notNbe used.

goes high first).

I

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read

operations access manufacture and device codes. See

Section 4.2 for read identifier code data.

M

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