Sharp LH28F800BGR-TL85, LH28F800BGR-TL12, LH28F800BGR-BL85, LH28F800BGR-BL12, LH28F800BGHR-TL85 Datasheet

...

0 (0)

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

DESCRIPTION

The LH28F800BG-L/BGH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F800BG-L/BGH-L can operate at VCC = 2.7 V and VPP = 2.7 V. Their low voltage operation capability realizes longer battery life and suits for cellular phone application. Their boot, parameter and main-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for portable terminals and personal computers. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800BG-L/BGH-L offer two levels of protection : absolute protection with VPP at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their code security needs.

FEATURES

•SmartVoltage technology

–2.7 V, 3.3 V or 5 V VCC

–2.7 V, 3.3 V, 5 V or 12 V VPP

•High performance read access time LH28F800BG-L85/BGH-L85

–85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/

100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)

LH28F800BG-L12/BGH-L12

–120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/

150 ns (2.7 to 3.6 V)

•Enhanced automated suspend options

–Word write suspend to read

–Block erase suspend to word write

–Block erase suspend to read

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

•Enhanced data protection features

–Absolute protection with VPP = GND

–Block erase/word write lockout during power transitions

–Boot blocks protection with WP# = VIL

•SRAM-compatible write interface

•Optimized array blocking architecture

–Two 4 k-word boot blocks

–Six 4 k-word parameter blocks

–Fifteen 32 k-word main blocks

–Top or bottom boot location

•Enhanced cycling capability

–100 000 block erase cycles

•Low power management

–Deep power-down mode

–Automatic power saving mode decreases ICC in static mode

•Automated word write and block erase

–Command user interface

–Status register

•ETOXTM V nonvolatile flash technology

•Packages

–48-pin TSOP Type I (TSOP048-P-1220)

Normal bend/Reverse bend

–48-ball CSP (FBGA048-P-0808)

ETOX is a trademark of Intel Corporation.

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

- 1 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

COMPARISON TABLE

VERSIONS	OPERATING	PACKAGE	DC CHARACTERISTICS	WRITE PROTECT FUNCTION
	TEMPERATURE		VCC deep power-down current (MAX.)	FOR BOOT BLOCKS


LH28F800BG-L	0 to +70°C	48-pin TSOP (I)	10 µA	Controlled by
(FOR TSOP, CSP)		48-ball CSP		WP# and RP# pins

LH28F800BGH-L	–40 to +85°C	48-pin TSOP (I)	20 µA	Controlled by
(FOR TSOP, CSP)		48-ball CSP		WP# and RP# pins

LH28F800BG-L 1	0 to +70°C	44-pin SOP	10 µA	Controlled by RP# pin
(FOR SOP)

1 Refer to the datasheet of LH28F800BG-L (FOR SOP).

PIN CONNECTIONS

48-PIN TSOP (Type I)

48-BALL CSP

TOP VIEW

A15

A16

A14

A13

GND

A17

WP#

WE#

A11

A14

A12

DQ15

A11

DQ7

A18

VPP

RP#

A10

A13

A10

DQ14

DQ6

A12

A15

DQ13

RY/BY#

DQ5

DQ12

OE#

DQ1

DQ10

DQ12

DQ6

DQ15

A16

WE#

DQ4

RP#

VCC

GND

DQ8

DQ2

DQ11

VCC

DQ5

DQ14

GND

VPP

DQ11

WP#

DQ3

CE#

DQ0

DQ9

DQ3

DQ4

DQ13

DQ7

RY/BY#

DQ10

A18

DQ2

A17

DQ9

(FBGA048-P-0808)

DQ1

DQ8

DQ0

OE#

GND

CE#

(TSOP048-P-1220)

NOTE :

Reverse bend available on request.

- 2 -

Sharp LH28F800BGR-TL85, LH28F800BGR-TL12, LH28F800BGR-BL85, LH28F800BGR-BL12, LH28F800BGHR-TL85 Datasheet

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

BLOCK ORGANIZATION

This product features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100 000 times. For the address locations of the blocks, see the memory map in

Fig. 1.

Boot Blocks : The two boot blocks are intended to replace a dedicated boot PROM in a microprocessor or microcontroller-based system. The boot blocks of 4 k words (4 096 words) feature hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot blocks is controlled using a combination of the VPP, RP# and WP# pins.

Parameter Blocks : The boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an EEPROM. By using software techniques, the byte-rewrite functionality of EEPROMs can be emulated. Each boot block component contains six parameter blocks of 4 k words (4 096 words) each. The parameter blocks are not write-protectable.

Main Blocks : The reminder is divided into main blocks for data or code storage. Each 8 M-bit device contains fifteen 32 k words (32 768 words) blocks.

BLOCK DIAGRAM

DQ0-DQ15

OUTPUT

INPUT

BUFFER

I/O

VCC

MULTIPLEXER

IDENTIFIER

LOGIC

OUTPUT

DATA REGISTER

COMMAND

CE#

STATUS

WE#

USER

OE#

INTERFACE

RP#

WP#

DATA

COMPARATOR

A0-A18

INPUT

Y GATING

WRITE

RY/BY#

DECODER

BUFFER

STATE

PROGRAM/ERASE

VPP

MACHINE

VOLTAGE SWITCH

ADDRESS

BOOT BLOCK 1 PARAMETER BLOCK 0

PARAMETER BLOCK 1

PARAMETER BLOCK 2

PARAMETER BLOCK 3

PARAMETER BLOCK 4

PARAMETER BLOCK 5

MAIN BLOCK 13 MAIN BLOCK 14

VCC

LATCH

GND

DECODER

32 k-WORD

BLOCKBOOT0

MAIN BLOCKS

ADDRESS

BLOCKMAIN0 BLOCKMAIN1

COUNTER

- 3 -

		LH28F800BG-L/BGH-L (FOR TSOP, CSP)
PIN DESCRIPTION
SYMBOL	TYPE	NAME AND FUNCTION
A0-A18	INPUT	ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
A0-A18	INPUT	are internally latched during a write cycle.
		are internally latched during a write cycle.
		DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
DQ0-DQ15	INPUT/	data during memory array, status register and identifier code read cycles. Data pins float
DQ0-DQ15	OUTPUT	to high-impedance when the chip is deselected or outputs are disabled. Data is
	OUTPUT
		internally latched during a write cycle.
		CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
CE#	INPUT	amplifiers. CE#-high deselects the device and reduces power consumption to standby
		levels.
		RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
		internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
RP#	INPUT/	write operations which provide data protection during power transitions. Exit from deep
RP#	INPUT/	power-down sets the device to read array mode. With RP# = VHH, block erase or word

		write can operate to all blocks without WP# state. Block erase or word write with VIH <
		RP# < VHH produce spurious results and should not be attempted.

OE#	INPUT	OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WE#	INPUT	WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
WE#	INPUT	latched on the rising edge of the WE# pulse.
		latched on the rising edge of the WE# pulse.

WP#	INPUT	WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot
WP#	INPUT	blocks cannot be erased and programmed.
		blocks cannot be erased and programmed.

		READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
		performing an internal operation (block erase or word write). RY/BY#-high indicates that
RY/BY#	OUTPUT	the WSM is ready for new commands, block erase is suspended, and word write is
RY/BY#	OUTPUT	inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#

		is always active and does not float when the chip is deselected or data outputs are
		disabled.

		BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
VPP	SUPPLY	writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase and
VPP	SUPPLY	word write with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce

		spurious results and should not be attempted.

		DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or
		5 V operation. To switch from one voltage to another, ramp VCC down to GND and then
VCC	SUPPLY	ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
VCC	SUPPLY	attempts to the flash memory are inhibited. Device operations at invalid VCC voltage

		(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
		not be attempted.

GND	SUPPLY	GROUND : Do not float any ground pins.

NC		NO CONNECT : Lead is not internal connected; recommend to be floated.

- 4 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800BG-L/BGH-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F800BG-L/ BGH-L flash memories documentation also includes ordering information which is referenced in Section 7.

1.1New Features

Key enhancements of LH28F800BG-L/BGH-L SmartVoltage flash memories are :

•SmartVoltage Technology

•Enhanced Suspend Capabilities

•Boot Block Architecture

Note following important differences :

•VPPLK has been lowered to 1.5 V to support 2.7 V, 3.3 V and 5 V block erase and word write operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND.

•To take advantage of SmartVoltage technology, allow VPP connection to 2.7 V, 3.3 V or 5 V.

1.2Product Overview

The LH28F800BG-L/BGH-L are high-performance 8 M-bit SmartVoltage flash memories organized as 512 k-word of 16 bits. The 512 k-word of data is arranged in two 4 k-word boot blocks, six 4 k-word parameter blocks and fifteen 32 k-word main blocks which are individually erasable in-system. The memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7 V VCC consumes approximately one-fifth the power of 5 V VCC and 3.3 V VCC consumes approximately one-fourth the power of 5 V VCC.

But, 5 V VCC provides the highest read performance. VPP at 2.7 V, 3.3 V and 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and word write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations Offered by SmartVoltage Technology

VCC VOLTAGE	VPP VOLTAGE
2.7 V	2.7 V, 3.3 V, 5 V, 12 V
3.3 V	3.3 V, 5 V, 12 V
5 V	5 V, 12 V

Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations.

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and word write operations.

A block erase operation erases one of the device’s 32 k-word blocks typically within 0.39 second (5 V VCC, 12 V VPP), 4 k-word blocks typically within 0.25 second (5 V VCC, 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times. Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block.

Writing memory data is performed in word increments of the device’s 32 k-word blocks typically within 8.4 µs (5 V VCC, 12 V VPP), 4 k- word blocks typically within 17 µs (5 V VCC, 12 V VPP). Word write suspend mode enables the

- 5 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

system to read data from, or write to any other flash memory array location.

The boot block is located at either the top or the bottom of the address map in order to accommodate different micro-processor protect for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 4.9 for details). Block erase or word write for boot block must not be carried out by WP# to low and RP# to VIH.

The status register indicates when the WSM’s block erase or word write operation is finished.

The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase or word write. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep power-down mode.

The access time is 85 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70°C (LH28F800BG-L)/

–40 to +85°C (LH28F800BGH-L). At 4.5 to 5.5 V VCC, the access time is 90 ns or 120 ns. At lower VCC voltage, the access time is 100 ns or 130 ns (3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).

The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC.

When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.

- 6 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

		Top Boot					Bottom Boot
7FFFF						7FFFF
	4 k-Word Boot Block			0			32 k-Word Main Block	14
7F000					78000

7EFFF	4 k-Word Boot Block			1		77FFF	32 k-Word Main Block	13
7E000					70000

7DFFF	4 k-Word Parameter Block			0		6FFFF	32 k-Word Main Block	12
7D000					68000

7CFFF	4 k-Word Parameter Block			1		67FFF	32 k-Word Main Block	11
7C000					60000

7BFFF	4 k-Word Parameter Block			2		5FFFF	32 k-Word Main Block	10
7B000					58000

7AFFF	4 k-Word Parameter Block			3		57FFF	32 k-Word Main Block	9
7A000					50000

79FFF	4 k-Word Parameter Block			4		4FFFF	32 k-Word Main Block	8
79000					48000

78FFF	4 k-Word Parameter Block			5		47FFF	32 k-Word Main Block	7
78000					40000

77FFF	32 k-Word Main Block			0		3FFFF	32 k-Word Main Block	6
70000					38000

6FFFF	32 k-Word Main Block			1		37FFF	32 k-Word Main Block	5
68000					30000

67FFF	32 k-Word Main Block			2		2FFFF	32 k-Word Main Block	4
60000					28000

5FFFF	32 k-Word Main Block			3		27FFF	32 k-Word Main Block	3
58000					20000

57FFF	32 k-Word Main Block			4		1FFFF	32 k-Word Main Block	2
50000					18000

4FFFF	32 k-Word Main Block			5		17FFF	32 k-Word Main Block	1
48000					10000

47FFF	32 k-Word Main Block			6		0FFFF	32 k-Word Main Block	0
40000					08000

3FFFF	32 k-Word Main Block			7		07FFF	4 k-Word Parameter Block	5
38000					07000

37FFF	32 k-Word Main Block			8		06FFF	4 k-Word Parameter Block	4
30000					06000

2FFFF	32 k-Word Main Block			9		05FFF	4 k-Word Parameter Block	3
28000					05000

27FFF	32 k-Word Main Block			10		04FFF	4 k-Word Parameter Block	2
20000					04000

1FFFF	32 k-Word Main Block			11		03FFF	4 k-Word Parameter Block	1
18000					03000

17FFF	32 k-Word Main Block			12		02FFF	4 k-Word Parameter Block	0
10000					02000

0FFFF	32 k-Word Main Block			13		01FFF	4 k-Word Boot Block	1
08000					01000

07FFF	32 k-Word Main Block			14		00FFF	4 k-Word Boot Block	0
00000					00000

NOTES :
BLOCK CONFIGURATION			VERSIONS
Top Boot			LH28F800BG-TL
			LH28F800BGH-TL

LH28F800BG-BL

Bottom Boot

LH28F800BGH-BL

Fig. 1 Memory Map

- 7 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800BG-L/BGH-L SmartVoltage flash memories include an on-chip WSM to manage block erase and word write functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure and word write, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations.

Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure and word writing. All functions associated with altering memory contents—block erase, word write, status and identifier codes—are accessed via the CUI and verified through the status register.

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase and word write. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data.

Interface software that initiates and polls progress of block erase and word write can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Word write suspend allows system

software to suspend a word write to read data from any other flash memory array location.

2.1Data Protection

Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases or word writes are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface.

When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase or word write command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device’s boot blocks locking capability for WP# provides additional protection from inadvertent code or data alteration by block erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1Read

Information can be read from any block, identifier codes or status register independent of the VPP voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component : CE#, OE#, WE#, RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the

- 8 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 11 illustrates read cycle.

3.2Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ15) are placed in a high-impedance state.

3.3Standby

CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase or word write, the device continues functioning, and consuming active power until the operation completes.

3.4Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase or word write modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.

As with any automated device, it is important to

assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase or word write modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.5Read Identifier Codes Operation

The read identifier codes operation outputs the manufacture code and device code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms.

7FFFF

	Reserved for
	Future Implementation
00002
00001	Device Code
00000	Manufacture Code

Fig. 2 Device Identifier Code Memory Map

3.6Write

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When

VCC = VCC1/2/3/4 and VPP = VPPH1/2/3, the CUI

additionally controls block erasure and word write.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Word Write command requires the command and address of the location to be written.

- 9 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 12 and Fig. 13 illustrate WE# and CE# controlled write operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2/3 on VPP enables successful block erase and word write operations.

Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.

		Table 2		Bus Operations
MODE	NOTE	RP#	CE#		OE#	WE#	ADDRESS	VPP	DQ0-15	RY/BY#
Read	1, 2, 3, 8	VIH or VHH	VIL		VIL	VIH	X	X	DOUT	X

Output Disable	3	VIH or VHH	VIL		VIH	VIH	X	X	High Z	X

Standby	3	VIH or VHH	VIH		X	X	X	X	High Z	X

Deep Power-Down	4	VIL	X		X	X	X	X	High Z	VOH

Read Identifier Codes	8	VIH or VHH	VIL		VIL	VIH	See Fig. 2	X	(NOTE 5)	VOH

Write	3, 6, 7, 8	VIH or VHH	VIL		VIH	VIL	X	X	DIN	X

NOTES :

1.Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP ≤ VPPLK, memory contents can be read, but

not altered.

2.X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.

3.RY/BY# is VOL when the WSM is executing internal block erase or word write algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with word write inactive), word write suspend mode or deep power-down mode.

4.RP# at GND±0.2 V ensures the lowest deep powerdown current.

5.See Section 4.2 for read identifier code data.

6.Command writes involving block erase or word write are reliably executed when VPP = VPPH1/2/3 and VCC = VCC1/2/3/4. Block erase or word write with VIH < RP# < VHH produce spurious results and should not be attempted.

7.Refer to Table 3 for valid DIN during a write operation.

8.Don’t use the timing both OE# and WE# are VIL.

- 10 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

Table 3 Command Definitions (NOTE 7)

COMMAND	BUS CYCLES	NOTE	FIRST BUS CYCLE			SECOND BUS CYCLE
COMMAND	REQ’D.	NOTE	Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)	Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)
	REQ’D.		Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)	Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)
Read Array/Reset	1		Write	X	FFH

Read Identifier Codes	≥ 2	4	Write	X	90H	Read	IA	ID

Read Status Register	2		Write	X	70H	Read	X	SRD

Clear Status Register	1		Write	X	50H

Block Erase	2	5	Write	BA	20H	Write	BA	D0H

Word Write	2	5, 6	Write	WA	40H or 10H	Write	WA	WD

Block Erase and	1	5	Write	X	B0H
Word Write Suspend	1	5	Write	X	B0H
Word Write Suspend

Block Erase and	1	5	Write	X	D0H
Word Write Resume	1	5	Write	X	D0H
Word Write Resume
NOTES :

1.Bus operations are defined in Table 2.

2.X = Any valid address within the device. IA = Identifier code address : see Fig. 2.

BA = Address within the block being erased. WA = Address of memory location to be written.

3.SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).

ID = Data read from identifier codes.

4.Following the Read Identifier Codes command, read operations access manufacture and device codes. See

Section 4.2 for read identifier code data.

5.If the block is boot block, WP# must be at VIH or RP# must be at VHH to enable block erase or word write operations. Attempts to issue a block erase or word write to a boot block while WP# is VIH or RP# is VIH.

6.Either 40H or 10H is recognized by the WSM as the word write setup.

7.Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.

- 11 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

4.1Read Array Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase or word write, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH.

4.2Read Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture and device codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read :

Table 4 Identifier Codes

CODE	ADDRESS	DATA
Manufacture Code	00000H	00B0H

Device Code (Top Boot)	00001H	0060H

Device Code (Bottom Boot)	00001H	0062H

4.3Read Status Register Command

The status register may be read to determine when a block erase or word write is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on

the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH.

4.4Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or word write suspend modes.

4.5Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions.

- 12 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI remains in read status register mode until a new command is issued.

This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase for boot blocks requires that the corresponding if set, that WP# = VIH or RP# = VHH. If block erase is attempted to boot block when the corresponding WP# = VIL or RP# = VIH, SR.1 and SR.5 will be set to "1". Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.6Word Write Command

Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the completion of the word write event by analyzing the RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command.

Reliable word writes can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against word writes. If word write is attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write for boot blocks requires that the corresponding if set, that WP# = VIH or RP# = VHH. If word write is attempted to boot block when the corresponding WP# = VIL or RP# = VIH, SR.1 and SR.4 will be set to "1". Word write operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.7Block Erase Suspend Command

The Block Erase Suspend command allows block erase interruption to read or word write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency.

At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word Write Suspend command (see Section 4.8), a word write operation can also be suspended. During a word write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status.

- 13 -

+ 30 hidden pages