Sharp LH540225U-35, LH540225U-25, LH540225M-35, LH540225M-25, LH540225M-20 Datasheet

LH540215/25

FEATURES

∙Fast Cycle Times: 20/25/35 ns

∙Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs

∙Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal

∙Device Comes Up into One of Two Known Default States at Reset Depending on the State of the EMODE Control Input: Programming is Allowed, but is not Required

∙Internal Memory Array Architecture Based on CMOS Dual-Port SRAM Technology, 512 × 18 or 1024 × 18

∙‘Synchronous’Enable-Plus-Clock Control at Both Input Port and Output Port

∙Independently-Synchronized Operation of Input Port and Output Port

∙Control Inputs Sampled on Rising Clock Edge

∙Most Control Signals Assertive-LOW for Noise Immunity

512 × 18 / 1024 × 18 Synchronous FIFO

∙May be Cascaded for Increased Depth, or Paralleled for Increased Width

∙Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are Programmable

∙In Enhanced Operating Mode, Almost-Full, Half-Full, and Almost-Empty Flags can be Made Completely Synchronous

∙In Enhanced Operating Mode, Duplicate Enables for Interlocked Paralleled FIFO Operation, for 36-Bit Data Width, when Selected and Appropriately Connected

∙In Enhanced Operating Mode, Disabling Three-State Outputs May be Made to Suppress Reading

∙Data Retransmit Function

∙TTL/CMOS-Compatible I/O

∙Space-Saving 68-Pin PLCC Package, and 64-Pin TQFP Package

RS	RESET
	LOGIC
FL/RT			FIFO
WXI/WEN2	EXPANSION	MEMORY ARRAY
WXO/HF		512 x 18/1024 x 18
	LOGIC
RXI/REN2
RXO/EF2			READ
		WRITE
		POINTER	POINTER
WCK	INPUT			OUTPUT	RCK
WEN	PORT			PORT	REN
	CONTROL			CONTROL
WXI/WEN2	LOGIC			LOGIC	RXI/REN2
FF		DEDICATED AND			EF
PAF		PROGRAMMABLE			PAE
WXO/HF		STATUS FLAGS			RXO/EF2
	INPUT			OUTPUT	OE
D0 - D17	PORT
		PROGRAMMABLE		PORT	Q0 - Q17
LD
		REGISTERS
	EMODE
BOLD ITALIC = Enhanced Operating Mode.					540215-1
	Figure 1.	LH540215/25 Block Diagram

BOLD ITALIC = Enhanced Operating Mode

1

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

FUNCTIONAL DESCRIPTION

NOTE: Throughout this data sheet, a BOLD ITALIC type font is used for all references to Enhanced Operating Mode features which do not function in IDT-Compatible Operating Mode; and also for all references to the retransmit facility (which is not an IDT72215B/25B FIFO feature), even though it may be used – subject to some restrictions – in either of these two operating modes. Thus, readers interested only in using the LH540215/25 FIFOs in IDT-Compatible Operating Mode may skip over BOLD ITALIC sections, if they wish.

The LH540215/25 parts are FIFO (First-In, First-Out) memory devices, based on fully-static CMOS dual-port SRAM technology, capable of containing up to 512 or 1024 18-bit words respectively. They can replace two or more byte-wide FIFOs in many applications, for microprocessor- to-microprocessor or microprocessor-to-bus communication. Theirarchitecture supportssynchronousoperation, tied to two independent free-running clocks at the input and output ports respectively. However, these ‘clocks’ also may be aperiodic, asynchronous ‘demand’ signals. Almost all control-input signals and status-output signals are synchronized to these clocks, to simplify system design.

The input and output ports operate altogether independently of each other, unless the FIFO becomes either totally full or else totally empty. Data flow is initiated at a port by the rising edge of its corresponding clock, and is gated by the appropriate edge-sampled enable signals.

The following FIFO status flags monitor the extent to which the internal memory has been filled: Full, AlmostFull, Half-Full, Almost-Empty, and Empty. The Almost-Full and Almost-Empty flag offsets are programmable overthe entire FIFO depth; but, during a reset operation, each of these is initialized to a default offset value of 6310 (LH540215) or 12710 (LH540225) FIFO-memory words, from the respective FIFO boundary. If this default offset value is satisfactory, no further programming is required.

After a reset operation during which the EMODE control input was not asserted (was HIGH), these FIFOs operate in the IDT-Compatible Operating Mode. In this mode, each part is pin-compatible and functionally-compatible with the IDT72215B/25B part of similar depth and speed grade; and the Control Register is not even accessible orvisible to the external-systemlogic which iscontrollingtheFIFO, although it still performs the same control functions.

However, assertion of the EMODE control input during a reset operation leaves Control Register bits 00-05 set, and causes the FIFO to operate in the Enhanced Operating Mode. In essence, asserting EMODE chooses a different default state for the Control Register. The system optionally then may program the Control Register in any desired manner to

BOLD ITALIC = Enhanced Operating Mode

activate or deactivate any or all of the Enhanced-Op- erating-Mode features which it can control, including selectable-clock-edge flag synchronization, and read inhibition when the data outputs are disabled.

Whenever EMODE is being asserted, interlockedoperation paralleling also is available, by appropriate interconnection of the FIFO’s expansion inputs.

The retransmit facility is available during standalone operation, in either IDT-Compatible Operating Mode or Enhanced Operating Mode. (See Tables 1 and 2.) It is inoperative if the FL/RT input signal is grounded. It is not an IDT72215B/25B feature. The Retransmit control signal causes the internal FIFO read-address pointer to be set back to zero, without affecting the internal FIFO write-address pointer. Thus, the Retransmit control signal also provides a mechanism whereby a block of data delimited by the zero physical address and the current write-address-pointer address may be read out repeatedly, an arbitrary number of times.

The only restrictions are that neither the read-ad- dress pointer nor the write-address pointer may ‘wrap around’ during this entire process, and that the retransmit facility is not available during depth-cas- caded operation, either in IDT-Compatible Operating Mode or in Enhanced Operating Mode. (See Tables 1 and 2.) Also, the flags behave differently for a short time after a retransmit operation. Otherwise, the retransmit facility is available during standalone operation, in either IDT-Compatible Operating Mode or Enhanced Operating Mode.

Note that, when FL/RT is being used as RT, RT is an assertive-HIGH signal, rather than assertive-LOW as it is in most other FIFOs having a retransmit facility.

Programming the programmable-flag offsets, the timing synchronization of the various status flags, the optional read-suppression functionality of OE, and the behavior of the pointers which access the offsetvalue registers and the Control Register may be individually controlled by asserting the signal LD, without any reset operation. When LD is being asserted, and writing is being enabled by asserting WEN, some portion of the input bus word D0 – D17 is used at the next rising edge of WCLK to program one or more of the programmable registers on successive write clocks. Likewise, the values programmed into these programmable registers may be read out for verification by asserting LD and REN, with the outputs Q0 – Q17 enabled. Reading out these programmable registers should not be initiated while they are being written into. Table 3 defines the possible modes of operation for loading and reading out the contents of programmable registers.

2

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

In the Enhanced Operating Mode, coordinated operation of two 18-bit FIFOs as one 36-bit FIFO may be ensured by ‘interlocked’ crosscoupling of the statusflag outputs from each FIFO to the expansion inputs of the other one; that is, FF to WXI/WEN2, and EF to

RXI/REN2, in both directions between two paralleled FIFOs. This ‘interlocked’ operation takes effect

automatically, if two paralleled FIFOs are crossconnected in this manner, with the EMODE control input being asserted (LOW). (See Tables 1 and 2, also Figures 27 and 30.) IDT-compatible depth cascading no longer is available when operating in this ‘inter- locked-paralleled’ mode; however, pipelined depth cascading remains available.

68-PIN PLCC							RCLK	REN	LD	OE	RS				EF							TOP VIEW
	D		D	D		V						V	V			V	Q	Q	V	Q
	15		16	17		SS						CC	SS			CC	17	16	SS	15
	9		8	7		6	5	4	3	2	1	68	67	66		65	64	63	62	61
D14	10																			60	VCC
D13	11																			59	Q14
D12	12																			58	Q13
D11	13																			57	VSS
D10	14																			56	Q12
D9	15																			55	Q11
VCC	16																			54	VCC
D8	17																			53	Q10
VSS	18																			52	Q9
D7	19																			51	VSS
D6	20																			50	Q8
D5	21																			49	Q7
																						*
D4	22																			48	EMODE
D3	23																			47	Q6
D2	24																			46	Q5
D1	25																			45	VSS
D0	26		28	29		30	31	32	33	34	35	36	37	38		39	40	41	42	44	Q4
	27																			43
	PAE		FL/RT	WCLK		WEN	WENWXI/	V	PAF	RENRXI/	FF	WXO/HF	RXO/EF		Q	Q	V	Q	Q	V
BOLD ITALIC = Enhanced Operating Mode.							2	CC		2			2	0		1	SS	2	3	CC
* This pin is VCC on IDT pinout; if					pin is simply
		EMODE
biased to VCC, part will behave identical to IDT functionality.																					540215-2

Figure 2. Pin Connections for 68-Pin PLCC Package

BOLD ITALIC = Enhanced Operating Mode

3

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

64-PIN TQFP

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

	D		D			V			RCLK			REN			LD			OE			RS			V			V			EF			Q			Q			V			Q			V
16			17			SS																		CC			SS					17			16				SS		15				CC
64			63		62			61			60			59			58			57			56			55			54			53			52			51			50			49
1																																												48
2																																												47
3																																												46
4																																												45
5																																												44
6																																												43
7																																												42
8																																												41
9																																												40
10																																												39
11																																												38
12																																												37
13																																												36
14																																												35
15																																												34
16																																												33
17			18		19			20			21			22			23			24			25			26			27			28			29			30			31			32
	PAE		FL/RT			WCLK			WEN		2				CC			PAF		2				FF			WXO/HF		2			0			1				SS		2			3
												WXI/WEN			V						RXI/REN									RXO/EF			Q			Q			V			Q			Q

BOLD ITALIC = Enhanced Operating Mode.

*This pin is VCC on IDT pinout; if EMODE pin is simply biased to VCC, part will behave identical to IDT functionality.

TOP VIEW

Q14

Q13

VSS

Q12

Q11

VCC

Q10

Q9

VSS

Q8

Q7

Q6

Q5

VSS

Q4

EMODE *

540215-34

Figure 3. Pin Connections for 64-Pin TQFP Package

SUMMARY OF SIGNALS/PINS

PIN

NAME

PIN

NAME

/WEN2

Write Expansion Input/Write Enable 2

D0 – D17

Data Inputs

WXI

Reset

Full Flag

RS

FF

Enhanced Operating Mode

EMODE

PAF

Programmable Almost-Full Flag

WCLK

Write Clock

WXO/HF

Write Expansion Output/Half-Full Flag

WEN

Write Enable

PAE

Programmable Almost-Empty Flag

RCLK

Read Clock

Empty Flag

EF

2

Read Expansion Output/Empty Flag 2

REN

Read Enable

RXO/

EF

OE

Output Enable

Q0 – Q17

Data Outputs

VCC

LD

Load

Power

First Load/Retransmit

VSS

FL

/RT

Ground

Read Expansion Input/Read Enable 2

RXI

/REN2

BOLD ITALIC = Enhanced Operating Mode

4

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

PIN LIST

SIGNAL NAME																							PLCC PIN NO.	TQFP PIN NO.
																							1	57
								RS
																							2	58
								OE
																							3	59
								LD
																							4	60
							REN
					RCLK																		5	61
							D17																7	63
							D16																8	64
							D15																9	1
							D14																10	2
							D13																11	3
							D12																12	4
							D11																13	5
							D10																14	6
									D9														15	7
									D8														17	8
									D7														19	9
									D6														20	10
									D5														21	11
									D4														22	12
									D3														23	13
									D2														24	14
									D1														25	15
									D0														26	16
																							27	17
							PAE
										RT													28	18
					FT/
					WCLK																		29	19
																							30	20
						WEN
									WEN2														31	21
	WXI/
																							33	23
							PAF
									REN2														34	24
		RXI/
																							35	25
									FF
																							36	26
				WXO/HF
																					2		37	27
			RXO/									EF
								Q0															38	28

SIGNAL NAME					PLCC PIN NO.	TQFP PIN NO.
		Q1			39	29
		Q2			41	31
		Q3			42	32
		Q4			44	34
		Q5			46	36
		Q6			47	37
					48	33
	EMODE
		Q7			49	38
		Q8			50	39
		Q9			52	41
	Q10				53	42
	Q11				55	44
	Q12				56	45
	Q13				58	47
	Q14				59	48
	Q15				61	50
	Q16				63	52
	Q17				64	53
					66	54
		EF
	VSS				6	62
	VCC				16	NC
	VSS				18	NC
	VCC				32	22
	VSS				40	30
	VCC				43	NC
	VSS				45	35
	VSS				51	40
	VCC				54	43
	VSS				57	46
	VCC				60	49
	VSS				62	51
	VCC				65	NC
	VSS				67	55
	VCC				68	56

BOLD ITALIC = Enhanced Operating Mode

5

LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

PIN DESCRIPTIONS

PIN

NAME

PIN

DESCRIPTION

TYPE 1

D0 – D17

Data Inputs

I

Data inputs from an 18-bit bus.

When RS is taken LOW, the FIFO’s internal read and write pointers are set to

address the first physical location of the RAM array; FF, PAF, and HF go HIGH;

and PAE and EF go LOW. The programmable-flag-offset registers and the

RS

Reset

I

Control Register are set to their default values. (But see the description of

EMODE, below.) A reset operation is required before an initial read or write

operation after power-up.

When

EMODE

is tied LOW, the default setting for Control Register bits 00-05

after a reset operation changes to HIGH rather than LOW, thus enabling all

Control-Register-controllable Enhanced Operating Mode features, and

allowing access to the Control Register for reprogramming or readback.

Enhanced

(See Tables 1, 2, and 5.) If this behavior is desired, EMODE may be

grounded; however, Control Register bits 00-05 still may be individually

EMODE

Operating

I

programmed to selectively enable or disable certain of the Enhanced Mode

Mode

features, even though those features associated with interlocked-paralleled

operation always are enabled whenever EMODE is being asserted. (See

Table 2.) Alternatively, EMODE may be tied to VCC, so that the FIFO is

functionally IDT-compatible, and the Control Register is not accessible or

visible, and all of its bits remain LOW. Controlling EMODE dynamically

during system operation is not recommended.

Data is written into the FIFO on a LOW-to-HIGH transition of WCLK, whenever

WEN (Write Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a

WCLK

Write Clock

I

programmable register rather than the internal FIFO memory is written into. In the

Enhanced Operating Mode, WEN2 is ANDed with WEN to produce an

effective internal write-enable signal. 2

When WEN is LOW and LD is HIGH, an 18-bit data word is written into the FIFO

on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO

WEN

Write Enable

I

internal memory continues to hold the previous data. (See Table 3.) Data will not

be written into the FIFO if FF is LOW. In the Enhanced Operating Mode, WEN2

is ANDed with WEN to produce an effective internal write-enable signal. 2

Data is read from the FIFO on a LOW-to-HIGH transition of RCLK whenever REN

(Read Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a

RCLK

Read Clock

I

programmable register rather than the internal FIFO memory is read from. In the

Enhanced Operating Mode, REN2 is ANDed with REN (and whenever

Control Register bit 05 is HIGH, also with OE) to produce an effective

internal read-enable signal. 2

When REN is LOW and LD is HIGH, an 18-bit data word is read from the FIFO on

every LOW-to-HIGH transition of RCLK. When REN is HIGH, and/or also when

EF is LOW, the FIFO’s output register continues to hold the previous data word,

REN

Read Enable

I

whether or not Q0 – Q17 (the data outputs) are enabled. (See Table 3.) In the

Enhanced Operating Mode, REN2 is ANDed with REN (and whenever

Control Register bit 05 is HIGH, also with OE) to produce an effective

internal read-enable signal. 2

When OE is LOW, the FIFO’s data outputs drive the bus to which they are

connected. If OE is HIGH, the FIFO’s outputs are in high-Z (high-impedance)

state. In the Enhanced Operating Mode, OE not only continues to control the

OE

Output Enable

I

outputs in this same manner, but also can function as an additional ANDing

input to the combined effective read-enable signal, along with REN and

REN2, whenever Control Register bit 05 is HIGH. (See Table 5.) 2

1I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

2The ostensible differences in signal assertiveness are reconciled before ANDing.

BOLD ITALIC = Enhanced Operating Mode

6

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

PIN DESCRIPTIONS (cont’d)

PIN

LD

FL/RT

WXI/WEN2

RXI/REN2

FF

PAF

NAME

Load

First Load/

Retransmit

Write

Expansion

Input/Write

Enable 2

Read

Expansion

Input/Read

Enable 2

Full Flag

Programmable

Almost-Full Flag

PIN

TYPE 1

I

I

I

I

O

O

DESCRIPTION

When LD is LOW, the data word on D0 – D17 (the data inputs) is written into a programmable-flag-offset register, or into the Control Register (when in the Enhanced Operating Mode), on the LOW-to-HIGH transition of WCLK, whenever WEN is LOW. (See Table 3.) Also, when LD is LOW, a word is read to Q0 – Q17 (the data outputs) from the offset registers and/or the Control Register (when in the Enhanced Operating Mode) on the LOW-to-HIGH transition of RCLK, whenever REN is LOW. (See again Table 3, and particularly the Notes following this table.) When LD is HIGH, normal FIFO write and read operations are enabled.

In the standalone or paralleled configuration, FL/RT should be LOW during a reset operation. (See Tables 1 and 2.) However, thereafter, in the standalone or paralleled configuration, if FL is taken HIGH, it functions instead as RT (Retransmit), and resets the FIFO’s internal read pointer to the first physical location of the RAM array. Note that although Retransmit is an ‘enhanced’ feature, it is always available for a FIFO during standalone operation, whether the FIFO is in IDT-Compatible Operating Mode or in Enhanced Operating Mode; it is not regulated either by the Control Register or by the EMODE control input. In IDT-compatible cascaded configuration, FL has an entirely

different function; it is grounded for the first FIFO device (the ‘master’ device or ‘firstload’ device), and is set to HIGH for all other FIFO devices in the daisy chain. Thus, the Retransmit feature is not available for FIFOs operating in an IDT-compatible cascaded configuration.

This signal is dual-purpose; its functionality is determined during a reset operation, according to its own state, and also according to the states of the three other control inputs RXI/REN2, FL/RT, and EMODE. (See Tables 1 and 2.) In the standalone or paralleled configuration, WXI/WEN2 is grounded. In the cascaded configuration, WXI/WEN2 is connected to WXO (Write Expansion Output) of the previous device, and functions as WXI. In the Enhanced Operating Mode,

WXI/WEN2 functions as a second write-enable signal, WEN2, which is ANDed with WEN to produce an effective internal write-enable signal. 2

This signal is dual-purpose; its functionality is determined during a reset operation, according to its own state, and also according to the states of the three other control inputs WXI/WEN2, FL/RT, and EMODE. (See Tables 1 and 2.) In the standalone or paralleled configuration, RXI/REN2 is grounded. In the cascaded configuration, RXI/REN2 is connected to RXO (Read Expansion Output) of the previous device, and functions as RXI. In the Enhanced Operating Mode,

RXI/REN2 functions as a second read-enable signal, REN2, which is ANDed with REN – and perhaps also with OE, if Control-Register bit 05 is HIGH – to produce an effective internal read-enable signal. 2

When FF is LOW, the FIFO is full; further advancement of its internal write-address pointer, and further data writes through its Data Inputs into its internal memory array, are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.

When PAF is LOW, the FIFO is ‘almost full,’ based on the almost-full-offset value programmed into the FIFO’s Almost-Full Offset Register. The default value of this offset at reset is one-eighth of the total number of words in the FIFO-memory array, minus one, measured from ‘full.’ (See Table 4.) In the IDT-Compatible Operating Mode, PAF is asynchronous. In the Enhanced Operating Mode, PAF is synchronized to WCLK after a reset operation, according to the state of Control Register bit 04. (See Table 5.)

NOTES:

1.I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

2.The ostensible differences in signal assertiveness are reconciled before ANDing.

BOLD ITALIC = Enhanced Operating Mode

7

LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

PIN DESCRIPTIONS (cont’d)

PIN

NAME

PIN

DESCRIPTION

TYPE 1

This signal is dual-purpose; its functionality is determined during a reset operation

according to the states of the two control inputs WXI/WEN2 and RXI/REN2. (See

Write

Tables 1 and 2.) In the standalone or paralleled configuration, whenever HF is LOW

the device is more than half full. In IDT-Compatible Operating Mode, HF is

Expansion

WXO/HF

O

asynchronous; in the Enhanced Operating Mode, HF may be synchronized

Output/

either to WCLK or to RCLK after a reset operation, according to the state of

Half-Full Flag

Control Register bits 02 and 03. (See Table 5.) In the IDT-compatible cascaded

configuration, a pulse is sent from WXO to the WXI input of the next FIFO in the

daisy-chain cascade, whenever the last location in the FIFO is written.

When PAE is LOW, the FIFO is ‘almost empty,’ based on the almost-empty-offset

value programmed into the FIFO’s Almost-Empty Offset Register. The default value

Programmable

of this offset at reset is one-eighth of the total number of words in the FIFO-memory

PAE

Almost-Empty

O

array, minus one, measured from ‘empty.’ (See Table 4.) In IDT-Compatible

Flag

Operating Mode, PAE is asynchronous. In the Enhanced Operating Mode,

PAE

is synchronized to RCLK after a reset operation, according to the state of

Control Register bit 01. (See Table 5.)

When EF is LOW, the FIFO is empty; further advancement of its internal read-

address pointer, and further readout of data words from its internal memory array to

EF

Empty Flag

O

its Data Outputs, are inhibited. When EF is HIGH, the FIFO is not empty. EF is

synchronized to RCLK.

This signal is dual-purpose; its functionality is determined by the state of the

EMODE control input during a reset operation. (See Tables 1 and 2.) In the IDT-

Read

Compatible Operating Mode, in a cascaded configuration, a pulse is sent from RXO

RXO

/EF

2

Expansion

O

to the RXI input of the next FIFO in the daisy-chain cascade, whenever the last

Output

location of the FIFO is read. In the Enhanced Operating Mode, whenever

EMODE is being asserted (LOW), EF2 behaves as an exact duplicate of

EF,

but delayed by one full cycle of RCLK with respect to EF.

Q0 – Q17

Data Outputs

O/Z

Data outputs to drive an 18-bit bus.

VCC

Power

V

+5 V power-supply pins.

VSS

Ground

V

0 V ground pins.

NOTE:

1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

BOLD ITALIC = Enhanced Operating Mode

8

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

ABSOLUTE MAXIMUM RATINGS

PARAMETER		RATING
Supply Voltage to VSS Potential	– 0.5	V to 7 V
Signal Pin Voltage to VSS Potential	– 0.5	V to VCC + 0.5 V
DC Output Current 1	±75 mA
Temperature Range with Power Applied 2	– 55°C to 125°C
Storage Temperature Range	– 65°C to 150°C
Power Dissipation (PLCC Package Limit)	2 W

NOTES:

1.Only one output may be shorted at a time, for a period not exceeding 30 seconds.

2.Measured with clocks idle.

OPERATING RANGE

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
TA	Temperature, Ambient	0	70	C
VCC	Supply Voltage	4.5	5.5	V
VSS	Supply Voltage	0	0	V
VIL	Logic LOW Input Voltage	–0 .5	0.8	V
VIH	Logic HIGH Input Voltage	2.0	VCC + 0.5	V

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SYMBOL	PARAMETER		TEST CONDITIONS	MIN.	MAX.	UNIT
ILI	Input Leakage	VCC = 5.5 V, VIN = 0 V to VCC		–10	10	mA
ILO	I/O Leakage		³ VIH, 0 V £ VOUT £ VCC	–10	10	mA
		OE
VOH	Output HIGH Voltage	IOH = –12.0 mA		2.4		V
VOL	Output LOW Voltage	IOL = 16.0 mA			0.4	V
ICC	Average Operating Supply Current 1	Measured at fCC = 50 MHz			190	mA
ICC2	Average Standby Supply Current	All inputs = VIH MIN. (clocks idle)			25	mA
ICC3	Power-Down Supply Current	All inputs = VCC – 0.2 V (clocks idle)			1	mA

NOTE:

1. Output load is disconnected.

AC TEST CONDITIONS

		PARAMETER	RATING
	Input Pulse Levels		VSS to 3 V
	Input Rise and Fall Times		3 ns
	(10% to 90%)
	Input Timing Reference Levels		1.5 V
	Output Timing Reference Levels		1.5 V
	Output Load,	R1 (Top Resistor)	1.1k W
	Timing Tests	R2 (Bottom Resistor)	680 W
	(Figure 4)	CL (Load Capacitance)	30 pF

CAPACITANCE1, 2

PARAMETER	RATING
CIN (Input Capacitance) VIN = 0 V	8 pF
COUT (Output Capacitance) VOUT = 0 V	8 pF

NOTES:

1.Sample tested only.

2.Capacitances are maximum values at 25°C, measured at 1.0 MHz, with VIN = 0 V.

	+5 V
1.1 k Ω
DEVICE
UNDER
TEST	Ω	30 pF *
680

* INCLUDES JIG AND SCOPE CAPACITANCES	540215-3

Figure 4. Output Load Circuit

BOLD ITALIC = Enhanced Operating Mode

9

LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

AC ELECTRICAL CHARACTERISTICS

SYMBOL	PARAMETER		–20		–25		-35
		MIN. MAX. MIN. MAX. MIN. MAX.
fCC	Clock Cycle Frequency		50		40		28.6
tA	Data Access Time	2	12	3	15	3	20
tCLK	Clock Cycle Time	20		25		35
tCLKH	Clock HIGH Time	8		10		14
tCLKL	Clock LOW Time	8		10		14
tDS	Data Setup Time	5		6		7
tDH	Data Hold Time	2		2		2
tENS	Enable Setup Time	5		6		7
tENH	Enable Hold Time	2		2		2
tRS	Reset Pulse Width 1	20		25		35
tRSS	Reset Setup Time 2	12		15		20
tRSR	Reset Recovery Time 2	12		15		20
tRSF	Reset to Flag and Output Time		30		35		40
tOLZ	Output Enable to Output in Low-Z 2	0		0		0
tOE	Output Enable to Output Valid		9		12		15
tOHZ	Output Enable to Output in High-Z 2	1	9	1	12	1	15
tWFF	Write Clock to Full Flag		12		15		20
tREF	Read Clock to Empty Flag		12		15		20
tPAF	Clock to Programmable Almost-Full Flag (IDT-Compatible Operating		14		17		23
	Mode)
tPAE	Clock to Programmable Almost-Empty Flag (IDT-Compatible		14		17		23
	Operating Mode)
tHF	Clock to Half-Full Flag (IDT-Compatible Operating Mode)		14		17		23
tPAFS	Clock to Programmable Almost-Full Flag		14		17		23
	(Enhanced Operating Mode)
tPAES	Clock to Programmable Almost-Empty Flag		14		17		23
	(Enhanced Operating Mode)
tHFS	Clock to Half-Full Flag (Enhanced Operating Mode)		14		17		23
tXO	Clock to Expansion-Out		12		15		20
tXI	Expansion-In Pulse Width	7		9		13
tXIS	Expansion-In Setup Time	7		9		14
tSKEW1	Skew Time Between Read Clock and Write Clock for Full Flag 3	9		11		16
tSKEW2	Skew Time Between Write Clock and Read Clock for Empty Flag 4	9		11		16

NOTES:

1.Pulse widths less than the stated minimum values may cause incorrect operation.

2.Values are guaranteed by design; not currently tested.

3.These times also apply to the Programmable-Almost-Full and Half-Full flags when they are synchronized to WCLK.

4.These times also apply to the Half-Full and Programmable-Almost-Empty flags when they are synchronized to RCLK.

BOLD ITALIC = Enhanced Operating Mode

10

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

DESCRIPTION OF SIGNALS AND

OPERATING SEQUENCES

Table 1. Grouping-Mode Determination

During a Reset Operation 5

WXO/HF

WXI/WEN2

RXI/REN2

FL/RT

RXO/EF2

EMODE

WXI/WEN2

RXI/REN2

FL/RT

MODE

USAGE

USAGE

USAGE

USAGE

USAGE

1

Cascaded

H

H

H

H

WXO

WXI

RXI

FL

RXO

Slave 2

H 1

Cascaded

H

H

L

WXO

WXI

RXI

FL

RXO

Master

2

H

H

L

X

(Reserved)

–

–

–

–

–

H

L

H

X

(Reserved)

–

–

–

–

–

H 3

(Not Allowed

(RT)

H

L

L

(HF)

(none)

(none)

(none)

During Reset)

H

L

L

L 3

Standalone

(none)

(none)

RT

(none)

HF

H 3

(Not Allowed

L

X

X

(HF)

(WEN2)

(REN2)

(RT)

(EF2)

During Reset)

L 3

Interlocked

L

X

X

HF

WEN2

REN2

RT

EF2

Paralleled

4

NOTES:

1.In IDT-compatible cascading, a reset operation forces WXO/HF and RXO/EF2 HIGH for the nth FIFO, thus forcing WXI/WEN2 and RXI/REN2 HIGH for the (n + 1)st FIFO.

2.The terms ‘master’ and ‘slave’ refer to IDT-compatible cascading. In pipelinedcascading4, there is no such distinction.

3.Once grouping mode has been determined during a reset operation, FL/RT then may go HIGH to activate a retransmit operation.

4.EMODE must be asserted for access to the Control Register to be enabled. Also, FIFOs being used in a pipelined-cascading configuration should be in Interlocked Paralleled mode.

5.Setup-time and recovery-time specifications apply during a reset operation.

6.H = HIGH; L = LOW; X = Don’t Care.

Table 2. Expansion-Pin Usage According to

Grouping Mode

IDT-COMPATIBLE OPERATING MODE

ENHANCED

OPERATING MODE

I/O

PIN

DEPTH-CASCADED

DEPTH-CASCADED

STANDALONE

INTERLOCKED

MASTER

SLAVE

PARALLELED

From

(other FIFO)

I

WXI

/WEN2

From WXO ((n-1)st FIFO)

From WXO ((n-1)st FIFO)

Grounded

FF

Becomes

O

WXO/HF

To WXI ((n+1)st FIFO)

To WXI ((n+1)st FIFO)

Becomes HF

HF

REN2

From

(other FIFO)

I

RXI/

From

RXO

((n-1)st FIFO)

From

RXO

((n-1)st FIFO)

Grounded

EF

O

RXO

/EF

2

To RXI ((n+1)st FIFO)

To RXI ((n+1)st FIFO)

Unused

Becomes

EF

2

Becomes RT1

Becomes RT1

I

FL/

RT

Grounded (Logic LOW)

Logic HIGH

NOTE:

1. FL/RT may be grounded if the Retransmit facility is not being used.

BOLD ITALIC = Enhanced Operating Mode

11

LH540215/25										512 x 18/1024 x 18 Synchronous FIFO
							Table 3. Selection of Read and Write Operations
				3,4		3, 4	WCLK	RCLK		ACTION
	LD		WEN		REN
	L		X		X		–	–	No operation.
	L		L		L				Illegal combination, which will cause errors.
	L		L		H			X	Write to a programmable register. 1
	L		H		H			X	Hold present value of programmable-register write counter, and do not
									write. 2
	L		H		L		X		Read from a programmable register. 1
	L		H		H		X		Hold present value of programmable-register read counter, and do not
									read. 2
	H		L		X			X	Normal FIFO write operation.
	H		X		L		X		Normal FIFO read operation.
	H		L		X		–	X	No write operation.
	H		H		X		X	X	No write operation.
	H		X		L		X	–	No read operation.
	H		X		H		X	X	No read operation.
	H		L		L		–	–	No operation.
KEY:
H = Logic ‘HIGH’; L = LogicLOW’;‘							X = ‘Don’t-care’ (logicHIGH,’‘			logic ‘LOW,’ or any transition);
= A ‘LOW’-to-‘HIGH’ transition; – =							Any condition EXCEPT a ‘LOW’-to-‘HIGH’ transition.

NOTES:

1.The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the selection for writing; the other state machine controls the selection for reading. These two state machines operate independently of each other. Both state machines are reset to point to Word 0 by a reset operation. In the Enhanced Operating Mode, if Control Register bit 00 is set, both state machines are also reset to point to Word 0 by deassertion of LD after LD has been asserted (that is, by a rising edge of LD), followed by a valid memory array write cycle for the writing-control state machine and/or by a valid memory array read cycle for the reading-control state machine.

2.The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is always:

Word 0: Almost-Empty Offset Register Word 1: Almost-Full Offset Register Word 0: Almost-Empty Offset Register

...

(repeats indefinitely)

...

The order of the three programmable registers which are accessible in Enhanced Operating Mode, as selected by either state machine, is always:

Word 0: Almost-Empty Offset Register Word 1: Almost-Full Offset Register Word 2: Control Register

Word 0: Almost-Empty Offset Register

(repeats indefinitely)

Note that, in IDT-Compatible Operating Mode, Word 2 is not accessed; Word 0 and Word 1 alternate.

3.After normal FIFO operation has begun, writing new contents into either of the offset registers should only be done when the FIFO is empty.

4.WEN2, REN2, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control input and of Control Register Bit 05.

BOLD ITALIC = Enhanced Operating Mode

12

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d)

Table 4. Status Flags

NUMBER OF UNREAD DATA WORDS PRESENT WITHIN FIFO 1, 2

FULL

MIDDLE FLAGS

EMPTY

FLAG

FLAG

512 × 18 FIFO

1024 × 18 FIFO

FF

PAF

HF

PAE

EF

0

0

H

H

H

L

L

1 to q

1 to q

H

H

H

L

H

(q + 1) to 256

(q + 1) to 512

H

H

H

H

H

257 to (512 – (p + 1))

513 to (1024 – (p + 1))

H

H

L

H

H

(512 – p) to 511

(1024 – p) to 1023

H

L

L

H

H

512

1024

L

L

L

H

H

NOTES:

1.q = Programmable-Almost-Empty Offset value. (Default values: 512 × 18, q = 63; 1024 × 18, q = 127.)

2.p = Programmable-Almost-Full Offset value. (Default values: 512 × 18, p = 63; 1024 × 18, p = 127.)

3.Only 9 (512 × 18) or 10 (1024 × 18) of the 12 offset-value-register bits should be programmed. The unneeded most-significant-end bits should be LOW (zero).

4.The flag output is delayed by one full clock cycle in Enhanced Operating Mode, when synchronous operation is specified for intermediate flags.

BOLD ITALIC = Enhanced Operating Mode

13

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

Table 5. Control-Register Format

COMMAND REGISTER CODE

BITS

L

00

H

	01	L
		H
		LL
	03, 02	LH
		HL,
		HH
	04	L
		H
		L
	05
		H
		L
	06	H
	11, 10,	LLLLL
	09, 08, 07
	NOTES:

	VALUE AFTER RESET				FLAG
					AFFECTED,
	EMODE = H EMODE = L
					IF ANY

L

H

–

L

H

PAE

LL

HH

HF

L

H

PAF

L

H

–

L	L	–
LLLLL	LLLLL	–

DESCRIPTION

Deassertion of LD does not reset the programmableregister write pointer and read pointer.

Deassertion of LD resets the programmable-register write pointer and read pointer to address Word 0, the Programmable-Almost- Empty-Flag-Offset Register. The change takes effect after a valid write operation or a valid read operation, respectively, to the memory array.

Set by −RCLK, reset by −WCLK.

Set and reset by −RCLK.

Set by −WCLK, reset by −RCLK.

Set and reset by −RCLK.

Set and reset by −WCLK.

Set by −WCLK, reset by −RCLK.

Set and reset by −WCLK.

OE has no effect on an internal read operation, apart from disabling the outputs.

Deassertion of OE inhibits a read operation; whenever the data outputs Q0 – Q 17 are in the high-Z state, the read pointer does not advance.

Reserved.

Reserved.

NOTES

IDT-compatible addressing of programmable registers.

Non-ambiguous addressing of programmable registers.

Asynchronous flag clocking.

Synchronous flag clocking.

Asynchronous flag clocking.

Synchronous flag clocking at output port.

Synchronous flag clocking at input port.

Asynchronous flag clocking.

Synchronous flag clocking.

Allows the read-address pointer to advance even when Q0 – Q 17 are not driving the output bus.

Inhibits the read-address pointer from advancing when Q0 – Q 17 are not driving the output bus; thus, guards against data loss.

Future use to control depth cascading and interlocked paralleling.

Reserved.

1.When EMODE is HIGH, and Control Register bits 00-05 are LOW, the FIFO behaves in a manner functionally equivalent to the IDT72215B/25B FIFO of similar depth and speed grade. Under these conditions, the Control Register is not visible or accessible to the external system which includes the FIFO.

2.If EMODE is not asserted (is HIGH), Control Register bits 00-05 remain LOW after a reset operation. However, if EMODE is asserted (is

LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits 06-11 are unaffected by EMODE.

BOLD ITALIC = Enhanced Operating Mode

14

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

DESCRIPTION OF SIGNALS AND

OPERATING SEQUENCES (cont’d)

Data Inputs

DATA IN (D0 – D 17)

Data, programmable-flag-offset values, and ControlRegister codes are input to the FIFO as 18-bit words on D0 – D17. Unused bit positions in offset-value and Con- trol-Register words should be zero-filled.

Control Inputs

RESET (RS)

The FIFO is reset whenever the asynchronous Reset (RS) input is taken to a LOW state. A reset operation is required after power-up, before the first write operation may occur. The state of the FIFO is fully defined after a reset operation. If the default values which are entered into the Programmable-Flag-Offset-Value Registers and the Control Register by a reset operation are acceptable, then no device programming is required. A reset operation initializes the FIFO’s internal read-address and write-address pointers to the FIFO’s firstphysical memory location. The five status flags, FF, PAF, HF, PAE, and EF, are updated to indicate that the FIFO is completely empty; thus, the first three of these are reset to HIGH, and the last two are reset to LOW. The flag-offset values for PAF and PAE each are initialized to one-eighth of the depth of a single FIFO, minus one; 63 for a 512-word FIFO, and 127 for a 1024-word FIFO. If EMODE is not being asserted (i.e., if EMODE is HIGH), all Control Register bits are initialized to LOW, to configure the FIFO to operate in the IDT72215B/25B-Compatible Operating Mode. Until a write operation occurs, the data outputs D0 – D17 all are

LOW whenever OE is LOW.

ENHANCED OPERATING MODE (EMODE)

Whenever EMODE is asserted during a reset operation, Control Register bits 00 – 05 remain HIGH rather than LOW after the completion of the reset operation. Thus, EMODE has the effect of activating all of the Enhanced-Operating-Mode features during a reset operation. Subsequently, they may be individually disabled or re-enabled by changing the setting of Control-Register bits. The behavior of these Enhanced-Operating-Mode features is described in Table 5. For permanent Enhanced-Operating-Mode operation, EMODE must be grounded; dynamic control of EMODE during system operation is not recommended.

Asserting EMODE during a reset operation also causes WXI/WEN2 to be configured as WEN2, and

RXI/REN2 to be configured as REN2, to support inter- locked-paralleled operation of two FIFOs ‘side by side. (See Figure 27.) Additionally, RXO/EF2 is config-

ured as EF2, which duplicates the EF signal with one

BOLD ITALIC = Enhanced Operating Mode

extra RCK cycle delay, in order to provide proper timing for ‘pipelined’ cascaded operation.

WRITE CLOCK (WCLK)

A rising edge (LOW-to-HIGH transition) of WCLK initiates a FIFO write cycle if LD is HIGH, or a programma- ble-register write cycle if LD is LOW. The 18 data inputs, and all input-side synchronous control inputs, must meet setup and hold times with respect to the rising edge of WCLK. The input-side status flags are meaningful after specified time intervals, following a rising edge of WCLK.

Conceptually, the WCLK input receives a free-running, periodic ‘clock’ waveform, which is used to control other signals which are edge-sensitive. However, there actually is not any absolute requirement that the WCLK waveform must be periodic. An ‘asynchronous’ mode of operation is in fact possible, if WEN is continuously asserted (that is, is continuously held LOW), and WCLK receives aperiodic ‘clock’ pulses of suitable duration. There likewise is no requirement that WCLK must have any particular synchronization relation to the read clock RCLK. These two clock inputs may in fact receive the same ‘clock’ signal; or they may receive totally-different signals, which are not synchronized to each other in any way.

WRITE ENABLE (WEN)

Whenever WEN is being asserted (is LOW) and LD is HIGH, and the FIFO is not full, an 18-bit data word is loaded into the effective input register for the memory array at every WCLK rising edge (LOW-to-HIGH transition). Data words are stored into the two-port memory array sequentially, regardless of any ongoing read operation. Whenever WEN is not being asserted (is HIGH), the input register retains whatever data word it contained previously, and no new data word gets loaded into the memory array.

To prevent overrunning the internal FIFO boundaries, further write operations are inhibited whenever the Full Flag (FF) is being asserted (is LOW). If a valid read operation then occurs, upon the completion of that read cycle FF again goes HIGH after a time tWFF, and another write operation is allowed to begin whenever WCLK makes another LOW-to-HIGH transition. Effectively, WEN is overridden by FF; thus, during normal FIFO operation, WEN has no effect when the FIFO is full.

In the Enhanced Operating Mode, whenever EMODE is being asserted (is LOW), WXI/WEN2 functions as WEN2, an additional duplicate (albeit asser- tive-HIGH) write-enable input, in order to provide an‘interlocking’ mechanism for reliable synchronization of two paralleled FIFOs. To control writing, WEN2 is ANDed with WEN; this logic-AND function

(WEN WEN2) then behaves like WEN in the foregoing description.

15