Sharp LH28F008SCR-V85, LH28F008SCT-V85, LH28F008SCT-V12, LH28F008SCN-V12, LH28F008SCHN-V12 Datasheet

LH28F008SC-V/SCH-V

LH28F008SC-V/SCH-V

DESCRIPTION

The LH28F008SC-V/SCH-V flash memories with Smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SC-V/SCH-V offer three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs.

FEATURES

•Smart 5 technology

–5 V VCC

–5 V or 12 V VPP

•High performance read access time LH28F008SC-V85/SCH-V85

–85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V) LH28F008SC-V12/SCH-V12

–120 ns (5.0±0.5 V)

8 M-bit (1 MB x 8) Smart 5

Flash Memories

•Enhanced automated suspend options

–Byte write suspend to read

–Block erase suspend to byte write

–Block erase suspend to read

•Enhanced data protection features

–Absolute protection with VPP = GND

–Flexible block locking

–Block erase/byte write lockout during power transitions

•SRAM-compatible write interface

•High-density symmetrically-blocked architecture

–Sixteen 64 k-byte erasable blocks

•Enhanced cycling capability

–100 000 block erase cycles

–1.6 million block erase cycles/chip

•Low power management

–Deep power-down mode

–Automatic power saving mode decreases ICC in static mode

•Automated byte write and block erase

–Command user interface

–Status register

•ETOXTM V nonvolatile flash technology

•Packages

–40-pin TSOP Type I (TSOP040-P-1020)

Normal bend/Reverse bend

–44-pin SOP (SOP044-P-0600)

–48-ball CSP (FBGA048-P-0608)

ETOX is a trademark of Intel Corporation.

COMPARISON TABLE

	VERSIONS	OPERATING TEMPERATURE	DC CHARACTERISTICS
			VCC deep power-down current (MAX.)
	LH28F008SC-V	0 to +70˚C	10 µA
	LH28F008SCH-V	–25 to +85˚C	20 µA

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

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LH28F008SC-V/SCH-V

PIN CONNECTIONS

40-PIN TSOP (Type I)					44-PIN SOP			TOP VIEW
A19				NC	VPP					VCC
	1		40			1			44
A18				NC	RP#					CE#
	2		39			2			43
A17				WE#	A11					A12
	3		38			3			42
A16				OE#	A10					A13
	4		37			4			41
A15				RY/BY#	A9					A14
	5		36			5			40
A14				DQ7	A8					A15
	6		35			6			39
A13				DQ6	A7					A16
	7		34			7			38
A12				DQ5	A6					A17
	8		33			8			37
CE#				DQ4	A5					A18
	9		32			9			36
VCC				VCC	A4					A19
	10		31			10			35
VPP				GND	NC					NC
	11		30			11			34
RP#				GND	NC					NC
	12		29			12			33
A11				DQ3	A3					NC
	13		28			13			32
A10				DQ2	A2					NC
	14		27			14			31
A9				DQ1	A1					WE#
	15		26			15			30
A8				DQ0	A0					OE#
	16		25			16			29
A7				A0	DQ0					RY/BY#
	17		24			17			28
A6				A1	DQ1					DQ7
	18		23			18			27
A5				A2	DQ2					DQ6
	19		22			19			26
A4				A3	DQ3					DQ5
	20		21			20			25
					GND					DQ4
						21			24
					GND					VCC
		(TSOP040-P-1020)				22			23
								(SOP044-P-0600)
NOTE :
Reverse bend available on request.

48-BALL CSP

	1	2	3	4	5	6	7	8
A	A5	A8	A11	VPP	VCC	A12	A15	A18
B	A6	A9	RP#	NC	NC	CE#	A14	A17
C	A4	A7	A10	NC	NC	A13	A16	A19
D	A3	A0	DQ2	NC	NC	DQ6	RY/BY#	NC
E	A1	DQ1	GND	NC	NC	DQ4	DQ7	OE#
F	A2	DQ0	DQ3	GND	VCC	DQ5	NC	WE#

(FBGA048-P-0608)

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LH28F008SC-V/SCH-V

BLOCK DIAGRAM

				DQ0-DQ7
			OUTPUT		INPUT
			BUFFER		BUFFER
							I/O	VCC
			OUTPUT MULTIPLEXER	IDENTIFIER			LOGIC
				REGISTER
					DATA REGISTER			CE#
				STATUS		COMMAND		WE#
				REGISTER
						USER
						INTERFACE		OE#
				DATA				RP#
				COMPARATOR
A0-A19	INPUT	Y DECODER		Y GATING		WRITE		RY/BY#
								VPP
	BUFFER					STATE
							PROGRAM/ERASE
						MACHINE
							VOLTAGE SWITCH
	ADDRESS			16				VCC
	LATCH	X DECODER		64 k-BYTE				GND
				BLOCKS
	ADDRESS
	COUNTER

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LH28F008SC-V/SCH-V

PIN DESCRIPTION

	SYMBOL	TYPE	NAME AND FUNCTION
	A0-A19	INPUT	ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
			are internally latched during a write cycle.
			DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
	DQ0-DQ7	INPUT/	data during memory array, status register, and identifier code read cycles. Data pins
		OUTPUT	float to high-impedance when the chip is deselected or outputs are disabled. Data is
			internally latched during a write cycle.
			CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
	CE#	INPUT	amplifiers. CE#-high deselects the device and reduces power consumption to standby
			levels.
			RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
			internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
			write operations which provide data protection during power transitions. Exit from deep
	RP#	INPUT	power-down sets the device to read array mode. RP# at VHH enables setting of the
			master lock-bit and enables configuration of block lock-bits when the master lock-bit is
			set. RP# = VHH overrides block lock-bits thereby enabling block erase and byte write
			operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
			with VIH ≤ RP# ≤ VHH produce spurious results and should not be attempted.
	OE#	INPUT	OUTPUT ENABLE : Gates the device's outputs during a read cycle.
	WE#	INPUT	WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
			latched on the rising edge of the WE# pulse.
			READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
			performing an internal operation (block erase, byte write, or lock-bit configuration).
	RY/BY#	OUTPUT	RY/BY#-high indicates that the WSM is ready for new commands, block erase is
			suspended, and byte write is inactive, byte write is suspended, or the device is in deep
			power-down mode. RY/BY# is always active and does not float when the chip is
			deselected or data outputs are disabled.
			BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For
			erasing array blocks, writing bytes, or configuring lock-bits. With VPP ≤ VPPLK, memory
	VPP	SUPPLY	contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
			invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
			and should not be attempted.
			DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation.
	VCC	SUPPLY	Do not float any power pins. With VCC ≤ VLKO, all write attempts to the flash memory
			are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC
			CHARACTERISTICS") produce spurious results and should not be attempted.
	GND	SUPPLY	GROUND : Do not float any ground pins.
	NC		NO CONNECT : Lead is not internal connected; recommend to be floated.

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LH28F008SC-V/SCH-V

1 INTRODUCTION

This datasheet contains LH28F008SC-V/SCH-V specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SC-V/ SCH-V flash memories documentation also includes ordering information which is referenced in Section 7.

1.1New Features

LH28F008SC-V/SCH-V Smart 5 flash memories maintain backwards-compatibility with the LH28F008SA. Key enhancements over the LH28F008SA include :

•Smart 5 Technology

•Enhanced Suspend Capabilities

•In-System Block Locking

Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the LH28F008SA to LH28F008SC-V/SCH-V. When upgrading, it is important to note the following differences :

•Because of new feature support, the two devices have different device codes. This allows for software optimization.

•VPPLK has been lowered from 6.5 V to 1.5 V to support 5 V block erase, byte write, and lock-bit configuration operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND.

•To take advantage of Smart 5 technology, allow VPP connection to 5 V.

1.2Product Overview

The LH28F008SC-V/SCH-V are high-performance 8 M-bit Smart 5 flash memories organized as 1 M- byte of 8 bits. The 1 M-byte of data is arranged in sixteen 64 k-byte blocks which are individually

erasable, lockable, and unlockable in-system. The memory map is shown in Fig.1.

Smart 5 technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. VPP at 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations Offered by Smart 5 Technology

VCC VOLTAGE	VPP VOLTAGE
5 V	5 V, 12 V

Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations.

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations.

A block erase operation erases one of the device’s 64 k-byte blocks typically within 1 second (5 V VCC, 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block.

Writing memory data is performed in byte increments typically within 6 µs (5 V VCC, 12 V VPP). Byte write suspend mode enables the system

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LH28F008SC-V/SCH-V

to read data from, or write data to any other flash memory array location.

Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits.

The status register indicates when the WSM’s block erase, byte write, or lock-bit configuration operation is finished.

The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode.

The access time is 85 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70˚C (LH28F008SC-V)/ –25 to +85˚C (LH28F008SCH-V). At 4.5 to 5.5 V VCC, the access time is 90 ns or 120 ns.

The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC.

When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.

FFFFF
	64 k-Byte Block	15
F0000
EFFFF	64 k-Byte Block	14
E0000
DFFFF	64 k-Byte Block	13
D0000
CFFFF	64 k-Byte Block	12
C0000
BFFFF	64 k-Byte Block	11
B0000
AFFFF	64 k-Byte Block	10
A0000
9FFFF	64 k-Byte Block	9
90000
8FFFF	64 k-Byte Block	8
80000
7FFFF	64 k-Byte Block	7
70000
6FFFF	64 k-Byte Block	6
60000
5FFFF	64 k-Byte Block	5
50000
4FFFF	64 k-Byte Block	4
40000
3FFFF	64 k-Byte Block	3
30000
2FFFF	64 k-Byte Block	2
20000
1FFFF	64 k-Byte Block	1
10000
0FFFF	64 k-Byte Block	0
00000
	Fig. 1 Memory Map

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LH28F008SC-V/SCH-V

2 PRINCIPLES OF OPERATION

The LH28F008SC-V/SCH-V Smart 5 flash memories include an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contents—block erase, byte write, lock-bit configuration, status, and identifier codes—are accessed via the CUI and verified through the status register.

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data.

Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system

software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location.

2.1Data Protection

Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to VPPH1/2. The device accommodates either design practice and encourages optimization of the processor-memory interface.

When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1Read

Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read

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LH28F008SC-V/SCH-V

array mode. Four control pins dictate the data flow in and out of the component : CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 12 illustrates a read cycle.

3.2Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ7 are placed in a high-impedance state.

3.3Standby

CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes.

3.4Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

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LH28F008SC-V/SCH-V

3.5Read Identifier Codes Operation

The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting.

FFFFF

		Reserved for
	F0004	Future Implementation
	F0003
	F0002	Block 15 Lock Configuration Code
	F0001	Reserved for
	F0000	Future Implementation
		Block 15
		(Blocks 2 through 14)
	1FFFF
		Reserved for
	10004	Future Implementation
	10003
	10002	Block 1 Lock Configuration Code
	10001
		Reserved for
	10000	Future Implementation
		Block 1
	0FFFF
		Reserved for
		Future Implementation
	00004
	00003	Master Lock Configuration Code
	00002	Block 0 Lock Configuration Code
	00001	Device Code
	00000	Manufacture Code Block 0

Fig. 2 Device Identifier Code Memory Map

3.6Write

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VPP = VPPH1/2, the CUI additionally controls block erasure, byte write, and lock-bit configuration.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 13 and Fig. 14 illustrate WE# and CE#-controlled write operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2 on VPP enables successful block erase, byte write and lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.

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LH28F008SC-V/SCH-V

		Table 2		Bus Operations
MODE	NOTE	RP#	CE#		OE#	WE#	ADDRESS	VPP	DQ0-7	RY/BY#
Read	1, 2, 3, 8	VIH or VHH	VIL		VIL	VIH	X	X	DOUT	X
Output Disable	3	VIH or VHH	VIL		VIH	VIH	X	X	High Z	X
Standby	3	VIH or VHH	VIH		X	X	X	X	High Z	X
Deep Power-Down	4	VIL	X		X	X	X	X	High Z	VOH
Read Identifier Codes	8	VIH or VHH	VIL		VIL	VIH	See Fig. 2	X	(NOTE 5)	VOH
Write	3, 6, 7, 8	VIH or VHH	VIL		VIH	VIL	X	X	DIN	X

NOTES :

1.Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP ≤ VPPLK, memory contents can be read, but

not altered.

2.X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2 voltages.

3.RY/BY# is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode.

4.RP# at GND±0.2 V ensures the lowest deep powerdown current.

5.See Section 4.2 for read identifier code data.

6.Command writes involving block erase, byte write, or lock-bit configuration are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2. Block erase, byte write, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted.

7.Refer to Table 3 for valid DIN during a write operation.

8.Don’t use the timing both OE# and WE# are VIL.

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LH28F008SC-V/SCH-V

Table 3 Command Definitions (NOTE 9)

	COMMAND	BUS CYCLES	NOTE	FIRST BUS CYCLE			SECOND BUS CYCLE
		REQ’D.		Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)	Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)
	Read Array/Reset	1		Write	X	FFH
	Read Identifier Codes	≥ 2	4	Write	X	90H	Read	IA	ID
	Read Status Register	2		Write	X	70H	Read	X	SRD
	Clear Status Register	1		Write	X	50H
	Block Erase	2	5	Write	BA	20H	Write	BA	D0H
	Byte Write	2	5, 6	Write	WA	40H or 10H	Write	WA	WD
	Block Erase and	1	5	Write	X	B0H
	Byte Write Suspend
	Block Erase and	1	5	Write	X	D0H
	Byte Write Resume
	Set Block Lock-Bit	2	7	Write	BA	60H	Write	BA	01H
	Set Master Lock-Bit	2	7	Write	X	60H	Write	X	F1H
	Clear Block Lock-Bits	2	8	Write	X	60H	Write	X	D0H

NOTES :

1.Bus operations are defined in Table 2.

2.X = Any valid address within the device. IA = Identifier code address : see Fig. 2.

BA = Address within the block being erased or locked. WA = Address of memory location to be written.

3.SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).

ID = Data read from identifier codes.

4.Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and master lock codes. See Section 4.2 for read identifier code data.

5.If the block is locked, RP# must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is VIH.

6.Either 40H or 10H is recognized by the WSM as the byte write setup.

7.If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH.

8.If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.

9.Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.

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LH28F008SC-V/SCH-V

4.1Read Array Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH.

4.2Read Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and master lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read :

Table 4 Identifier Codes

CODE	ADDRESS	DATA
Manufacture Code	00000H	89
Device Code	00001H	A6
Block Lock Configuration	X0002H (NOTE 1)
• Block is Unlocked		DQ0 = 0
• Block is Locked
		DQ0 = 1
• Reserved for Future Use		DQ1-7
Master Lock Configuration	00003H
• Device is Unlocked		DQ0 = 0
• Device is Locked		DQ0 = 1
• Reserved for Future Use
		DQ1-7

NOTE :

1.X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map.

4.3Read Status Register Command

The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH.

4.4Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or byte write suspend modes.

4.5Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written,

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