Sharp LH28F800SGB-L10, LH28F800SGR-L70, LH28F800SGR-L10, LH28F800SGHR-L70, LH28F800SGHR-L10 Datasheet

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

DESCRIPTION

The LH28F800SG-L/SGH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F800SG-L/SGH-L can operate at VCC = 2.7 V and VPP = 2.7 V. Their low voltage operation capability realizes longer battery life and suits for cellular phone application. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800SG-L/SGH-L offer three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking.These alternatives give designers ultimate control of their code security needs.

FEATURES

•SmartVoltage technology

–2.7 V, 3.3 V or 5 V VCC

–2.7 V, 3.3 V, 5 V or 12 V VPP

•High performance read access time LH28F800SG-L70/SGH-L70

–70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)/

85 ns (3.3±0.3 V)/100 ns (2.7 to 3.0 V)

LH28F800SG-L10/SGH-L10

–100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/

120 ns (2.7 to 3.0 V)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

•Enhanced automated suspend options

–Word write suspend to read

–Block erase suspend to word write

–Block erase suspend to read

•Enhanced data protection features

–Absolute protection with VPP = GND

–Flexible block locking

–Block erase/word write lockout during power transitions

•SRAM-compatible write interface

•High-density symmetrically-blocked architecture

–Sixteen 32 k-word erasable blocks

•Enhanced cycling capability

–100 000 block erase cycles

–1.6 million block erase cycles/chip

•Low power management

–Deep power-down mode

–Automatic power saving mode decreases ICC in static mode

•Automated word write and block erase

–Command user interface

–Status register

•ETOXTM V nonvolatile flash technology

•Packages

–48-pin TSOP TypeI (TSOP048-P-1220)

Normal bend/Reverse bend

–48-ball CSP(FBGA048-P-0808)

ETOX is a trademark of Intel Corporation.

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

- 1 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

COMPARISON TABLE

	VERSIONS	OPERATING TEMPERATURE	PACKAGE	WRITE PROTECT FUNCTION
	LH28F800SG-L	0 to +70˚C	48-pin TSOP (I)	Controlled by
	(FOR TSOP, CSP)		48-ball CSP	WP# and RP# pins
	LH28F800SGH-L	– 40 to +85˚C	48-pin TSOP (I)	Controlled by
	(FOR TSOP, CSP)		48-ball CSP	WP# and RP# pins
	LH28F800SG-L 1	0 to +70˚C	44-pin SOP	Controlled by RP# pin
	(FOR SOP)

1 Refer to the datasheet of LH28F800SG-L (FOR SOP).

PIN CONNECTIONS

48-PIN TSOP (Type I)

48-BALL CSP

TOP VIEW

A15

A16

1

48

1

2

3

4

5

6

7

8

A14

NC

2

47

A13

GND

A

A2

A5

A17

WP#

WE#

A8

A11

A14

3

46

A12

DQ15

4

45

A11

DQ7

5

44

B

A3

A6

A18

VPP

RP#

NC

A10

A13

A10

DQ14

6

43

A9

DQ6

7

42

C

A1

A4

A7

RY/BY#

NC

A9

A12

A15

A8

DQ13

8

41

NC

DQ5

9

40

NC

DQ12

D

A0

OE#

DQ1

DQ10

DQ12

DQ6

DQ15

A16

10

39

WE#

11

38

DQ4

RP#

VCC

12

37

E

GND

DQ8

DQ2

DQ11

VCC

DQ5

DQ14

GND

VPP

DQ11

13

36

WP#

DQ3

14

35

F

CE#

DQ0

DQ9

DQ3

DQ4

DQ13

DQ7

NC

RY/BY#

DQ10

15

34

A18

DQ2

16

33

A17

DQ9

17

32

(FBGA048-P-0808)

A7

DQ1

18

31

A6

DQ8

19

30

A5

DQ0

20

29

A4

OE#

21

28

A3

GND

22

27

A2

CE#

23

26

A1

A0

24

25

(TSOP048-P-1220)

NOTE :

Reverse bend available on request.

- 2 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

BLOCK DIAGRAM

				DQ0-DQ15
			OUTPUT		INPUT
			BUFFER		BUFFER
							I/O	VCC
			OUTPUT MULTIPLEXER	IDENTIFIER			LOGIC
				REGISTER
					DATA REGISTER			CE#
				STATUS		COMMAND		WE#
				REGISTER				OE#
						USER
						INTERFACE		WP#
				DATA				RP#
				COMPARATOR
A0-A18	INPUT	Y DECODER		Y GATING		WRITE		RY/BY#
								VPP
	BUFFER					STATE
							PROGRAM/ERASE
						MACHINE
							VOLTAGE SWITCH
	ADDRESS			16				VCC
	LATCH	X DECODER		32 k-WORD				GND
				BLOCKS
	ADDRESS
	COUNTER

- 3 -

			LH28F800SG-L/SGH-L (FOR TSOP, CSP)
	PIN DESCRIPTION
	SYMBOL	TYPE	NAME AND FUNCTION
	A0-A18	INPUT	ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
			are internally latched during a write cycle.
			DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
	DQ0-DQ15	INPUT/	data during memory array, status register, and identifier code read cycles. Data pins
		OUTPUT	float to high-impedance when the chip is deselected or outputs are disabled. Data is
			internally latched during a write cycle.
			CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
	CE#	INPUT	amplifiers. CE#-high deselects the device and reduces power consumption to standby
			levels.
			RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
			internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
			write operations which provide data protection during power transitions. Exit from deep
	RP#	INPUT	power-down sets the device to read array mode.
			RP# at VHH allows to set permanent lock-bit. Block erase, word write, or lock-bit
			configuration with VIH < RP# < VHH produce spurious results and should not be
			attempted.
	OE#	INPUT	OUTPUT ENABLE : Controls the device's outputs during a read cycle.
	WE#	INPUT	WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
			latched on the rising edge of the WE# pulse.
	WP#	INPUT	WRITE PROTECT : Master control for block locking. When VIL, locked blocks cannot be
			erased and programmed, and block lock-bits can not be set and reset.
			READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
			performing an internal operation (block erase, word write, or lock-bit configuration).
	RY/BY#	OUTPUT	RY/BY#-high indicates that the WSM is ready for new commands, block erase is
			suspended, and word write is inactive, word write is suspended, or the device is in deep
			power-down mode. RY/BY# is always active and does not float when the chip is
			deselected or data outputs are disabled.
			BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
			For erasing array blocks, writing words, or configuring lock-bits. With VPP ≤ VPPLK,
	VPP	SUPPLY	memory contents cannot be altered. Block erase, word write, and lock-bit configuration
			with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious
			results and should not be attempted.
			DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or
			5 V operation. To switch from one voltage to another, ramp VCC down to GND and then
	VCC	SUPPLY	ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
			attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
			(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
			not be attempted.
	GND	SUPPLY	GROUND : Do not float any ground pins.
	NC		NO CONNECT : Lead is not internal connected; recommend to be floated.

- 4 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800SG-L/SGH-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F800SG-L/ SGH-L flash memories documentation also includes ordering information which is referenced in Section 7.

1.1New Features

Key enhancements of LH28F800SG-L/SGH-L SmartVoltage flash memories are :

•SmartVoltage Technology

•Enhanced Suspend Capabilities

•In-System Block Locking

•Permanent Lock Capability,

Note following important differences :

•VPPLK has been lowered to 1.5 V to support 3.3 V and 5 V block erase, word write, and lockbit configuration operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND.

•To take advantage of SmartVoltage technology, allow VCC connection to 2.7 V, 3.3 V or 5 V.

•Once set the permanent lock bit, the blocks which have been set block lock-bit can not be erased, written forever.

1.2Product Overview

The LH28F800SG-L/SGH-L are high-performance 8 M-bit SmartVoltage flash memories organized as 512 k-word of 16 bits. The 512 k-word of data is arranged in sixteen 32 k-word blocks which are individually erasable, lockable, and unlockable insystem. The memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7 to 3.6 V VCC consumes approximately one-fifth

the power of 5 V VCC. But, 5 V VCC provides the highest read performance. VPP at 2.7 V, 3.3 V and 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and word write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations Offered by SmartVoltage Technology

VCC VOLTAGE	VPP VOLTAGE
2.7 V	2.7 V, 3.3 V, 5 V, 12 V
3.3 V	3.3 V, 5 V, 12 V
5 V	5 V, 12 V

Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations.

A command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timing necessary for block erase, word write, and lock-bit configuration operations.

A block erase operation erases one of the device’s 32 k-word blocks typically within 1.2 second (5 V VCC, 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block.

Writing memory data is performed in word increments typically within 7.5 µs (5 V VCC, 12 V VPP). Word write suspend mode enables the system to read data from, or write data to any other flash memory array location.

- 5 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

The selected block can be locked or unlocked individually by the combination of sixteen block lock bits and the RP# or WP#. Block erase or word write must not be carried out by setting block lock bits and setting WP# to low and RP# to VIH. Even if WP# is high state or RP# is set to VHH, block erase and word write to locked blocks is prohibited by setting permanent lock bit.

The status register or RY/BY# indicates when the WSM’s block erase, word write, or lock-bit configuration operation is finished.

The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, word write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep powerdown mode.

The access time is 70 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70°C (LH28F800SG-L)/

– 40 to +85°C (LH28F800SGH-L). At 4.5 to 5.5 V VCC, the access time is 80 ns or 100 ns. At lower VCC voltage, the access time is 85 ns or 100 ns (3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).

The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC and 3 mA at 2.7 to 3.6 V VCC.

When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.

7FFFF
	32 k-Word Block	15
78000
77FFF	32 k-Word Block	14
70000
6FFFF	32 k-Word Block	13
68000
67FFF	32 k-Word Block	12
60000
5FFFF	32 k-Word Block	11
58000
57FFF	32 k-Word Block	10
50000
4FFFF	32 k-Word Block	9
48000
47FFF	32 k-Word Block	8
40000
3FFFF	32 k-Word Block	7
38000
37FFF	32 k-Word Block	6
30000
2FFFF	32 k-Word Block	5
28000
27FFF	32 k-Word Block	4
20000
1FFFF	32 k-Word Block	3
18000
17FFF	32 k-Word Block	2
10000
0FFFF	32 k-Word Block	1
08000
07FFF	32 k-Word Block	0
00000
	Fig. 1 Memory Map

- 6 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800SG-L/SGH-L SmartVoltage flash memories include an on-chip WSM to manage block erase, word write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, word write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, word writing, and lock-bit configuration. All functions associated with altering memory contents — block erase, word write, lockbit configuration, status, and identifier codes — are accessed via the CUI and verified through the status register.

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, word write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data.

Interface software that initiates and polls progress of block erase, word write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write

data from/to blocks other than that which is suspended. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location.

2.1Data Protection

Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, word writes, or lock-bit configurations are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface.

When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, word write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1Read

Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component : CE#, OE#, WE#,

- 7 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 13 illustrates read cycle.

3.2Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.

3.3Standby

CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, word write, or lockbit configuration, the device continues functioning, and consuming active power until the operation completes.

3.4Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase, word write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, word write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

- 8 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

3.5Read Identifier Codes

The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the permanent lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting.

7FFFF

		Reserved for
	78004	Future Implementation
	78003
	78002	Block 15 Lock Configuration Code
	78001
		Reserved for
	78000	Future Implementation
		Block 15
		(Blocks 2 through 14)
	0FFFF
		Reserved for
	08004	Future Implementation
	08003
	08002	Block 1 Lock Configuration Code
	08001
		Reserved for
	08000	Future Implementation
		Block 1
	07FFF
		Reserved for
		Future Implementation
	00004
	00003	Permanent Lock Configuration Code
	00002	Block 0 Lock Configuration Code
	00001	Device Code
	00000	Manufacture Code Block 0

Fig. 2 Device Identifier Code Memory Map

3.6Write

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Word Write command requires the command and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 14 and Fig. 15 illustrate WE# and CE# controlled write operations.

4 COMMAND DEFINITIONS

When the VPP ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2/3 on VPP enables successful block erase, word write and lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.

- 9 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

		Table 2		Bus Operations
MODE	NOTE	RP#	CE#		OE#	WE#	ADDRESS	VPP	DQ0-15	RY/BY#
Read	1, 2, 3, 8	VIH or VHH	VIL		VIL	VIH	X	X	DOUT	X
Output Disable	3	VIH or VHH	VIL		VIH	VIH	X	X	High Z	X
Standby	3	VIH or VHH	VIH		X	X	X	X	High Z	X
Deep Power-Down	4	VIL	X		X	X	X	X	High Z	VOH
Read Identifier Codes	8	VIH or VHH	VIL		VIL	VIH	See Fig. 2	X	(NOTE 5)	VOH
Write	3, 6, 7, 8	VIH or VHH	VIL		VIH	VIL	X	X	DIN	X

NOTES :

1.Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP ≤ VPPLK, memory contents can be read, but

not altered.

2.X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.

3.RY/BY# is VOL when the WSM is executing internal block erase, word write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with word write inactive), word write suspend mode, or deep power-down mode.

4.RP# at GND±0.2 V ensures the lowest deep powerdown current.

5.See Section 4.2 for read identifier code data.

6.VIH < RP# < VHH produce spurious results and should not be attempted.

7.Refer to Table 3 for valid DIN during a write operation.

8.Don’t use the timing both OE# and WE# are VIL.

- 10 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

Table 3 Command Definitions (NOTE 9)

	COMMAND	BUS CYCLES	NOTE	FIRST BUS CYCLE			SECOND BUS CYCLE
		REQ’D.		Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)	Oper (NOTE 1)	Addr (NOTE 2)	Data (NOTE 3)
	Read Array/Reset	1		Write	X	FFH
	Read Identifier Codes	≥ 2	4	Write	X	90H	Read	IA	ID
	Read Status Register	2		Write	X	70H	Read	X	SRD
	Clear Status Register	1		Write	X	50H
	Block Erase	2	5	Write	BA	20H	Write	BA	D0H
	Word Write	2	5, 6	Write	WA	40H or 10H	Write	WA	WD
	Block Erase and	1	5	Write	X	B0H
	Word Write Suspend
	Block Erase and	1	5	Write	X	D0H
	Word Write Resume
	Set Block Lock-Bit	2	7	Write	BA	60H	Write	BA	01H
	Set Permanent Lock-Bit	2	7	Write	X	60H	Write	X	F1H
	Clear Block Lock-Bits	2	8	Write	X	60H	Write	X	D0H

NOTES :

1.Bus operations are defined in Table 2.

2.X = Any valid address within the device. IA = Identifier code address : see Fig. 2.

BA = Address within the block being erased or locked. WA = Address of memory location to be written.

3.SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).

ID = Data read from identifier codes.

4.Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and permanent lock codes. See Section 4.2 for read identifier code data.

5.If the block is locked and the permanent lock-bit is not set, WP# must be at VIH or RP# must be at VHH to enable block erase or word write operations. Attempts to issue a block erase or word write to a locked block while WP# is VIH or RP# is VHH.

6.Either 40H or 10H is recognized by the WSM as the word write setup.

7.If the permanent lock-bit is set, WP# must be at VIH or RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the permanent lock-bit. If the permanent lock-bit is set, a block lock-bit cannot be set. Once the permanent lock-bit is set, permanent lock-bit reset is unable.

8.If the permanent lock-bit is set, clear block lock-bits operation is unable. The clear block lock-bits operation simultaneously clears all block lock-bits. If the permanent lock-bit is not set, the Clear Block Lock-Bits command can be done while WP# is VIH or RP# is VHH.

9.Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.

- 11 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

4.1Read Array Command

Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, word write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH.

4.2Read Identifier Codes Command

The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and permanent lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read :

Table 4 Identifier Codes

CODE	ADDRESS	DATA
Manufacture Code	00000H	00B0H
Device Code	00001H	0050H
Block Lock Configuration (NOTE 2)	XX002H (NOTE 1)
• Unlocked		DQ0 = 0
• Locked		DQ0 = 1
• Reserved for future enhancement
		DQ1-15
Permanent Lock Configuration (NOTE 2)	00003H
• Unlocked		DQ0 = 0
• Locked		DQ0 = 1
• Reserved for future enhancement
		DQ1-15

NOTES :

1.X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map.

2.Block lock status and permanent lock status are output by DQ0. DQ1-DQ15 are reserved for future enhancement.

4.3Read Status Register Command

The status register may be read to determine when a block erase, word write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH.

4.4Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or word write suspend modes.

4.5Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written,

- 12 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued.

This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that WP# = VIH or RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and WP# = VIL and RP# = VIH, SR.1 and SR.5 will be set to "1". Once permanent lock-bit is set, the blocks which have been set block lock-bit are unable to erase forever. Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.6Word Write Command

Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the

completion of the word write event by analyzing the RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command.

Reliable word writes can only occur when VCC = VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against word writes. If word write is attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write requires that the corresponding block lock-bit be cleared or, if set, that WP# = VIH or RP# = VHH. If word write is attempted when the corresponding block lock-bit is set and WP# = VIL and RP# = VIH, SR.1 and SR.4 will be set to "1". Once permanent lock-bit is set, the blocks which have been set block lock-bit are unable to write forever. Word write operations with VIH < RP# < VHH produce spurious results and should not be attempted.

4.7Block Erase Suspend Command

The Block Erase Suspend command allows block erase interruption to read or word write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency.

- 13 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word Write Suspend command (see Section 4.8), a word write operation can also be suspended. During a word write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status.

The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 5). VPP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). WP# must also remain at VIL or VIH (the same WP# level used for block erase). Block erase cannot resume until word write operations initiated during block erase suspend have completed.

also transition to VOH. Specification tWHRH1 defines the word write suspend latency.

At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the word write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Fig. 6). VPP must remain at VPPH1/2/3 (the same VPP level used for word write) while in word write suspend mode. RP# must also remain at VIH or VHH (the same RP# level used for word write). WP# must also remain at VIL or VIH (the same WP# level used for word write).

4.9Set Block and Permanent Lock-

Bit Commands

The combination of the software command sequence and hardware WP#, RP# pin provides most flexible block lock (write protection) capability. The word write/block erase operation is restricted by the status of block lock-bit, WP# pin, RP# pin and permanent lock-bit. The status of WP# pin, RP# pin and permanent lock-bit restricts the set

4.8Word Write Suspend Command block bit. When the permanent lock-bit has not

The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM suspend the word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). RY/BY# will

been set, and when WP# = VIH or RP# = VHH, the block lock bit can be set with the status of the RP# pin. When RP# = VHH, the permanent lock-bit can be set with the permanent lock-bit set command. After the permanent lock-bit has been set, the write/erase operation to the block lock-bit can never be accepted. Refer to Table 5 for the hardware and the software write protection.

Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The

- 14 -