TLE 4269
5-V Low-Drop Fixed Voltage Regulator |
TLE 4269 |
Features
●Output voltage tolerance ≤ ± 2 %
●Very low current consumption
●Early warning
●Reset output low doown to VQ = 1 V
●Overtemperature protection
●Reverse polarity proof
●Settable reset threshold
●Very low drop voltage
●Wide temperature range
●Integrated pull up resistor at logic outputs
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Type |
Ordering Code |
Package |
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TLE 4269 A |
Q67000-A9190 |
P-DIP-8-4 |
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TLE 4269 G |
Q67006-A9173 |
P-DSO-8-1 (SMD) |
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▼ |
TLE 4269 GM |
Q67006-A9288 |
P-DSO-14-4 (SMD) |
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TLE 4269 GL |
Q67006-A9192 |
P-DSO-20-6 (SMD) |
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▼ New type |
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Functional Description
This device is a voltage regulator with a fixed 5-V output, e.g. in a P-DSO-8-1 package. The maximum operating voltage is 45 V. The output is able to drive a 150 mA load. It is short circuit protected and the thermal shutdown switches the output off if the junction temperature is in excess of 150 °C. A reset signal is generated for an output voltage of VQ < 4.6 V. The reset threshold voltage can be decreased by external connection of a voltage divider. The reset delay time can be set by an external capacitor. Reset and sense output have integrated pull up resistors. If the integrated resistors are not desired TLE 4279 can be used. It is also possible to supervise the input voltage by using an integrated comparator to give a low voltage warning.
P-DIP-8-4
P-DSO-8-1
P-DSO-20-6
P-DSO-14-4
Semiconductor Group |
1 |
1998-11-01 |
TLE 4269
Pin Configuration
(top view)
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P-DIP-8-4 |
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P-DSO-8-1 |
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Ι |
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Ι |
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1 |
8 |
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Q |
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1 |
8 |
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Q |
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S Ι |
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2 |
7 |
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SO |
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RE |
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3 |
6 |
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R |
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S Ι |
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2 |
7 |
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SO |
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3 |
6 |
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R |
D |
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4 |
5 |
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GND |
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RE |
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AEP01668 |
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D |
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4 |
5 |
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GND |
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AEP01813 |
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Pin Definitions and Functions (TLE 4269 A and TLE 4269 G)
Pin No. |
Symbol |
Function |
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1 |
I |
Input; block directly to GND on the IC with a ceramic capacitor. |
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SI |
Sense Input; if not needed connect to Q. |
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3 |
RE |
Reset Threshold; if not needed connect to ground. |
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4 |
D |
Reset Delay; to select delay time, connect to GND via external |
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capacitor. |
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5 |
GND |
Ground |
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6 |
R |
Reset Output; the open-collector output is internally linked to Q |
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via a 20 kΩ pull-up resistor. |
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7 |
SO |
Sense Output; the open-collector output is internally linked to the |
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output via a 20 kΩ pull-up resistor. |
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8 |
Q |
5-V Output; connect to GND with a 10 µF capacitor, ESR < 10 Ω. |
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Semiconductor Group |
2 |
1998-11-01 |
TLE 4269
Pin Configuration
(top view)
P-DSO-14-4
RE |
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14 |
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SI |
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D |
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2 |
13 |
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Ι |
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GND |
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3 |
12 |
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GND |
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GND |
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4 |
11 |
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GND |
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GND |
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5 |
10 |
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GND |
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GND |
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6 |
9 |
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Q |
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R |
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7 |
8 |
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SO |
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AEP02248 |
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Pin Definitions and Functions (TLE 4269 GM)
Pin No. |
Symbol |
Function |
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1 |
RE |
Reset Threshold; if not needed connect to GND. |
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2 |
D |
Reset Delay; connect to GND via external delay capacitor for |
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setting delay time. |
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3, 4, 5, 6 |
GND |
Ground |
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7 |
R |
Reset Output; open-collector output, internally connected to Q |
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via a pull-up resistor of 20 kΩ. |
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8 |
SO |
Sense Output; open-collector output, internally connected to Q |
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via a 20 kΩ pull-up resistor. |
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9 |
Q |
5-V Output; connect to GND with a 10 µF capacitor, ESR < 10 Ω. |
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10, 11, 12 |
GND |
Ground |
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13 |
I |
Input; block to GND directly at the IC by a ceramic capacitor. |
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14 |
SI |
Sense Input; if not needed connect to Q. |
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Semiconductor Group |
3 |
1998-11-01 |
TLE 4269
Pin Configuration
(top view)
P-DSO-20-6
RE |
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20 |
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SΙ |
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D |
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2 |
19 |
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Ι |
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N.C. |
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3 |
18 |
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N.C. |
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GND |
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4 |
17 |
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GND |
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GND |
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5 |
16 |
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GND |
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GND |
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6 |
15 |
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GND |
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GND |
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7 |
14 |
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GND |
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N.C. |
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8 |
13 |
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N.C. |
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N.C. |
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9 |
12 |
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Q |
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R |
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10 |
11 |
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SO |
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AEP01802 |
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Pin Definitions and Functions (TLE 4269 GL)
Pin No. |
Symbol |
Function |
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1 |
RE |
Reset Threshold; if not needed connect to GND. |
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2 |
D |
Reset Delay; to select delay time connect to GND via external |
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capacitor. |
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4-7, 14-17 |
GND |
Ground |
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10 |
R |
Reset Output; the open-collector output is internally linked to |
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Q via 20 kΩ pull-up resistor. |
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11 |
SO |
Sense Output; the open-collector output is internally linked to |
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Q via 20 kΩ pull-up resistor. |
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12 |
Q |
Output; connect to GND with a 10 µF capacitor, ESR < 10 Ω. |
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19 |
I |
Input; block directly to GND at the IC by a ceramic capacitor. |
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20 |
SI |
Sense Input; if not needed connect to Q. |
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Semiconductor Group |
4 |
1998-11-01 |
TLE 4269
Circuit Description
The control amplifier compares a reference voltage, made highly accurate by resistance balancing, with a voltage proportional to the output voltage and drives the base of the series PNP transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element.
In the reset generator block a comparator compares a reference voltage independent of the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V the reset delay capacitor is discharged and the reset output is set to low. This low is guaranteed down to an output voltage of 1 V. As the output voltage increases again, from 4.6 V onward the reset delay capacitor is charged with constant current. When the capacitor voltage reaches the upper switching threshold VdT, the reset returns to high. By choosing the value of this capacitor, the reset delay time can be selected over a wide range. With the reset threshold input RE it is possible to lower the reset threshold Vrt. If pin RE is connected to pin Q via a voltage divider, for example, the reset condition is reached when this voltage is decreased below the switching threshold Vre of 1.35 V.
Another comparator compares the signal of the pin SI, normally fed by a voltage divider from the input voltage, with the reference and gives an early warning on the pin SO. It is also possible to superwise an other voltage e.g. of a second regulator, or to build a watchdog circuit with few external components.
Application Description
The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor CQ is necessary for the stability of the regulating circuit. Stability is guaranteed at values ≥ 10 µF and an ESR ≤ 10 Ω within the operating temperature range. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted.
Semiconductor Group |
5 |
1998-11-01 |
TLE 4269
Ι |
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Q |
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Error |
20 kΩ |
20 kΩ |
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Amplifier |
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Reference |
Current and |
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Saturation |
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Control |
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Trimming |
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D |
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R |
RE |
Reference |
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SO |
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SI |
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AEB01669 |
Block Diagram
Semiconductor Group |
6 |
1998-11-01 |
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