NSC LP3985ITLX-5.0, LP3985ITLX-4.8, LP3985IBLX-5.0, LP3985IBLX-3.3, LP3985IBLX-3.1 Datasheet

June 2003

LP3985

Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS

Voltage Regulator

General Description

The LP3985 is designed for portable and wireless applications with demanding performance and space requirements.

The LP3985 is stable with a small 1µF ±30% ceramic or high-quality tantalum output capacitor. The micro SMD requires the smallest possible PC board area - the total application circuit area can be less than 2.0mm x 2.5mm, a fraction of a 1206 case size.

The LP3985’s performance is optimized for battery powered systems to deliver ultra low noise, extremely low dropout voltage and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life.

An optional external bypass capacitor reduces the output noise without slowing down the load transient response. Fast start-up time is achieved by utilizing an internal power-on circuit that actively pre-charges the bypass capacitor.

Power supply rejection is better than 50 dB at low frequencies and starts to roll off at 1kHz. High power supply rejection is maintained down to low input voltage levels common to battery operated circuits.

The device is ideal for mobile phone and similar battery powered wireless applications. It provides up to 150 mA, from a 2.5V to 6V input. The LP3985 consumes less than 1.5µA in disable mode and has fast turn-on time less than 200µs.

The LP3985 is available in a 5 bump small bump micro SMD, a 5 bump large bump micro SMD, a 5 bump thin micro SMD and a 5 pin SOT-23 package. Performance is specified for −40˚C to +125˚C temperature range and is available in 2.5V,

2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V. 3.1V, 3.2V, 3.3V, 4.7V, 4.8V and 5.0V output voltages. For other output voltage options between 2.5V to 5.0V or for a dual LP3985, please contact National Semiconductor sales office.

Key Specifications

n2.5 to 6.0V input range

n150mA guaranteed output

n50dB PSRR at 1kHz @ VIN = VOUT + 0.2V

n≤1.5µA quiescent current when shut down

nFast Turn-On time: 200 µs (typ.)

n100mV maximum dropout with 150mA load

n30µVrms output noise (typ) over 10Hz to 100kHz

n−40 to +125˚C junction temperature range for operation

n2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V, 3.2V, 3.3V, 4.7V, 4.8V and 5.0V outputs standard

Features

nMiniature 5-I/O micro SMD and SOT-23-5 package

nLogic controlled enable

nStable with ceramic and high quality tantalum capacitors

nFast turn-on

nThermal shutdown and short-circuit current limit

Applications

nCDMA cellular handsets

nWideband CDMA cellular handsets

nGSM cellular handsets

nPortable information appliances

Typical Application Circuit

10136402

Note: Pin Numbers in parenthesis indicate micro SMD package. * Optional Noise Reduction Capacitor.

Regulator Voltage CMOS Dropout-Low Ultra Noise-Low 150mA Micropower, LP3985

© 2003 National Semiconductor Corporation

DS101364

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LP3985

Block Diagram

				10136401
Pin Description
	Name	* micro SMD	SOT	Function
	VEN	A1	3	Enable Input Logic, Enable High
	GND	B2	2	Common Ground
	VOUT	C1	5	Output Voltage of the LDO
	VIN	C3	1	Input Voltage of the LDO
	BYPASS	A3	4	Optional Bypass Capacitor for Noise
				Reduction

* The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.

Connection Diagrams

SOT 23-5 Package (MF)

5 Bump micro SMD Package (BPA05, BLA05, TLA05)

10136407

Top View

See NS Package Number MF05A

10136470

Top View

See NS Package Number BPA05, BLA05, TLA05

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Ordering Information

BP refers to 0.170mm bump size, 0.900mm height for micro SMD Package

	Output	Grade	LP3985 Supplied as 250	LP3985 Supplied as 3000
	Voltage (V)		Units, Tape and Reel	Units, Tape and Reel
	2.5	STD	LP3985IBP-2.5	LP3985IBPX-2.5
	2.6	STD	LP3985IBP-2.6	LP3985IBPX-2.6
	2.7	STD	LP3985IBP-2.7	LP3985IBPX-2.7
	2.8	STD	LP3985IBP-2.8	LP3985IBPX-2.8
	2.85	STD	LP3985IBP-285	LP3985IBPX-285
	2.9	STD	LP3985IBP-2.9	LP3985IBPX-2.9
	3.0	STD	LP3985IBP-3.0	LP3985IBPX-3.0
	3.1	STD	LP3985IBP-3.1	LP3985IBPX-3.1
	3.2	STD	LP3985IBP-3.2	LP3985IBPX-3.2
	3.3	STD	LP3985IBP-3.3	LP3985IBPX-3.3
	4.7	STD	LP3985IBP-4.7	LP3985IBPX-4.7
	5.0	STD	LP3985IBP-5.0	LP3985IBPX-5.0
		BL refers to 0.300mm bump size, 0.995mm height for micro SMD Package
	Output	Grade	LP3985 Supplied as 250	LP3985 Supplied as 3000
	Voltage (V)		Units, Tape and Reel	Units, Tape and Reel
	2.5	STD	LP3985IBL-2.5	LP3985IBLX-2.5
	2.6	STD	LP3985IBL-2.6	LP3985IBLX-2.6
	2.7	STD	LP3985IBL-2.7	LP3985IBLX-2.7
	2.8	STD	LP3985IBL-2.8	LP3985IBLX-2.8
	2.85	STD	LP3985IBL-285	LP3985IBLX-285
	2.9	STD	LP3985IBL-2.9	LP3985IBLX-2.9
	3.0	STD	LP3985IBL-3.0	LP3985IBLX-3.0
	3.1	STD	LP3985IBL-3.1	LP3985IBLX-3.1
	3.2	STD	LP3985IBL-3.2	LP3985IBLX-3.2
	3.3	STD	LP3985IBL-3.3	LP3985IBLX-3.3
	4.8	STD	LP3985IBL-4.8	LP3985IBLX-4.8
	5.0	STD	LP3985IBL-5.0	LP3985IBLX-5.0
		TL refers to 0.300mm bump size, 0.600mm height for micro SMD Package
	Output	Grade	LP3985 Supplied as 250	LP3985 Supplied as 3000
	Voltage (V)		Units, Tape and Reel	Units, Tape and Reel
	2.5	STD	LP3985ITL-2.5	LP3985ITLX-2.5
	2.6	STD	LP3985ITL-2.6	LP3985ITLX-2.6
	2.7	STD	LP3985ITL-2.7	LP3985ITLX-2.7
	2.8	STD	LP3985ITL-2.8	LP3985ITLX-2.8
	2.85	STD	LP3985ITL-285	LP3985ITLX-285
	2.9	STD	LP3985ITL-2.9	LP3985ITLX-2.9
	3.0	STD	LP3985ITL-3.0	LP3985ITLX-3.0
	3.1	STD	LP3985ITL-3.1	LP3985ITLX-3.1
	3.2	STD	LP3985ITL-3.2	LP3985ITLX-3.2
	3.3	STD	LP3985ITL-3.3	LP3985ITLX-3.3
	4.8	STD	LP3985ITL-4.8	LP3985ITLX-4.8
	5.0	STD	LP3985ITL-5.0	LP3985ITLX-5.0

LP3985

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LP3985

Ordering Information		(Continued)
		For SOT Package
Output	Grade	LP3985 Supplied as 1000		LP3985 Supplied as 3000	Package Marking
Voltage (V)		Units, Tape and Reel		Units, Tape and Reel
2.5	STD	LP3985IM5-2.5		LP3985IM5X-2.5	LCSB
2.6	STD	LP3985IM5-2.6		LP3985IM5X-2.6	LCTB
2.7	STD	LP3985IM5-2.7		LP3985IM5X-2.7	LCUB
2.8	STD	LP3985IM5-2.8		LP3985IM5X-2.8	LCJB
2.85	STD	LP3985IM5-285		LP3985IM5X-285	LCXB
2.9	STD	LP3985IM5-2.9		LP3985IM5X-2.9	LCYB
3.0	STD	LP3985IM5-3.0		LP3985IM5X-3.0	LCRB
3.1	STD	LP3985IM5-3.1		LP3985IM5X-3.1	LCZB
3.2	STD	LP3985IM5-3.2		LP3985IM5X-3.2	LDPB
3.3	STD	LP3985IM5-3.3		LP3985IM5X-3.3	LDQB
4.7	STD	LP3985IM5-4.7		LP3985IM5X-4.7	LDRB
5.0	STD	LP3985IM5-5.0		LP3985IM5X-5.0	LDSB

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Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

VIN, VEN	−0.3 to 6.5V
VOUT	-0.3 to (VIN+0.3) ≤ 6.5V
Junction Temperature	150˚C
Storage Temperature	−65˚C to +150˚C
Lead Temp.	235˚C
Pad Temp. (Note 3)	235˚C
Maximum Power Dissipation
SOT23-5 (Note 4)	364mW
micro SMD (Note 4)	355mW
ESD Rating(Note 5)
Human Body Model	2kV
Machine Model	150V

Operating Ratings (Notes 1, 2)

VIN	2.5 to 6V
VEN	0 to (VIN+0.3) ≤ 6V
Junction Temperature	−40˚C to +125˚C
Thermal Resistance
θJA (SOT23-5)	220˚C/W
θJA (micro SMD)	255˚C/W
Maximum Power Dissipation
SOT23-5 (Note 6)	250mW
micro SMD (Note 6)	244mW

Electrical Characteristics

Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction

temperature range for operation, −40˚C to +125˚C. (Note 7) (Note 8)

	Symbol	Parameter	Conditions	Typ	Limit		Units
					Min	Max
		Output Voltage	IOUT = 1mA		−2	2	% of
		Tolerance			−3	3	VOUT(nom)
		Line Regulation Error	VIN = (VOUT(nom) + 0.5V) to 6.0V,
	∆VOUT		For 4.7 to 5.0 options		−0.19	0.19	%/V
			For all other options		−0.1	0.1
		Load Regulation Error	IOUT = 1 mA to 150 mA	0.0025		0.005
		(Note 9)	LP3985IM5 (SOT23-5)				%/mA
			LP3985 (micro SMD)	0.0004		0.002
		Output AC Line Regulation	VIN = VOUT(nom) + 1V,	1.5			mVP-P
			IOUT = 150 mA (Figure 1)
			VIN = VOUT(nom) + 0.2V,	50
			f = 1 kHz,
	PSRR	Power Supply Rejection Ratio	IOUT = 50 mA (Figure 2)				dB
			VIN = VOUT(nom) + 0.2V,	40
			f = 10 kHz,
			IOUT = 50 mA (Figure 2)
	IQ	Quiescent Current	VEN = 1.4V, IOUT = 0 mA
			For 4.7 to 5.0 options	100		165
			For all other options	85		150
			VEN = 1.4V, IOUT = 0 to 150 mA				µA
			For 4.7 to 5.0 options	155		250
			For all other options	140		200
			VEN = 0.4V	0.003		1.5
		Dropout Voltage (Note 10)	IOUT = 1 mA	0.4		2
			IOUT = 50 mA	20		35	mV
			IOUT = 100 mA	45		70
			IOUT = 150 mA	60		100
	ISC	Short Circuit Current Limit	Output Grounded	600			mA
			(Steady State)
	IOUT(PK)	Peak Output Current	VOUT ≥ VOUT(nom) - 5%	550	300		mA

LP3985

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LP3985

Electrical Characteristics (Continued)

Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction

temperature range for operation, −40˚C to +125˚C. (Note 7) (Note 8)

Symbol	Parameter	Conditions	Typ		Limit		Units
				Min		Max
TON	Turn-On Time	CBYPASS = 0.01 µF	200				µs
	(Note 11)
en	Output Noise Voltage(Note 12)	BW = 10 Hz to 100 kHz,	30				µVrms
		COUT = 1µF
	Output Noise Density	CBP = 0	230				nV/
IEN	Maximum Input Current at EN	VEN = 0.4 and VIN = 6.0	±1				nA
VIL	Maximum Low Level Input	VIN = 2.5 to 6.0V				0.4	V
	Voltage at EN
VIH	Minimum High Level Input	VIN = 2.5 to 6.0V		1.4			V
	Voltage at EN
COUT	Output Capacitor	Capacitance		1		20	µF
		ESR		5		500	mΩ
TSD	Thermal Shutdown Temperature		160				˚C
	Thermal Shutdown Hysteresis		20				˚C

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).

Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ - TA)/θJA,

where TJ is the junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance. The 364mW rating for SOT23-5 appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150˚C, for TJ, 70˚C for TA, and 220˚C/W for θJA. More power can be dissipated safely at ambient temperatures below 70˚C . Less power can be dissipated safely at ambient temperatures above 70˚C. The Absolute Maximum power dissipation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above 70˚C.

Note 5: The human body model is 100pF discharged through 1.5kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin.

Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating for SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125˚C, for TJ, 70˚C for TA, and 220˚C/W for θJA into (Note 4) above. More power can be dissipated at ambient temperatures below 70˚C . Less power can be dissipated at ambient temperatures above 70˚C. The maximum power dissipation for operation can be increased by 4.5mW for each degree below 70˚C, and it must be derated by 4.5mW for each degree above 70˚C.

Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25˚C or correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Note 8: The target output voltage, which is labeled VOUT(nom), is the desired voltage option.

Note 9: An increase in the load current results in a slight decrease in the output voltage and vice versa.

Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply for input voltages below 2.5V.

Note 11: Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value.

Note 12: The output noise varies with output voltage option. The 30µVrms is measured with 2.5V voltage option. To calculate an approximated output noise for other options, use the equation: (30µVrms)(X)/2.5, where X is the voltage option value.

10136408

FIGURE 1. Line Transient Input Test Signal

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