NSC MM80C97N, MM80C96J, MM80C95J, MM70C98N, MM70C98J Datasheet
...
February 1988
MM70C95/MM80C95, MM70C97/MM80C97
TRI-STATEÉ Hex Buffers
MM70C96/MM80C96, MM70C98/MM80C98
TRI-STATE Hex Inverters
General Description
These gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. The MM70C95/MM80C95 and the MM70C97/MM80C97 convert CMOS or TTL outputs to TRI-STATE outputs with no logic inversion, the MM70C96/MM80C96 and the MM70C98/MM80C98 provide the logical opposite of the input signal. The MM70C95/ MM80C95 and the MM70C96/MM80C96 have common TRI-STATE controls for all six devices. The MM70C97/ MM80C97 and the MM70C98/MM80C98 have two TRISTATE controls; one for two devices and one for the other four devices. Inputs are protected from damage due to static discharge by diode clamps to VCC and GND.
Features
Y Wide supply voltage range |
3.0V to 15V |
|
Y Guaranteed noise margin |
1.0V |
|
Y |
High noise immunity |
0.45 VCC (typ.) |
Y |
TTL compatible |
Drive 1 TTL Load |
Applications
Y Bus drivers |
Typical propagation delay |
|
into 150 pF load is 40 ns |
Connection Diagrams (Dual-In-Line Packages)
MM70C95/MM80C95 |
MM70C96/MM80C96 |
TL/F/5907 ± 1 |
TL/F/5907 ± 2 |
Top View |
Top View |
Order Number MM70C95 or MM80C95 |
Order Number MM70C96 or MM80C96 |
MM70C97/MM80C97 |
MM70C98/MM80C98 |
TL/F/5907 ± 3 |
TL/F/5907 ± 4 |
Top View |
Top View |
Order Number MM70C97 or MM80C97 |
Order Number MM70C98 or MM80C98 |
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation |
TL/F/5907 |
RRD-B30M105/Printed in U. S. A. |
Buffers Hex STATE-TRI MM70C97/MM80C97 MM70C95/MM80C95,
Inverters Hex STATE-TRI MM70C98/MM80C98 MM70C96/MM80C96,
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Voltage at Any Pin |
b0.3V to VCC a 0.3V |
Operating Temperature Range |
b55§C to a125§C |
MM70CXX |
|
MM80CXX |
b40§C to a85§C |
Storage Temperature Range |
b65§C to a150§C |
Power Dissipation (PD) |
|
Dual-In-Line |
700 mW |
Small Outline |
500 mW |
Power Supply Voltage (VCC) |
18V |
Lead Temperature |
260§C |
(Soldering, 10 seconds) |
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol |
Parameter |
|
Conditions |
Min |
Typ |
Max |
Units |
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CMOS TO CMOS |
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VIN(1) |
Logical ``1'' Input Voltage |
VCC e 5V |
3.5 |
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|
V |
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VCC e 10V |
8.0 |
|
|
V |
|
VIN(0) |
Logical ``0'' Input Voltage |
VCC e 5V |
|
|
1.5 |
V |
|
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|
VCC e 10V |
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2.0 |
V |
|
VOUT(1) |
Logical ``1'' Output Voltage |
VCC e 5V |
4.5 |
|
|
V |
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VCC e 10V |
9.0 |
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|
V |
|
VOUT(0) |
Logical ``0'' Output Voltage |
VCC e 5V |
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|
0.5 |
V |
|
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VCC e 10V |
|
|
1.0 |
V |
|
IIN(1) |
Logical ``1'' Input Current |
VCC e 15V |
|
0.005 |
1.0 |
mA |
|
IIN(0) |
Logical ``0'' Input Current |
|
|
b1.0 |
b0.005 |
|
mA |
IOZ |
Output Current in High |
VCC e 15V, VO e 15V |
|
0.005 |
1.0 |
mA |
|
|
Impedance State |
VCC e 15V, VO e 0V |
b1.0 |
b0.005 |
|
mA |
|
ICC |
Supply Current |
VCC e 15V |
|
0.01 |
15 |
mA |
|
TTL INTERFACE |
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VIN(1) |
Logical ``1'' Input Voltage |
70C |
VCC e 4.5V |
VCC b 1.5 |
|
|
V |
|
|
80C |
VCC e 4.75V |
VCC b 1.5 |
|
|
V |
VIN(0) |
Logical ``0'' Input Voltage |
70C |
VCC e 4.5V |
|
|
0.8 |
V |
|
|
80C |
VCC e 4.75V |
|
|
0.8 |
V |
VOUT(1) |
Logical ``1'' Output Voltage |
70C |
VCC e 4.5V, IO e b1.6 mA |
2.4 |
|
|
V |
|
|
80C |
VCC e 4.75V, IO e b1.6 mA |
2.4 |
|
|
V |
VOUT(0) |
Logical ``0'' Output Voltage |
70C |
VCC e 4.5V, IO e 1.6 mA |
|
|
0.4 |
V |
|
|
80C |
VCC e 4.75V, IO e 1.6 mA |
|
|
0.4 |
V |
OUTPUT DRIVE (Short Circuit Current) |
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ISOURCE |
Output Source Current |
VCC e 5V, VIN(1) e 5V |
b4.35 |
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|
mA |
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TA e 25§C, VOUT e 0V |
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ISOURCE |
Output Source Current |
VCC e 10V, VIN(1) e 10V |
b20 |
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mA |
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TA e 25§C, VOUT e 0V |
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ISINK |
Output Sink Current |
VCC e 5V, VIN(0) e 0V |
4.35 |
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mA |
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TA e 25§C, VOUT e VCC |
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ISINK |
Output Sink Current |
VCC e 10V, VIN(0) e 0V |
20 |
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mA |
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TA e 25§C, VOUT e VCC |
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Note 1: ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. Except for ``Operating Temperature Range'' they are not meant to imply that the device should be operated at these limits. The table of ``Electrical Characteristics'' provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note AN-90.
2
AC Electrical Characteristics* TA e 25§C, CL e 50 pF, unless otherwise noted.
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
|
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|
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tpd0, tpd1 |
Propagation Delay Time to a Logical ``0'' or |
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Logical ``1'' from Data Input to Output |
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MM70C95/MM80C95, MM70C97/MM80C97 |
VCC e 5V |
|
60 |
100 |
ns |
|
|
VCC e 10V |
|
25 |
40 |
ns |
|
MM70C96/MM80C96, MM70C98/MM80C98 |
VCC e 5V |
|
70 |
150 |
ns |
|
|
VCC e 10V |
|
35 |
75 |
ns |
tpd0, tpd1 |
Propagation Delay Time to a Logical ``0'' or |
|
|
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Logical ``1'' from Data Input to Output |
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MM70C95/MM80C95, MM70C97/MM80C97 |
VCC e 5V, CL e 150 pF |
|
85 |
160 |
ns |
|
|
VCC e 10V, CL e 150 pF |
|
40 |
80 |
ns |
|
MM70C96/MM80C96, MM70C98/MM80C98 |
VCC e 5V, CL e 150 pF |
|
95 |
210 |
ns |
|
|
VCC e 10V, CL e 150 pF |
|
45 |
110 |
ns |
t1H, t0H |
Delay from Disable Input to High Impedance |
RL e 10k, CL e 5 pF |
|
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|
State, (from Logical ``1'' or Logical ``0'') |
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MM70C95/MM80C95 |
VCC e 5V |
|
80 |
135 |
ns |
|
|
VCC e 10V |
|
50 |
90 |
ns |
|
MM70C96/MM80C96 |
VCC e 5V |
|
100 |
180 |
ns |
|
|
VCC e 10V |
|
70 |
125 |
ns |
|
MM70C97/MM80C97 |
VCC e 5V |
|
70 |
125 |
ns |
|
|
VCC e 10V |
|
50 |
90 |
ns |
|
MM70C98/MM80C98 |
VCC e 5V |
|
90 |
170 |
ns |
|
|
VCC e 10V |
|
70 |
125 |
ns |
tH1, tH0 |
Delay from Disable Input to Logical ``1'' Level |
RL e 10k, CL e 50 pF |
|
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|
|
(from High Impedance State) |
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MM70C95/MM80C95 |
VCC e 5V |
|
120 |
200 |
ns |
|
|
VCC e 10V |
|
50 |
90 |
ns |
|
MM70C96/MM80C96 |
VCC e 5V |
|
130 |
225 |
ns |
|
|
VCC e 10V |
|
60 |
110 |
ns |
|
MM70C97/MM80C97 |
VCC e 5V |
|
95 |
175 |
ns |
|
|
VCC e 10V |
|
40 |
80 |
ns |
|
MM70C98/MM80C98 |
VCC e 5V |
|
120 |
200 |
ns |
|
|
VCC e 10V |
|
50 |
90 |
ns |
CIN |
Input Capacitance |
Any Input (Note 2) |
|
5.0 |
|
pF |
COUT |
Output Capacitance TRI-STATE |
Any Output (Note 2) |
|
11 |
|
pF |
CPD |
Power Dissipation Capacitance |
(Note 3) |
|
60 |
|
pF |
*AC Parameters are guaranteed by DC correlated testing.
Truth Tables
MM70C95/MM80C95
Disable |
Input |
Input |
Output |
|
DIS1 |
DIS2 |
|||
|
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0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
|
0 |
1 |
X |
H-z |
|
1 |
0 |
X |
H-z |
|
1 |
1 |
X |
H-z |
|
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MM70C97/MM80C97 |
|
||
|
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|
|
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Disable |
Input |
Input |
Output |
|
DIS4 |
DIS2 |
|||
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|||
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
|
X |
1 |
X |
H-z* |
|
1 |
X |
X |
H-z** |
|
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*Output 5±6 only **Output 1±4 only X e Irrelevant
MM70C96/MM80C96
Disable |
Input |
Input |
Output |
|
DIS1 |
DIS2 |
|||
|
|
|||
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
0 |
|
0 |
1 |
X |
H-z |
|
1 |
0 |
X |
H-z |
|
1 |
1 |
X |
H-z |
|
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MM70C98/MM80C98 |
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||
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|
Disable |
Input |
Input |
Output |
|
DIS4 |
DIS2 |
|||
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|||
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
0 |
|
X |
1 |
X |
H-z* |
|
1 |
X |
X |
H-z** |
|
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3
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