Page 1
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CXD2437TQ
E96319A95-PS
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2437TQ is an IC developed to generate
the timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.
Features
• External trigger function
• Electronic shutter function
• Supports non-interlaced operation
• 12 frames/s. Double-speed readout (24 frames/s)
is also possible by mixing two vertical pixels.
• Base oscillation 40.490496MHz
Applications
Progressive Scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX085AK, ICX085AL
Absolute Maximum Ratings
• Supply voltage VDD Vss – 0.5 to +7.0 V
• Input voltage VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDD 4.75 to 5.25 V
• Operating temperature
Topr –20 to +75 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin TQFP (Plastic)
Page 2
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CXD2437TQ
Block Diagram
18
19
21
22
23
25
26
27
30
31
32
51
52
53
BUSY
CL
CLD1
CKO
WEN
ID
PBLK
XCPDM
XCPOB
XRS1
XSHD1
XSHP1
RG
XH2
XH1
XV1
XV2
XV3
V
DD
XSUB
OSCO
OSCI
V
SS
INT
XSG
ESG
TRIG
STDBY
XGRST
VD
HD
STRB
DCLK
DATA
11
13
14
RM
FSE
SMDE
36
35
34
46
47
48
56
57
58
59
61
62
4
1/2
64
CKI
2
1
20
28
33
42
54
63
10
24
29
37
41
50
55
60
3
9
6
7
8
TG
PULSE GENERATOR
REGISTER
DECODE
COUNTER
GATE
CLD2
38
39
49
40
XRS2
XSHD2
XSHP2
TEST1
TEST2
TEST3
TEST4
5
12
15
16
Pin Configuration (Top View)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
4142
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLD2
BUSY
VSS
CL
CLD1
CKO
V
DD
VSS
XGRST
STDBY
TRIG
ESG
V
SS
HD
VD
V
DD
CKI
WEN
ID
NC
NC
NC
V
DD
V
SS
XRS2
XSHD2
XSHP2
V
SS
PBLK
XCPDM
XCPOB
V
DD
XRS1
XSHD1
XSHP1
V
SS
VDD
RG
XH2
XH1
V
SS
XV1
XV2
XV3
V
DD
XSUB
XSG
CH
OSCO
OSCI
V
SS
INT
TEST1
STRB
DCLK
DATA
V
SS
V
DD
RM
TEST2
FSE
SMDE
TEST3
TEST4
Page 3
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CXD2437TQ
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
OSCO
OSCI
VSS
INT
TEST1
STRB
DCLK
DATA
VSS
VDD
RM
TEST2
FSE
SMDE
TEST3
TEST4
CH
XSG
XSUB
VDD
XV3
XV2
XV1
VSS
XH1
XH2
RG
VDD
VSS
XSHP1
XSHD1
XRS1
VDD
XCPOB
O
I
—
I
I
I
I
I
—
—
I
I
I
I
I
I
—
O
O
—
O
O
O
—
O
O
O
—
—
O
O
O
—
O
Inverter output for oscillation.
Inverter input for oscillation.
GND
Switching for base oscillation input (with pull-up resistor).
High: Oscillation provided by the internal oscillation cell, Low: CKI input valid
Test (with pull-up resistor). Fix to high.
Shutter speed setting (with pull-up resistor).
Shutter speed setting (with pull-up resistor).
Shutter speed setting (with pull-up resistor).
GND
Power supply.
Switching for frame rate (with pull-up resistor).
High: Normal readout mode, Low: Double-speed readout mode
Test (with pull-up resistor). Fix to high.
Switching for external trigger discharge operation (with pull-up resistor).
High: High-speed discharge, Low: No high-speed discharge
Switching for readout timing (with pull-up resistor).
High: ESG setting invalid, Low: ESG input valid
Test (with pull-up resistor). Fix to high.
Test (with pull-up resistor). Fix to high.
Switching for color separated pulse output (with pull-up resistor).
High: Normal pulse output mode, Low: Color separated pulse output mode
Sensor charge readout pulse output.
CCD discharge pulse output.
Power supply.
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
GND
Clock output for horizontal CCD drive.
Clock output for horizontal CCD drive.
Reset gate pulse output.
Power supply.
GND
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Power supply.
Clamp pulse output.
Symbol I/O Description
Page 4
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
– 4 –
CXD2437TQ
XCPDM
PBLK
VSS
XSHP2
XSHD2
XRS2
VSS
VDD
NC
NC
NC
ID
WEN
BUSY
CLD2
VSS
CL
CLD1
CKO
VDD
VSS
XGRST
STDBY
TRIG
ESG
VSS
HD
VD
VDD
CKI
O
O
—
O
O
O
—
—
O
O
O
O
—
O
O
O
—
—
I
I
I
I
—
I
I
—
I
Clamp pulse output.
Blanking cleaning pulse output.
GND
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Sample-and-hold pulse output.
GND
Power supply.
Line identification output.
Write enable output.
Trigger mode flag.
AD conversion pulse output.
GND
Clock output (1616fH).
AD conversion pulse output.
Clock output (3232fH).
Power supply.
GND
Resets all internal FF. Low: Reset (with pull-up resistor).
Always input one reset pulse after power–on.
Standby (with pull-up resistor).
High: Normal, Low: Internal clock supply stopped
External trigger input (with pull-up resistor).
External readout input (with pull-up resistor).
GND
Horizontal sync signal input.
Vertical sync signal input.
Power supply.
Clock input (valid when INT = low).
Pin
No.
Symbol I/O Description
Page 5
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CXD2437TQ
Electrical Characteristics
1. DC Characteristics
(VDD = 4.75 to 5.25V, Topr = –20 to +75°C)
Item
Supply voltage
Input voltage 1
(Input pins other than those listed below)
Input voltage 2
(Pin 2)
Output voltage 1
(Output pins other than those listed below)
Output voltage 2
(Pins 30, 31, 32, 38, 39, 40, 49, 51, 52 and 53)
Output voltage 3
(Pins 25, 26 and 27)
Output voltage 4
(Pin 1)
Feedback resistor
Pull-up resistor
Pull-down resistor
Current consumption
VDD
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
RFB
RPU
RPD
IDD
IOH = –2.5mA
IOL = 4.5mA
IOH = –5.0mA
IOL = 9.0mA
IOH = –7.5mA
IOL = 13.5mA
VIN = VSS or VDD
VIL = 0V
VIH = VDD
VDD = 5V
4.75
0.7VDD
0.7VDD
VDD – 0.4
VDD – 0.4
VDD – 0.4
VDD/2
5.0
1M
50k
50k
60
5.25
0.3VDD
0.3VDD
0.4
0.4
0.4
VDD/2
100k
100k
V
V
V
V
V
V
V
V
V
V
V
V
V
Ω
Ω
Ω
mA
Symbol
Conditions Min. Typ. Max. Unit
Page 6
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CXD2437TQ
2. AC Characteristics
1) Waveform characteristics of XH1, XH2 and RG
XH1
0.9VDD
0.1VDD
tWH1 tRH1tFH1
XH2
0.9VDD
0.1VDD
tWH2 tFH2tRH2
RG
0.1VDD
0.9VDD
tWRG tFRGtRRG
(VDD = 5.0V, Topr = 25°C, load capacitance of XH1 and XH2 = 30pF, load capacitance of RG = 10pF)
tRH1
tFH1
tWH1
tRH2
tFH2
tWH2
tRRG
tFRG
tWRG
XH1 rise time
XH1 fall time
XH1 low level time
XH2 rise time
XH2 fall time
XH2 high level time
RG rise time
RG fall time
RG high level time
3
3
25
3
3
25
2
2
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Definition Min. Typ. Max. Unit
Page 7
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CXD2437TQ
2) Phase characteristics of XH1, XH2, RG, XSHP, XSHD, XRS, CL, CLD and CKO
0.5VDD
tH1
0.5VDD0.5VDDXH1
XH2 0.5VDD 0.5VDD
tPD2tPD1
RG 0.5VDD
tPD3
0.5VDD
tPD4
XSHP 0.5VDD 0.5VDD
tW1 tPD5
XSHD 0.5VDD 0.5VDD
tW2 tPD6
XRS
CLD
CL
0.5VDD
0.5VDD
0.5VDD
0.5VDD
0.5VDD
0.5VDD0.5VDD
0.5VDD
tW5
tPD11
tW4
tPD7
tPD8 tPD9
tW3
tPD10
CKO
Symbol
tH1
tPD1
tPD2
tPD3
tPD4
tPD5
tPD6
tPD7
tPD8
tPD9
tPD10
XH1 cycle
XH2 falling delay, activated by the rising edge of XH1
XH2 rising delay, activated by the falling edge of XH1
XH1 falling delay, activated by the rising edge of RG
XSHP falling delay, activated by the falling edge of RG
XSHP rising delay, activated by the rising edge of XH1
XH1 falling delay, activated by the rising edge of XSHD
CLD falling delay, activated by the falling edge of XSHD
CLD falling delay, activated by the rising edge of XRS
XRS falling delay, activated by the falling edge of CLD
CL rising delay, activated by the falling edge of CLD
49.4
0
0
4
4.5
9
3
23
21.5
9
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Definition Max.Typ.Min. Unit
(VDD = 5.0V, Topr = 25°C, load capacitance of CL and CKO = 30pF,
load capacitance of CLD, XSHP, XSHD, XRS and RG = 10pF)
Page 8
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CXD2437TQ
0.5VDD
tSETUP
0.5VDD
CL 0.5VDD
HD, VD, TRIG,
ESG
t
HOLD
Symbol
tSETUP
tHOLD
HD, VD, TRIG and ESG setup time, activated by CL
HD, VD, TRIG and ESG hold time, activated by CL
6
6
ns
ns
Definition Max.Typ.Min. Unit
(VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF)
3) Phase conditions of HD, VD, TRIG and ESG
Symbol
tPD11
tW1
tW2
tW3
tW4
tW5
CKO rising delay, activated by the falling (rising) edge of XH1
XSHP pulse width
XSHD pulse width
CLD pulse width
CL pulse width
CKO pulse width
2.5
21
20
21
25
11.5
ns
ns
ns
ns
ns
ns
Definition Max.Typ.Min. Unit
3) Phase conditions of HD, VD, TRIG and ESG
0.3VDD
tWRST
0.3VDD
XGRST
(Within the recommended operating condition)
Symbol
tWRST
XGRST pulse width 50 ns
Definition Max.Typ.Min. Unit
Page 9
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CXD2437TQ
tPDCL1
0.5VDD
CL 0.5VDD0.5VDD
tPDCL2
0.5VDD
XSG, XSUB, PBLK,
XCPDM, XCPOB
XV1, XV2, XV3
BUSY, WEN, ID
tPDCL3
0.5VDD
Symbol
tPDCL1
tPDCL2
tPDCL3
XV1, XV2 and XV3 delay, activated by the falling edge of CL
BUSY, WEN and ID delay, activated by the rising edge of CL
XSG, XSUB, PBLK, XCPDM and XCPOB delay, activated by the
rising edge of CL
30
35
30
20
20
15
ns
ns
ns
Definition Max.Typ.Min. Unit
5) Phase characteristics of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID
(VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF,
load capacitance of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID = 10pF)
Page 10
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CXD2437TQ
Description of Functions
1. Progressive Scan CCD drive pulse generation
• Combining this IC with a crystal oscillator generates a fundamental frequency of 40.49MHz.
• CCD drive pulse generation is synchronized with the HD and VD inputs.
• Setting the RM pin to low sets the frame rate to double-speed readout mode (24 frames/s). However, the
CCD vertical resolution is halved.
• fCL = 1616fHD, fHD = 1044fVD (normal readout mode: RM = high)
• fCL = 1616fHD, fHD = 522fVD (double-speed readout mode: RM = low)
• The various operations are performed by the TRIG and ESG inputs. (See the following items.)
<Detection timing for VD, RM, TRIG and ESG>
1
CL
65 68
HD
XH1
Detection timing for VD,
RM, TRIG and ESG
After HD input is detected, VD, RM, TRIG and ESG are detected at the rising edge of the 65th CL pulse.
However, the low level period for each pulse should be set to 1H or longer to prevent misoperation.
2. Electronic shutter
<Shutter modes>
The electronic shutter has the following four shutter modes.
• Electronic shutter off: Exposure time is 1/12s (RM = high) or 1/24s (RM = low)
• High-speed electronic shutter: Exposure time is shorter than 1/12s (RM = high) or 1/24s (RM = low)
• Low-speed electronic shutter: Exposure time is longer than 1/12s (RM = high) or 1/24s (RM = low)
<Shutter mode and speed setting methods>
The shutter speed is set serially using the STRB, DCLK and DATA pins. The electronic shutter mode and the
meanings of the numbers indicated by D0 to 10 vary according to the SMD1 and SMD2 settings of the internal
register.
DCLK
DATA
STRB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 SMD1 SMD2
Page 11
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CXD2437TQ
SMD1
H
L
H
L
H
H
L
L
Electronic shutter off (1/12s accumulation∗1)
High-speed electronic shutter
Low-speed electronic shutter
Electronic shutter off (1/12s accumulation∗1)
—
Number of exposed lines
∗2
Number of exposed frames
∗3
—
SMD2 Mode D0 to 10
∗1
When RM = high. 1/24s accumulation when RM = low.
∗2
Relationship between the number of exposed lines and the exposure time
The relationship between the number of exposed lines and the exposure time is as follows.
(Exposure time) = (Number of exposed lines) × (One horizontal scan period) + (Accumulation time for the
readout lines)
In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for the
readout lines is the time from the rising edge of XSUB to the falling edge of XSG (510 bits). Also, the
number of exposed lines should be set to greater than 1 but less than 1043.
∗3
The number of exposed frames should be set to greater than 1 but less than 120. During external trigger
mode, the number of exposed frames should be set to greater than 2.
Timing Chart
DCLK
DATA
STRB
tWD tSDS tWS
tHDDtSDD
Symbol
tSDD
tHDD
tSDS
tWS
tWD
DATA setup time, activated by the rising edge of DCLK
DATA hold time, activated by the rising edge of DCLK
DCLK setup time, activated by the falling edge of STRB
STRB pulse width
DCLK pulse width
10
10
30
82
82
—
—
—
—
—
Min. Max.
Definition
AC characteristics for serial input
Unit
ns
ns
ns
ns
ns
Page 12
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CXD2437TQ
3. External trigger mode
External trigger mode starts exposure in sync with the external trigger input. No special pins are required to set
this mode. Note that during external trigger mode, normal readout mode results regardless of the RM status.
The IC prepares to shift to external trigger mode with the rising edge of the TRIG pin.∗1The timing to shift to
external trigger mode varies according to the mode setting. (See the table.) The BUSY pin maintains high
status during external trigger mode. Whether or not to discharge the vertical CCD charge is set by FSE just
after shifting to external trigger mode.
∗1
See the detection timing for VD, TRIG and ESG.
Mode settings during external trigger
SMD1
L
L
H
H
L
H
L
H
Trigger input is not accepted. Fix SMDE to high.
The IC is shifted to external trigger mode by HD, exposure is finished after the set time,
and XSG is output.
∗2
The IC is shifted to external trigger mode by VD and exposure is finished in sync with VD
after the set time.
∗2
Trigger input is not accepted. Fix SMDE to high
SMD2 Description of operation
∗2
The exposure time setting method is the same as the exposure time setting for the electronic shutter.
<FSE and discharge operation>
During external trigger mode, the previously exposed signal charge sometimes remains in the vertical CCD
when exposure finishes. In this case, the image shot with external trigger mode is output overlapped with the
previously shot image.
Setting FSE to high performs discharge operation for signal charges remaining in the vertical CCD after trigger
input. Discharge operation is not performed when FSE is low. This setting is only valid when using the highspeed shutter.
<Finishing the exposure period with ESG>
During external trigger mode, exposure can be finished in sync with the falling edge of ESG.∗3If SMDE is set
to low, the XSG pulse is output regardless of the electronic shutter setting, when the falling edge of ESG is
detected. ESG should be fixed to high status at all times other than during external trigger mode.
∗3
See the detection timing for VD, TRIG and ESG.
<Signal after external trigger mode>
After high-speed external trigger mode is finished, the exposure time differs from that performed by the
electronic shutter setting. This is because the start and finish of external trigger mode are not synchronized to
VD input.
4. Internal logic stop (standby mode)
When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output from
the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status of each
output pin when STDBY is low is shown below.
High: XSUB, XSG
Low: RG, XH1, XH2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN, BUSY, CLD
Not stopped: OSCO, CL, CKO
Page 13
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CXD2437TQ
5. Color separated pulse output mode
• CDS/AGC can be supported to the system which performs with 2-channel by setting CH pin to low. When
using CH pin at high, leave XSHP2, XSHD2, XRS2 and CLD2 pins open, respectivery.
• XSHP, XSHD, XRS and CLD pins operate as shown in the figure below.
Note) XSHP = XSHP1 and XSHP2, XSHD = XSHD1 and XSHD2
XRS = XRS1 and XRS2, CLD = CLD1 and CLD2
High-speed pulse when CH = low
XH1
RG
XH2
ID = H
ID = L
XH1 and 2 stop.
XH1 and 2 operations start.
XSHP1
XSHD1
XRS1
CLD1
XSHP2
XSHD2
XRS2
CLD2
XSHP1
XSHD1
XRS1
CLD1
XSHP2
XSHD2
XRS2
CLD2
R and Gr lines when ID = high
Gb and B lines when ID = low
Page 14
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CXD2437TQ
6. Mode settings
6-1. VD input-related
H X
L
H
X
SMD2 SMDEBUSY
H
L
L Invalid
Exposure is started from the first VD input.
Readout operation or the number of accumulated frames
is counted.
Readout operation is performed.
SMD1 VD input
H
L
L
H
L
H
H
L
Notes) 1. SMD1 and SMD2 indicate the corresponding internal register values.
2. See "2. Electronic shutter".
6-2. TRIG and ESG input-related
X
H
L
X
H
L
H
L
SMDEBUSY
H
L
Discharge period
∗1
Prohibited
IC shifted to external
trigger mode
∗3
Prohibited
TRIG
∗4
Prohibited
∗5
Readout operation
∗5
Prohibited
∗5
Prohibited
∗6
ESG
Exposure period
Signal output period
Before TRIG input
After TRIG
input
∗2,∗3
∗1
Only when FSE is high.
∗2
Valid only during low-speed shutter.
∗3
See "3. External trigger mode".
∗4
Do not re-input the TRIG pulse until BUSY goes low.
∗5
ESG input is valid only one time after TRIG input. Do not input ESG two times or more.
∗6
Lock ESG to high status when BUSY is low.
Page 15
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CXD2437TQ
6-3. List of Timing Charts
SMD1SMD2
RM FSE
SMDE BUSY
Timing
chart
Vertical/
Horizontal
X
L H
H L
L H
X
H
L
X
L → H
H → L
H
H
H
L
X
H
L
L
H
X
L
H H L
X X
L
X
L
X
L
H
Chart-1
Chart-2
Chart-3
Chart-4
Chart-5
Chart-6
Chart-7
Chart-8
Chart-9
Chart-10
Chart-11
Chart-12
Chart-13
Chart-14
Chart-15
Vertical
Horizontal
Vertical
Horizontal
Horizontal
Vertical
Vertical
Vertical
Vertical
Horizontal
Vertical
Vertical
Vertical
Vertical
Vertical
Normal readout
Normal readout
Double-speed readout
Double-speed readout
Readout operation
Shifting from normal readout to double-speed
readout
Shifting from double-speed readout to normal
readout
During external trigger input, discharge
During external trigger input, discharge,
double-speed
During external trigger input,
(discharge operation)
During external trigger input, no discharge
During external trigger input, no discharge,
double-speed
During external trigger input, low-speed shutter
During external trigger input, low-speed shutter,
double-speed
During external trigger input, ESG
Operation
Page 16
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CXD2437TQ
Chart-1 Normal Operation: Vertical synchronization
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
XV1
XV2
XV3
XSUB
HD
VD
OUT
5 6 7 81 21 2 3 3 4
1030
1036
1
6
1037
3
See "2. Electronic shutter" for the number of XSUB pulses.
Page 17
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CXD2437TQ
Chart-2 Normal Operation: Horizontal synchronization
XV1
XV2
XV3
RG
XSHP
XSHD
CL
HD
XSUB
XH1
XH2
XRS
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
(= High)
1616
22
59
68
87
106
144
163
300
234 276
67 322
306 321
1
68 125
0
1
1
1
1
1
1
1
1
286
Page 18
– 18 –
CXD2437TQ
Chart-3 Normal Operation, Double-speed Mode (RM = low): Vertical synchronization
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
XV1
XV2
XV3
XSUB
HD
VD
OUT
5 7
1
3
1029
519
1
4
520
2
6 8
1
2
2
3 4
1030
See "2. Electronic shutter" for the number of XSUB pulses.
Page 19
– 19 –
CXD2437TQ
Chart-4 Normal Operation, Double-speed Mode (RM = low): Horizontal synchronization
XV1
XV2
XV3
RG
XSHP
XSHD
CL
HD
XSUB
XH1
XH2
XRS
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
(= High)
1616
22 59
68
87
106
144
163
182
201
220
239
258
277
300
234 276
67 322
306 321
1
68
125
0
1
1
1
1
1
1
1
1
286
Page 20
– 20 –
CXD2437TQ
Chart-5 Readout Operation: Horizontal synchronization
Normal readout
Double-speed readout
HD
XSG
1
684
786
XV1
125
1
68
1
68
125
PBLK
1
67
1
XV3
106
868
106
1
163
1
XV2
87
144
87
144
1 1
XV1
11
125
68 182 68
125
182
239
239
XSG
11
684
786
XV2
1
87
144
201
87
144
201
258
258
1
XV3
1
868
106
163
220
106
163
220
277
1
PBLK
67 1
322
1
1
68
1
68
322
CL
Page 21
– 21 –
CXD2437TQ
Chart-6 Switching from Normal Mode (RM = high) to Double-speed Mode (RM = low)
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
XV1
XV2
XV3
XSUB
HD
VD
OUT
5 7
1
3
1
4
2
6 8
1
2
2
3 4
RM
RM is reflected from the next VD.
See "2. Electronic shutter" for the number of XSUB pulses.
Page 22
– 22 –
CXD2437TQ
Chart-7 Switching from Double-speed Mode (RM = low) to Normal Mode (RM = high)
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
XV1
XV2
XV3
XSUB
HD
VD
OUT
5 71 3
1
6
3
6 812 23 4
RM
RM is reflected from the next VD.
See "2. Electronic shutter" for the number of XSUB pulses.
Page 23
– 23 –
CXD2437TQ
Chart-8 External Trigger Mode: High-speed electronic shutter, discharge, normal readout (FSE = high, SMDE = high, RM = high)
BUSY
XSG
WEN
XCPDM
XV3
XV2
XV1
PBLK
XSUB
TRIG
VD
HD
1
76
1
5
5 6 7 81 21 2 3 3 4
OUT
RG
ID
XCPOB
1
9
1037
5 6 71 21 2 3 3 4
The number of XSUB pulses here
conforms to normal operation.
See "2. Electronic shutter" for the XSG output position.
This VD is ignored.
Page 24
– 24 –
CXD2437TQ
Chart-9 External Trigger Mode: High-speed electronic shutter, discharge, double-speed mode (FSE = high, SMDE = high, RM = low)
BUSY
XSG
WEN
XCPDM
XV3
XV2
XV1
PBLK
XSUB
TRIG
VD
HD
1
76
1
6
5 6 7 81 21 2 3 3 4
OUT
RG
ID
XCPOB
1
9
1037
5 7
1
3
6 8
1
2
2
3 4
See "2. Electronic shutter" for the XSG output position.
The number of XSUB pulses here
conforms to normal operation.
This VD is ignored.
Page 25
– 25 –
CXD2437TQ
Chart-10 External Trigger Mode: High-speed electronic shutter, when discharge starts (FSE = high)
XV1
XV2
XV3
RG
XSHP
XSHD
CL
HD
XSUB
XH1
XH2
XRS
PBLK
XCPOB
XCPDM
ID
WEN
BUSY
XSG
(= High)
1616
22 59
68
87
106
144
163
182
201
220
239
258
277
298
234 276
67
1
68
125
0
1
1
1
1
1
1
1
1
286
1 2
3
(This XV1 to XV3 operation is repeated up to 1045 times.)
Page 26
– 26 –
CXD2437TQ
Chart-11 External Trigger Mode: High-speed electronic shutter, no discharge (FSE = low, SMDE = high)
5 6 71 21 2 3 3 4
1
6
1037
5 6 7 81 21 2 3 43
BUSY
XSG
WEN
XV3
XV2
XV1
PBLK
XSUB
TRIG
HD
OUT
RG
ID
XCPOB
XCPDM
VD
The number of XSUB pulses here
conforms to normal operation.
See "2. Electronic shutter" for the XSG output position.
This VD is ignored.
Page 27
– 27 –
CXD2437TQ
Chart-12 External Trigger Mode: High-speed electronic shutter, no discharge, double-speed mode (FSE = low, SMDE = high, RM = low)
1
6
1037
5 6 7 81 21 2 3 43
BUSY
XSG
WEN
XV3
XV2
XV1
PBLK
XSUB
TRIG
HD
OUT
RG
ID
XCPOB
XCPDM
VD
5 7
1
3
6 8
1
2
2
3 4
The number of XSUB pulses here
conforms to normal operation.
See "2. Electronic shutter" for the XSG output position.
This VD is ignored.
Page 28
– 28 –
CXD2437TQ
Chart-13 External Trigger Mode: Low-speed electronic shutter (SMDE = high, RM = high)
5 6 7 81 21 2 3 3 4 5 6 7 8
1 2
1 2 3 4
1
6
1037
1
6
1037
BUSY
XSG
WEN
XV3
XV2
XV1
PBLK
XSUB
TRIG
HD
OUT
RG
ID
XCPOB
XCPDM
VD
3
See "2. Electronic shutter" for the time from the XSG output after TRIG input until the next XSG output.
Page 29
– 29 –
CXD2437TQ
Chart-14 External Trigger Mode: Low-speed electronic shutter, double-speed mode (SMDE = high, RM = low)
1
6
1
6
1037
BUSY
XSG
WEN
XV3
XV2
XV1
PBLK
XSUB
TRIG
HD
OUT
RG
ID
XCPOB
XCPDM
VD
51 3 612 23 4
5 7
1
3
6 8
1
2
2
3 4
5 61 21 2 3 3 4
1
4
See "2. Electronic shutter" for the time from the XSG output after TRIG input until the next XSG output.
Page 30
– 30 –
CXD2437TQ
Chart-15 Example during ESG Input: Discharge, normal readout (FSE = high, RMDE = low, RM = high)
VD
WEN
BUSY
XCPDM
XV3
XV2
XV1
TRIG
5 6 7 81 21 2 3 3 4
OUT
RG
ID
XCPOB
HD
1
76
1
6
1037
XSUB
1
9
XSG
PBLK
ESG
5 6 71 21 2 3 3 4
The number of XSUB pulses here
conforms to normal operation.
This VD is ignored.
Page 31
– 31 –
CXD2437TQ
Application Circuit 1
CXD2437TQ
+5V
+15V
A/D Converter
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CDS/AGC
1/6 74AC04 × 3
CXD1267AN
CXD1268M × 2 ICX085AL
Digital Out
1000p
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 32
– 32 –
CXD2437TQ
Application Circuit 2
CXD2437TQ
+5V
+15V
A/D Converter
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CDS/AGC
74AC04 × 3
CXD1267AN
CXD1268M × 2 ICX085AK/AL
Digital Out
1000p
A/D Converter
CDS/AGC
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 33
– 33 –
CXD2437TQ
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
DETAIL A
64PIN TQFP (PLASTIC)
0.3g
TQFP-64P-L071
TQFP064-P-1010-AN
0.1
A
48
12.0 ± 0.4
33
M
0.08
1
16
0.5 0.2 ± 0.1
1.27 MAX
1.0 ± 0.1
0.5 ± 0.2
1.0 ± 0.2
0.1 ± 0.1
3° – 3°
+ 7°
49
64
32
17
0.125 ± 0.05
10.0 ± 0.2
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