Datasheet CXD2598Q Datasheet (Sony)

CXD2598Q

CD Digital Signal Processor with Built-in Digital Servo and DAC

Description

The CXD2598Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, 1-bit DAC and analog low-pass filter on a single chip.

Features

• All digital signal processing during playback is

performed with a single chip

• Highly integrated mounting possible due to a built-

in RAM Digital Signal Processor (DSP) Block

• Playback mode supporting CAV (Constant Angular

Velocity)

• Frame jitter free

• 0.5× to 4× continuous playback possible

• Allows relative rotational velocity readout

• Wide capture range playback mode

• Spindle rotational velocity following method

• Supports normal-speed to 4× speed playback

• Supports variable pitch playback

• The bit clock, which strobes the EFM signal, is

generated by the digital PLL.

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• Refined super strategy-based powerful error correction

C1: double correction, C2: quadruple correction

Supported during 4× speed playback

• Noise reduction during track jumps

• Auto zero-cross mute

• Subcode demodulation and Sub-Q data error detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry correction circuit

• CPU interface on serial bus

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Fine search performs track jumps with high accuracy

• Digital audio interface outputs

• Digital level meter, peak meter

• Bilingual compatible

• VCO control mode

• CD TEXT data demodulation

Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment functions

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages

Focus filter: 5 stages Digital Filter, DAC and Analog Low-Pass Filter Blocks

• DBB (digital bass boost) function

• Digital de-emphasis

• Digital attenuation

• 8fs oversampling digital filter

• Adoption of tertiary ∆∑ noise shaper

• S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB

• THD + N: 0.007% or less (master clock: 384Fs, typ.)

• Rejection band attenuation: –60dB or less

• Double-speed playback supported

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.3 to +7.0 V

• Input voltage VI –0.3 to +7.0 V

(Vss – 0.3V to VDD + 0.3V)

• Output voltage VO –0.3 to +7.0 V

(Vss – 0.3V to VDD + 0.3V)

• Storage temperature Tstg –40 to +125 °C

• Supply voltage difference

VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD and AVSS includes XVSS. Recommended Operating Conditions

• Supply voltage VDD 2.7 to 5.5 V

• Operating temperature Topr –20 to +75 °C

Note) The VDD for the CXD2598Q varies according

to the playback speed selection.

I/O Pin Capacitance

• Input capacitance CI 11 (Max.) pF

• Output capacitance CO 11 (Max.) pF

• I/O capacitance CI/O 11 (Max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

– 1 –

E97Y14-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

100 pin QFP (Plastic)

Playback speed

CD-DSP block

DAC block

4×

4.75 to 5.25

2×

3.0 to 5.5 4.5 to 5.5

1×

2.7 to 5.5 2.7 to 5.5

VDD[V]

– 2 –

CXD2598Q

Block Diagram

PWM PWM

AOUT1

AIN1 LOUT1 AOUT2

AIN2 LOUT2

3rd-Order

Noise Shaper

Over Sampling

Digital Filter

Serial-In Interface

LMUT

RMUT

XTAO

XTAI

Timing

Logic

XRST

TEST

TES1

D/A

Interface

DOUT

EFM

demodulator

Error

Corrector

32K

RAM

Digital

OUT

Sub Code Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

CPU

Interface

Servo

Auto

Sequencer

Signal Processor Block

DAC Block

PCMDI

BCK

PCMD

LRCK

C2PO

WFCK

EMPH

GFS

XUGF

XTSL

RFAC

ASYI

ASYO

BIAS

FSTIO

FILO

FILI

PCO

CLTV

MDP

PWMI

SENS DATA

XLAT

CLOK

SCOR

SBSO EXCK

Servo Block

SERVO

Interface

SCLK COUT SSTP ATSK

MIRR DFCT

FOK

MIRR DFCT FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

FFDR FRDR TFDR TRDR SFDR SRDR

RFDC

CE

TE

SE

FE

VC

IGEN

OPAmp

Analog SW

A/D

Converter

ADIO

BCKI

SYSM

LRCKI

EMPHI

WDCK

VPCO

V16M

VCTL

XPCK

C4M

SQSO

SQCK

LOCK

Digital

CLV

ASYE

SCSY

XOLT

SOCK

SOUT

MD2

– 3 –

CXD2598Q

Pin Configuration

V

DD

V

SS

SOUT

SOCK

XOLT

SQSO

SQCK

SCSY

SBSO

EXCK

XRST

SYSM

DATA

XLAT

CLOK

SENS

SCLK

ATSK

WFCK

XUGF

XPCK

GFS

C2PO

SCOR

C4M

WDCK

COUT

MIRR

V

SS

V

DD

PCMDI

PCMD

LRCKI

LRCK

VDDASYE

DOUT

MD2

V

SS

VPCO

V16M

VCTL

BIAS

AV

DD

3

PCO

FILI

FILO

CLTV

AV

SS

3

RFAC

ASYI

ASYO

AV

DD

0

IGEN

AV

SS

0

ADIO

RFDC

CE

TE

SE

FE VC XTSL TES1 TEST VSS VDD FRDR FFDR TRDR TFDR SRDR SFDR FSTIO SSTP MDP LOCK PWMI FOK DFCT

40

39

38 37 36 35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

1

81 82 83 84

88

87

86

85

89 90

100

99

98

97

96

95

94

91 92

93

BCK

BCKI

EMPH

EMPHI

XV

DD

XTAI

XTAO

XV

SS

AVDD1

AOUT1

AIN1

LOUT1

AVSS1 AVSS2

LOUT2

AIN2

AOUT2

AVDD2

RMUT

LMUT

– 4 –

CXD2598Q

Pin Description

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26

27 28 29 30 31 32 33

34

— —

O O O O

I I

O

I I I I I I

O

I

I/O

O O O O O O

O

O I/O I/O

—

— I/O I/O

I

I/O

—

— 1, 0 1, 0 1, 0 1, 0

1, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

1, 0 1, 0

—

— 1, 0 1, 0

1, 0

Digital power supply. Digital GND. Servo block internal serial data output. Servo block internal serial data readout clock output. Servo block internal serial data latch output. Sub-Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. GRSCOR resynchronization input. Sub P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. MNT0 or RFCK is output by switching with the command. XPCK output. MNT1 is output by switching with the command. GFS output. MNT2 or XROF is output by switching with the command. C2PO output. MNT3 or GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected.

4.2336MHz output. In CAV-W mode and variable pitch mode, the 1/4 frequency division of V16M is output.

Word clock output f = 2Fs. GRSCOR is output by switching with the command. Track count signal input/output. Mirror signal input/output. Digital GND. Digital power supply. Defect signal input/output. Focus OK signal input/output. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS

is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1.

VDD VSS SOUT SOCK XOLT SQSO SQCK SCSY SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR

C4M WDCK

COUT MIRR VSS VDD DFCT FOK PWMI

LOCK

Symbol I/O Description

– 5 –

CXD2598Q

35 36 37 38 39 40 41 42 43 44 45 46 47

48 49

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

O

I

I/O

O O O O O

O — —

I I

I I I I I

O —

I

—

O

I I

—

I

O

I

O —

I I

1, Z, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

— —

Analog

—

1, 0

—

Analog

1, Z, 0

—

Spindle motor servo control output. Disc innermost track detection signal input. Input/output of 2/3 frequency division for the XTAI pin. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital power supply. Digital GND. Test pin. Normally, GND. Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the

crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test pin. Do not connect anything. Analog GND. Operational amplifier constant current input. Analog power supply. EFM full-swing output (low = VSS, high = VDD). Asymmetry comparator voltage input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Analog power supply. Asymmetry circuit constant current input. Wide-band EFM PLL VCO2 control voltage input.

MDP SSTP FSTIO SFDR SRDR TFDR TRDR FFDR FRDR VDD VSS TEST TES1

XTSL VC

FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI RFAC AVSS3 CLTV FILO FILI PCO AVDD3 BIAS VCTL

Pin No.

Symbol I/O Description

– 6 –

CXD2598Q

70 71

72 73 74 75 76 77 78 79 80 81 82

83

84 85

86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

I/O

O

—

I

O

I

—

O

I

O

I

O

I

O

I

O

—

O

I

O

— —

O

I

O

—

O O

1, 0

1, Z, 0

—

1, 0

—

1, 0

—

— —

— 1, 0 1, 0

Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL clock input by switching with the command.

Wide-band EFM PLL charge pump output. Digital GND. Digital Out on/off control (low = off, high = on). Digital Out output. Asymmetry circuit on/off (low = off, high = on). Digital power supply. D/A interface. LR clock output f = Fs. D/A interface. LR clock input. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) D/A interface. Bit clock output. D/A interface. Bit clock input. Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis. Inputs a high signal when emphasis is on, and a low signal when emphasis

is off. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND. Analog power supply. Left channel analog output. Left channel operational amplifier input. Left channel LINE output. Analog GND. Analog GND. Right channel LINE output. Right channel operational amplifier input. Right channel analog output. Analog power supply. Right channel zero detection flag. Left channel zero detection flag.

V16M VPCO

VSS MD2 DOUT ASYE VDD LRCK LRCKI PCMD PCMDI BCK BCKI

EMPH

EMPHI XVDD

XTAI XTAO XVSS AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT

Pin No.

Symbol I/O Description

– 7 –

CXD2598Q

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window opens.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.

Monitor Pin Output Combinations

Command bit

Output data

MTSL1

MTSL0

XUGF

XPCK

GFS

C2PO

MNT0

MNT1

MNT2

MNT3

RFCK

XPCK

XROF

GTOP

0 0 1

0 1 0

– 8 –

CXD2598Q

Electrical Characteristics

1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Input voltage (1)

Input voltage (2)

Input voltage (3)

Input voltage (4) Output voltage

(1) Output voltage

(2) Output voltage

(3) Output voltage

(4)

Input leak current (1)

Input leak current (2) Input leak current (3)

Input leak current (4)

∗1, ∗11

∗2, ∗12

∗3

∗4, ∗9, ∗10

∗5

∗6

∗7

∗1, ∗2

∗3, ∗11, ∗12 ∗9

∗10

∗8

Schmitt input

Analog input IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –6mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VIN = VSS

or VDD VIN = VSS

or VDD VI = 1.5 to 3.5V VI = 0 to 5.0V

High level input voltage Low level input voltage High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage

VIH (1) VIL (1) VIH (2) VIL (2) VIH (3) VIL (3) VIN (4) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) VOH (4) VOL (4)

ILI (1)

ILI (2) ILI (3)

ILI (4)

0.7VDD

0.8VDD

Vss

VDD – 0.8

Vss

VDD – 0.8

Vss

VDD – 0.8

Vss

VDD – 0.5

Vss –10

–40 –20

–40

0.3VDD

0.2VDD

0.2VDD VDD VDD

0.4

VDD

0.4

VDD

0.4

VDD

0.4 10

40 20

600

V V V V V V V V V V V V V V V

µA

µA µA

µA

Conditions Min. Typ. Max. Unit

Applicable pins

∗1

SYSM, DATA, XLAT, PWMI, SSTP, XTSL, TEST, TES1, MD2, SCSY

∗2

SQCK, XRST, CLOK, ASYE

∗3

LRCKI, PCMDI, BCKI, EMPHI

∗4

ASYI, RFAC, CLTV, FILI, VCTL

∗5

SQSO, SBSO, SENS, ATSK, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTIO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SOUT, SOCK, XOLT

∗6

V16M

∗7

MDP, PCO, VPCO

∗8

FILO

∗9

VC, FE, SE, TE, CE

∗10

RFDC

∗11

EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK, PWMI, V16M, FSTIO

∗12

SCLK

– 9 –

CXD2598Q

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(b) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(c) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Oscillation frequency fMAX 7 34 MHz

Item Symbol Min. Typ. Max. Unit

High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time

tWHX

13

500

ns

tWLX

13 500

ns

tCX

26 1000

ns

VIHX

VDD – 1.0

V

VILX 0.8

V

tR, tF

10

ns

Item Symbol Min. Typ. Max. Unit

Input amplitude VI 2.0 VDD + 0.3 Vp-p

Item Symbol Min. Typ. Max. Unit

tR tF

tWHX

tWLX

tCX

VILX

VIHX × 0.1

V

IHX × 0.9

V

IHX

XTAI

V

DD/2

– 10 –

CXD2598Q

(2) CLOK, DATA, XLAT, SQCK and EXCK pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (during input)

∗

COUT pulse width (during input)

∗

fCK

tWCK tSU tH tD tWL

fT

tWT

fT

tWT

750 300 300 300 750

750

7.5

0.65

65

MHz

ns ns ns ns ns

MHz

ns

kHz

µs

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT tWT

tH

tSU

CLOK

DATA

XLAT

EXCK SQCK COUT

SBSO SQSO

∗

Only when $44 and $45 are executed.

– 11 –

CXD2598Q

(3) BCKI, LRCKI and PCMDI pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

BCK pulse width PCMDI setup time PCMDI hold time LRCK setup time

tW tSU tH tSU

ns ns ns ns

Item Symbol

Conditions

Typ. 94 18 18 18

Min.

Max. Unit

VDD/2 VDD/2

tW(BCKI) tW(BCKI)

tSU

(PCMDI)

t

H

(PCMDI)

tSU

(LRCKI)

BCKI

PCMDI

LRCKI

(4) SCLK pin

SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16 MHz

ns µs

Item Symbol Min. Typ. Max. Unit

tSPWtDLS

1/fSCLK

MSB LSB· · ·

· · ·

XLAT

SCLK

Serial Read Out Data

(SENS)

– 12 –

CXD2598Q

(5) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency

fCOUT fMIRR fDFCTH

40 40

5

kHz kHz kHz

∗1 ∗2 ∗3

Item Symbol Min. Typ. Max. Max.

Conditions

∗1

When using a high-speed traverse TZC.

∗2

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.12VDD to 0.26VDD

• ≤ 25%

∗3

During complete RF signal omission. When settings related to DFCT signal generation are Typ.

A

B

A + B

– 13 –

CXD2598Q

1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)

Item

Total harmonic distortion

Signal-to-noise ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data (Using A-weighting filter)

384Fs 768Fs 384Fs 768Fs

96 96

0.0050

0.0045 100 100

0.0070

0.0065

Min.

Typ.

Max.

Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

680p

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD2598Q

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Output voltage Load resistance

VOUT RL

∗1 ∗1

Vrms

kΩ

Item Symbol

8

Min.

Max.

1.12

Typ.

Applicable pinsUnit

∗

Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB.

Applicable pins

∗1

LOUT1, LOUT2

Block diagram of analog characteristics measurement

LPF external circuit diagram

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

– 14 –

CXD2598Q

Contents

§1. CPU Interface

§1-1. CPU Interface Timing ..........................................................................................................................15

§1-2. CPU Interface Command Table ..........................................................................................................15

§1-3. CPU Command Presets ......................................................................................................................26

§1-4. Description of SENS Signals...............................................................................................................32

§1-5. Description of Commands ...................................................................................................................34

§2. Subcode Interface

§2-1. P to W Subcode Readout....................................................................................................................62

§2-2. 80-bit Sub-Q Readout..........................................................................................................................62

§3. Description of Modes

§3-1. CLV-N Mode........................................................................................................................................69

§3-2. CLV-W Mode.......................................................................................................................................69

§3-3. CAV-W Mode.......................................................................................................................................69

§3-4. VCO-C mode.......................................................................................................................................70

§4. Description of Other Functions

§4-1. Channel Clock Recovery by Digital PLL Circuit...................................................................................73

§4-2. Frame Sync Protection........................................................................................................................75

§4-3. Error Correction...................................................................................................................................75

§4-4. DA Interface.........................................................................................................................................76

§4-5. Digital Out............................................................................................................................................78

§4-6. Servo Auto Sequence..........................................................................................................................82

§4-7. Digital CLV...........................................................................................................................................90

§4-8. CD-DSP Block Playback Speed..........................................................................................................91

§4-9. DAC Block Playback Speed ................................................................................................................91

§4-10. DAC Block Input Timing ....................................................................................................................92

§4-11. Description of DAC Block Functions..................................................................................................92

§4-12. LPF Block ..........................................................................................................................................97

§4-13. Asymmetry Correction.......................................................................................................................98

§4-14. CD TEXT Data Demodulation ...........................................................................................................99

§5. Description of Servo Signal Processing System Functions and Commands

§5-1. General Description of Servo Signal Processing System..................................................................101

§5-2. Digital Servo Block Master Clock (MCK)...........................................................................................102

§5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...........................................................103

§5-4. E:F Balance Adjustment Function .....................................................................................................104

§5-5. FCS Bias Adjustment Function..........................................................................................................104

§5-6. AGCNTL Function .............................................................................................................................106

§5-7. FCS Servo and FCS Search .............................................................................................................108

§5-8. TRK and SLD Servo Control .............................................................................................................109

§5-9. MIRR and DFCT Signal Generation..................................................................................................110

§5-10. DFCT Countermeasure Circuit........................................................................................................111

§5-11. Anti-Shock Circuit............................................................................................................................111

§5-12. Brake Circuit....................................................................................................................................112

§5-13. COUT Signal ...................................................................................................................................113

§5-14. Serial Readout Circuit......................................................................................................................113

§5-15. Writing to Coefficient RAM ..............................................................................................................114

§5-16. PWM Output....................................................................................................................................114

§5-17. Servo Status Changes Produced by LOCK Signal ........................................................................115

§5-18. Description of Commands and Data Sets .......................................................................................115

§5-19. List of Servo Filter Coefficients........................................................................................................137

§5-20. Filter Composition............................................................................................................................139

§5-21. TRACKING and FOCUS Frequency Response ..............................................................................145

§6. Application Circuit...................................................................................................................................146

Explanation of abbreviations

AVRG: Average TRK: Tracking AGCNTL: Auto gain control SLD: Sled FCS: Focus DFCT: Defect

– 15 –

CXD2598Q

§1. CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• The internal registers are initialized by a reset when XRST = 0.

§1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7 8 9 A

B C D E

8 bits

8 to 24 bits

16 bits 20 bits 32 bits 32 bits 28 bits 24 bits 28 bits 20 bits 20 bits

Total bit length

750ns or more

D18 D19 D20 D21 D22 D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

D0 D1

– 16 –

CXD2598Q

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN

NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

1

0

1

0

—

0

1

—

0

—

1

0

—

0

1

—

0

1

—

0

1

—

1

0

—

0

1

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Command Table ($0X to 1X)

—: Don’t care

– 17 –

CXD2598Q

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(±1 × basic value) (Default)

SLED KICK LEVEL

(±2 × basic value)

SLED KICK LEVEL

(±3 × basic value)

SLED KICK LEVEL

(±4 × basic value)

0

1

—

0

1

0

1

0

1

—

0

1

0

1

—

0

1

—

0

1

0

1

—

2

3

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Register

Command

Address

D23 to D20

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

—: Don’t care

Command Table ($2X to 3X)

– 18 –

CXD2598Q

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($340X)

– 19 –

CXD2598Q

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($341X)

– 20 –

CXD2598Q

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

NOT USED

KRAM DATA (K2F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($342X)

– 21 –

CXD2598Q

KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TGup2)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

NOT USED

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($343X)

– 22 –

CXD2598Q

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when THSK = 1 TGup2)

KRAM DATA (K47)

NOT USED

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

NOT USED

KRAM DATA (K4F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 1 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($344X)

– 23 –

CXD2598Q

0

1

0

PGFS, PFOK, RFAC

DOUT

Booster Surf Brake

Booster

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

PGFS1

A/D

SEL

SFBK1

THBON

0

1

0

PGFS0

COPY

EN

SFBK2

FHBON

0

1

0

RFOK1

EMPH

D

0

TLB1ON

0

FBL9

FB9

TV9

RFOK0

CAT

b8

0

FLB1ON

0

FBL8

FB8

TV8

0

DOUT

EN1

0

TLB2ON

0

FBL7

FB7

TV7

0

DOUT

DMUT

0

FBL6

FB6

TV6

0

DOUT

WOD

0

HBST1

0

FBL5

FB5

TV5

0

WIN

EN

0

HBST0

0

FBL4

FB4

TV4

0

DOUT

EN2

0

LB1S1

0

FBL3

FB3

TV3

0

LB1S0

0

FBL2

FB2

TV2

0

LB2S1

0

FBL1

FB1

TV1

0

LB2S0

0

—

TV0

SELECT

Register

Command

Address 1

D23 to D20

D19

D18 D17 D16

Address 2

D15

D15 D14

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 2

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Command Table ($348X to 34FX)

—: Don’t care

0 0 1 1

– 24 –

CXD2598Q

FCS search, AGF

TRK jump, AGT

FZC, AGC, SLD move

DC measure, cancel

Serial data read out

FCS Bias, Gain,

Surf jump/brake

Mirr, DFCT, FOK

TZC, Cout, Bottom, Mirr

SLD filter

Filter

Clock, others

3

FT1

TDZC

FZSH

VCLM

DAC

0

SFO2

COSS

SFID

F1NM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

COTS

SFSK

F1DM

AGG4

FS5

TJ5

SM5

FLM

SD5

FBSS

SDF2

CETZ

THID

F3NM

XT4D

FS4

TJ4

SM4

FLC0

SD4

FBUP

SDF1

CETF

THSK

F3DM

XT2D

FS3

TJ3

SM3

RFLM

SD3

FBV1

MAX2

COT2

0

TINM

0

FS2

TJ2

SM2

RFLC

SD2

FBV0

MAX1

COT1

TLD2

TIUM

DRR2

FS1

TJ1

SM1

AGF

SD1

0

SFOX

MOT2

TLD1

T3NM

DRR1

FS0

TJ0

SM0

AGT

SD0

TJD0

BTF

0

TLD0

T3UM

DRR0

FTZ

SFJP

AGS

DFSW

0

FPS1

D2V2

BTS1

0

DF1S

0

FG6

TG6

AGJ

LKSW

0

FPS0

D2V1

BTS0

0

TLCD

ASFG

FG5

TG5

AGGF

TBLM

0

TPS1

D1V2

MRC1

0

FTQ

FG4

TG4

AGGT

TCLM

0

TPS0

D1V1

MRC0

0

LKIN

LPAS

FG3

TG3

AGV1

FLC1

0

RINT

0

COIN

0

FG2

TG2

AGV2

TLC2

0

SJHD

0

MDFI

0

FG1

TG1

AGHS

TLC1

0

INBK

0

MIRI

AGHF

FG0

TG0

AGHT

TLC0

0

MTI0

0

XT1D

ASOT

SELECT

Register

Command

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

0 0 1 1

Command Table ($35X to 3FX)

– 25 –

CXD2598Q

Auto sequence

Blind (A, E),

Brake (B),

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

AS3

TR3

SD3

32768

CD-

ROM

1

VARI

ON

32768

Gain

MDP1

0

CM3

AS2

TR2

SD2

16384

DOUT

Mute

DSPB

ON/OFF

VARI

USE

16384

Gain

MDP0

TB

CM2

AS1

TR1

SD1

8192

DOUT

Mute-F

ASEQ

ON/OFF

Mute

8192

Gain

MDS1

TP

CM1

AS0

TR0

SD0

4096

WSEL

1

ATT

4096

Gain

MDS0

CLVS

Gain

CM0

MT3

0

KF3

2048

VCO

SEL1

BiliGL

MAIN

PCT1

2048

Gain

DCLV1

VP7

EPWM

MT2

0

KF2

1024

ASHS

BiliGL

SUB

PCT2

1024

Gain

DCLV0

VP6

SPDC

MT1

0

KF1

512

SOCT0

FLFC

MCSL

512

PCC1

VP5

ICAP

MT0

0

KF0

256

VCO

SEL2

XWOC

SOC2

256

PCC0

VP4

SFSL

LSSL

0

128

KSL3

DAC

EMO

DCOF

128

SFP3

VP3

VC2C

0

64

KSL2

DAC

ATT

FMUT

64

SFP2

VP2

HIFC

0

32

KSL1

SYCOF

BSBST

32

SFP1

VP1

LPWR

0

16

KSL0

0

BBST

16

SFP0

VP0

VPON

—

8

0

PLM3

ATTCH

SEL

8

SRP3

VP

CTL1

Gain

CAV1

—

4

0

PLM2

ATD10

4

SRP2

VP

CTL0

Gain

CAV0

—

2

XVCO2

THRU

PLM1

ATD9

2

SRP1

0

—

1

0

PLM0

ATD8

1

SRP0

0

INV

VPCO

4

5

6

7

8

9

A

B

C

D

E

Register

Command

Address

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1 Data 2 Data 3 Data 4

Command Table ($4X to EX)

—: Don’t care

– 26 –

CXD2598Q

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(±1 × basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0

1

0

—

0

1

2

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Register

Command

3 SELECT

Address

D23 to D20

0 0 1 1

0 0 1 1 0 1 0 0 0

See "Coefficient ROM Preset Values Table".

0 0 0 0 — — — — — — — — — — — — — — — —

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D0 D0

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Address 3

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D0 D0

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

—: Don’t care

MODE

specification

1 0 0 08

Function

specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

1 0 0 1

1 0 1 0

1 0 1 1

9

A

B

C

Register

Command

Address Data 1

Data 2

Data 3

Data 4

—: Don’t care

ERC4

SCOR

SEL

SCSY SOCT1 TXON

TXOUT OUTLI OUTL0

DAC

SMUTL

ATD7

0

EDC7

DAC

SMUTR

ATD6

LRMIX

EDC6

ZMUT

ATD5

MTSL1

EDC5

ZDPL

ATD4

MTSL0

EDC4

0

ATD3

—

EDC3

0

ATD2

—

EDC2

0

ATD1

—

EDC1

0

ATD0

—

EDC0

D3 D2 D1 D0 D3 D2 D1 D0

Data 5 Data 6

FSTIN 0 OUTL2 0

DIV4 0 0 0

D3 D2 D1 D0

Data 7

Command Table ($4X to EX) cont.

– 27 –

CXD2598Q

Command Preset Table ($348X to 34FX)

0010

PGFS, PFOK, RFAC

DOUT

Booster Surf Brake

Booster

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 2

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

0 0 1 1

– 28 –

CXD2598Q

FCS search, AGF

TRK jump, AGT

FZC, AGC, SLD move

DC measure, cancel

Serial data read out

FCS Bias, Gain,

Surf jump/brake

Mirr, DFCT, FOK

TZC, Cout, Bottom, Mirr

SLD filter

Filter

Clock, others

3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SELECT

Register

Command

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

0 0 1 1

Command Preset Table ($35X to 3FX)

– 29 –

CXD2598Q

Auto sequence

Blind (A, E),

Brake (B),

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence (N)

track jump count

setting

MODE

specification

Function

specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

1

0

—

0

1

0

—

0

1

0

—

0

1

0

1

0

4

5

6

7

8

9

A

B

C

D

E

Register

Command

Address

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1 Data 2 Data 3 Data 4

Command Preset Table ($4X to EX)

—: Don’t care

MODE specification

Function specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

8

9

A

B

C

Register

Command

Address Data 1

Data 2

Data 3

Data 4

D3 D2 D1 D0 D3 D2 D1 D0

Data 5 Data 6

0

—

0

—

0

—

0

—

0

D3 D2 D1 D0

Data 7

0

– 30 –

CXD2598Q

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A

K0B K0C K0D K0E K0F

E0

81 23 7F

6A

10 14 30 7F 46 81

1C

7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E K2F

4E

32 20 30 80 77 80 77 00 F1 7F

3B

81 44 7F

5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81

3A

7F 66 82

44 4E 1B

00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

∗

Fix indicates that normal preset values should be used.

– 31 –

CXD2598Q

ADDRESS

K30 K31 K32 K33 K34 K35 K36 K37 K38

K39 K3A K3B K3C K3D K3E K3F

80 66 00 7F

6E

20 7F

3B

80 44 7F 77 86

0D

57 00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED

K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F

04 7F 7F 79 17

6D

00 00 02 7F 7F 79 17 54 00 00

TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

– 32 –

CXD2598Q

§1-4. Description of SENS Signals

SENS output

Microcomputer serial register (latching not required)

$0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X,

DX, FX

Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z

GFS

COMP

COUT

OV64

Z

FZC

AS

TZC

SSTP

AGOK

∗

XAVEBSY

∗

TE Avrg Reg. FE Avrg Reg. VC Avrg Reg.

TRVSC Reg.

FB Reg.

RFDC Avrg Reg.

FBIAS Count STOP

SSTP

XBUSY

FOK

0

GFS

COMP

COUT

OV64

0

— — — — —

— 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits

—

ASEQ = 0 ASEQ = 1 Output data length

∗

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

– 33 –

CXD2598Q

Description of SENS Signals

The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin.

High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set by Reg.B.

High when Reg.B is latched, low when COUT is counted for the initial Reg.B number. Counts the number of tracks set by Reg.B.

High when Reg.B is latched, toggles each time COUT is counted for the Reg.B number. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number.

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter.

Z XBUSY

FOK GFS COMP

COUT

OV64

SENS output

– 34 –

CXD2598Q

§1-5. Description of Commands

The meaning of the data for each address is explained below.

$4X commands

Register name

4

Data 1

Command

Data 2

MAX timer value

Data 3

Timer range

AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 0

Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move

0 0 0 1 1 1 1

0 1 1 0 0 1 1

0 0 1 0 1 0 1

0

RXF

1 RXF RXF RXF RXF

AS3 AS2 AS1 AS0

RXF = 0 Forward RXF = 1 Reverse

• When the Focus-On command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track Jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence

is interrupted.

• To disable the MAX timer, set the MAX timer value to 0.

$5X commands

MAX timer value

MT3

23.2ms

1.49s

11.6ms

0.74s

5.8ms

0.37s

2.9ms

0.18s

0 1

0 0

MT2 MT1 MT0 LSSL 0 0 0

Timer range

Timer TR3 TR2 TR1

TR0

Blind (A, E), Overflow (C, G) Brake (B)

0.18ms

0.36ms

0.09ms

0.18ms

0.045ms

0.09ms

0.022ms

0.045ms

– 35 –

CXD2598Q

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 2152142132122112102928272625242322212

0

Auto sequence track jump count setting

This command is used to set N when a 2N-track jump is executed, M when an M-track move is executed and the jump count when fine search is executed for auto sequence.

• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system.

• When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted.

$7X commands

Auto sequence track jump count setting

$6X commands

Register name

6

Data 1

KICK (D)

Data 2

KICK (F)

SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0

Timer SD3 SD2 SD1 SD0

When executing KICK (D) $44 or $45

When executing KICK (D) $4C or $4D

23.2ms

11.6ms

5.8ms

2.9ms

1.45ms

Timer KF3 KF2 KF1 KF0

KICK (F) 0.72ms 0.36ms 0.18ms 0.09ms

– 36 –

CXD2598Q

∗

See mute conditions (1) and (3) to (5) under $AX commands for other mute conditions.

MD2

Other mute conditions

∗

DOUT Mute

DOUT Mute F

DOUT output

OFF

0dB

–∞dB

DA output for 48-bit slot

0dB

–∞dB

0dB

–∞dB

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Command

Data 1

MODE specification

CD-

ROM

DOUT

Mute

DOUT

Mute-F

WSEL

D3 D2 D1 D0

Data 2

VCO

SEL1

ASHS SOCT0

VCO

SEL2

D3 D2 D1 D0

$8X commands

Command bit DOUT Mute = 1 DOUT Mute = 0

When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted.

Processing

Command bit DOUT Mute F = 1 DOUT Mute F = 0

When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off.

Processing

Command bit

CDROM = 1 CDROM = 0

C2PO timing

1-3 1-3

CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed.

Processing

– 37 –

CXD2598Q

Command bit

Processing VCOSEL1 = 0 VCOSEL1 = 1

Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed.

Command bit

KSL3 KSL2

Processing

Output of multiplier PLL VCO1 is 1/1 frequency-divided. Output of multiplier PLL VCO1 is 1/2 frequency-divided. Output of multiplier PLL VCO1 is 1/4 frequency-divided. Output of multiplier PLL VCO1 is 1/8 frequency-divided.

0 0 1 1

0 1 0 1

See above.

Command

Data 2

MODE specification

VCO

SEL1

ASHS SOCT0

VCO

SEL2

D3 D2 D1 D0

Data 3

KSL3 KSL2 KSL1 KSL0

D3 D2 D1 D0

Command bit

Sync protection window width WSEL = 1 WSEL = 0

±26 channel clock

±6 channel clock

Anti-rolling is enhanced. Sync window protection is enhanced.

Application

∗

In normal-speed playback, channel clock = 4.3218MHz.

Command bit

Function ASHS = 0 ASHS = 1

The command transfer rate from the auto sequencer to the DSSP block is set to normal speed. The command transfer rate from the auto sequencer to the DSSP block is set to half speed.

∗

See "§4-8. CD-DSP Block Playback Speed" for settings.

Command bit

SOCT0 SOCT1

Processing

Sub-Q is output from the SQSO pin. Various signals are output from the SQSO pin. Input the readout clock to SQCK.

(See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK.

(See Timing Chart 2-6.)

0 1

1

—

0

1

—: Don't care

– 38 –

CXD2598Q

Command bit

Processing VCOSEL2 = 0 VCOSEL2 = 1

Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed.

Command bit

KSL1 KSL0

Processing

Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided. Output of wide-band PLL VCO2 is 1/4 frequency-divided. Output of wide-band PLL VCO2 is 1/8 frequency-divided.

0 0 1 1

0 1 0 1

D3

0 0

VCO2 THRU

0 ERC4

SCOR

SEL

SCSY SOCT1 TXON TXOUT OUTL1 OUTL0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 4 Data 5 Data 6

Command

MODE specification

Command bit

VCO2 THRU = 0

Processing

V16M is output. Wide-band EFM PLL clock can be input from the V16M pin.

∗

This command sets internal or external connection for the VCO2 used during CAV-W mode and variable pitch mode.

VCO2 THRU = 1

Command bit

Processing ERC4 = 0 ERC4 = 1

C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1.

Command bit

Processing SCOR SEL = 0 SCOR SEL = 1

WDCK signal is output. GRSCOR (protected SCOR) is output.

∗

Used when outputting GRSCOR from the WDCK pin.

See the previous page.

– 39 –

CXD2598Q

Command bit

TXON = 0

Processing

When CD TEXT data is not demodulated, set TXON to 0. When CD TEXT data is demodulated, set TXON to 1.

∗

See "§4-14. CD TEXT Data Demodulation".

TXON = 1

Command bit

Processing

SCSY = 0 SCSY = 1

No processing. GRSCOR (protected SCOR) synchronization is applied again.

∗

Used to resynchronize GRSCOR.

The rising edge signal of this command bit is used internally, so when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR is the crystal accuracy SCOR signal obtained by removing the motor wow component. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (Same as when SCSY = 1 is sent by the $8X command.)

Command bit

TXOUT = 0

Processing

Various signals except for CD TEXT are output from the SQSO pin. CD TEXT data is output from the SQSO pin.

∗

See "§4-14. CD TEXT Data Demodulation".

TXOUT = 1

Command bit

OUTL1 = 0

Processing

XPCK, C4M, WDCK and FSTO are output. V16M is output when VCO2 THRU = 0.

XPCK, C4M, WDCK and FSTO outputs are set to low. V16M output is set to low when VCO2 THRU = 0.

OUTL1 = 1

Command bit

OUTL0 = 0 OUTL0 = 1

Processing

PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are set to low.

– 40 –

CXD2598Q

Command

Data 1

Function specification

1

DSPB

ON-OFF

A.SEQ

ON-OFF

1

D3 D2 D1 D0

Data 2

BiliGL

MAIN

BiliGL

SUB

FLFC

D3 D2

D1

XWOC

D0

$9X commands

Command bit

DSPB = 0 DSPB = 1

Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1)

Processing

FLFC is normally 0. Set FLFC to 1 in CAV-W mode for any playback speed.

Command bit BiliGL SUB = 0 BiliGL SUB = 1

STEREO

SUB

MAIN

Mute

BiliGL MAIN = 0 BiliGL MAIN = 1

Definition of bilingual capable MAIN, SUB and STEREO

The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels, respectively, for STEREO.

Command bit

Processing

FSTIN = 0

FSTIN = 1

Servo block clock switching uses the internal connection. (Preset) The clock with 2/3 frequency division for the XTLO pin is input to the servo block. The FSTIO pin functions as an output pin for monitoring the servo block clock.

Servo block clock switching uses external input. The FSTIO pin functions as an input pin. Input the servo block clock from the FSTIO pin.

Command bit

Processing OUTL2 = 0 OUTL2 = 1

WFCK is output. WFCK is set to low.

Command

MODE specification

Data 7

FSTIN 0 OUTL2 0

D3 D2 D1 D0

– 41 –

CXD2598Q

Command

Data 3

Function specification

DAC

EMPH

DAC

ATT

SYCOF 0

D3 D2 D1 D0

Command bit DAC EMPH = 1 DAC EMPH = 0

Applies digital de-emphasis. The emphasis constants are τ1 = 50µs and τ 2 = 15µs when Fs = 44.1kHz.

Turns digital de-emphasis off.

Processing

Command bit

DAC ATT = 1

DAC ATT = 0

Identical digital attenuation control is used for both the left and right channels. When common attenuation data is specified, the attenuation values for the left channel are used.

Independent digital attenuation control is used for the left and right channels.

Processing

∗

This is used to resynchronize the DAC.

Command bit

Processing DAC sync window opens. DAC sync window does not open.

XWOC = 0 XWOC = 1

Command bit

SYCOF = 1 SYCOF = 0

LRCK asynchronous mode. Normal operation.

Processing

∗

Set SYCOF = 0 in advance when setting the XWOC command of $9 to 0.

– 42 –

CXD2598Q

PLM3

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Mute

L

R

L + R

Mute

L

R

L + R

Mute

L

R

L + R

Mute

L

R

L + R

Mute Mute Mute Mute

L L L

L R R R R

L + R L + R L + R L + R

Mute

Reverse

Stereo

Mono

PLM2 PLM1 PLM0 Left channel output Right channel output Remarks

Note) The output data of L + R is (L + R)/2 to prevent overflow.

Command

Data 4

Function specification

PLM3 PLM2 PLM1 PLM0

D3 D2 D1 D0

• DAC play mode By controlling these command bits, the DAC output left channel and right channel can be output in 16 different combinations of left (L) channel, right (R) channel, left + right (L + R) channel, and mute. The relationship between the commands and the outputs is shown in the table below.

– 43 –

CXD2598Q

Command

Data 5

Function specification

DAC

SMUTL

DAC

SMUTR

ZMUT ZDPL

D3 D2 D1 D0

Command bit DAC SMUTL = 1 DAC SMUTL = 0

Left channel soft mute is on. Left channel soft mute is off.

Processing

Command bit

DAC SMUTR = 1 DAC SMUTR = 0

Right channel soft mute is on. Right channel soft mute is off.

Processing

Command bit

ZMUT = 1 ZMUT = 0

Zero detection mute is on. Zero detection mute is off.

Processing

Command bit

ZDPL = 1 ZDPL = 0

LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted.

Processing

∗

See "Mute flag output" for the mute flag output conditions.

Command

Data 6

Function specification

0 0 0 0

D3 D2 D1 D0

Data 7

DIV4 0 0 0

D3 D2 D1 D0

Command bit

DIV4 = 0 DIV4 = 1

Digital PLL master clock, conventional mode. (Preset) Digital PLL master clock, 2/3 mode.

Processing

This switches the digital PLL master clock. Either the conventional mode or the 2/3 mode (2/3 of the conventional clock) can be selected.

Note) Do not set DIV4 = 1 when DSPB = 0.

– 44 –

CXD2598Q

Command

Data 1

Audio CTRL

VARI

ON

VARI

USE

Mute ATT

D3 D2 D1 D0

Data 2

PCT1 PCT2

D3 D2

MCSL SOC2

D1 D0

$AX commands

Command bit

Mute = 0

Mute = 1

Mute off if other mute conditions are not set.

Mute on. Peak register reset.

Meaning

Command bit

ATT = 0 ATT = 1

Attenuation off. –12dB

Meaning

Mute conditions

(1) When register A mute = 1. (2) When Digital Out is on (MD2 pin = 1) and register 8 DOUT Mute F = 1. (3) When GFS stays low for 35 ms or more (during normal-speed). (4) When register 9 BiliGL MAIN = Sub = 1. (5) When register A PCT1 = 1 and PCT2 = 0.

(1) to (3) perform zero-cross muting with a 1ms time limit.

Command bit

PCT1

0 0 1 1

PCT2

0 1 0 1

Normal mode Level meter mode Peak meter mode Normal mode

× 0dB × 0dB

Mute

× 0dB

C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double

Meaning PCM Gain

ECC error correction ability

Description of level meter mode (see Timing Chart 1-4.)

• When the LSI is set to this mode, it performs digital level meter functions.

• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.

The initial 80 bits are Sub-Q data (see "§2. Subcode Interface"). The last 16 bits are LSB first, and consist of 15-bit PCM data (absolute values) and an L/R flag. The final bit (L/R flag) is high when the PCM data is from the left channel and low when the data is from the right channel.

• The PCM data is reset and the L/R flag is reversed after one readout. Then the maximum value is measured until the next readout.

Command bit

VARION = 0

Processing

Variable pitch mode is off. (The internal clock uses the crystal reference.) Variable pitch mode is on. (The internal clock uses the VCO2 reference.)VARION = 1

Command bit

VARIUSE = 0

Processing Set VARIUSE = 0 when not using variable pitch mode. Set VARIUSE = 1 when using variable pitch mode.

∗

See "$DX commands" for the variable pitch range and example of use.

VARIUSE = 1

– 45 –

CXD2598Q

Description of peak meter mode (see Timing Chart 1-5.)

• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the

left or right channel. The 96-bit clock must be input to SQCK to read out this data.

• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is reset in the LSI internal register. In other words, the PCM maximum value register is not reset by the readout.

• To reset the PCM maximum value register, set PCT1 = PCT2 = 0 or set the Mute command of $AX to 1.

• The Sub-Q absolute time is automatically controlled in this mode.

In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time.

• The final bit (L/R flag) of the 96-bit data is normally 0.

• The pre-value hold and average value interpolation data are fixed to level (–∞) for this mode.

SENS output switching

• This command is used to output the SQSO pin signal from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin.

Note) SOC2 should be switched when SQCK = SCLK = high.

Command bit

SOC2 = 0 SOC2 = 1

The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin.

Processing

Command bit

MCSL = 1 MCSL = 0

DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)

Processing

Note) See "§4-9. DAC Block Playback Speed".

– 46 –

CXD2598Q

Command

Data 3

Audio CTRL

DCOF FMUT BSBST BBSL

D3 D2 D1 D0

Command bit

DCOF = 1 DCOF = 0

DC offset is off. DC offset is on.

Processing

Command bit

FMUT = 1 FMUT = 0

Forced mute is on. Forced mute is off.

Processing

Command bit

BSBST = 1 BSBST = 0

Bass boost is on. Bass boost is off.

Processing

Command bit

BBSL = 1 BBSL = 0

Bass boost is Max. Bass boost is Mid.

Processing

∗

Set DC offset to off when zero detection mute is on.

– 47 –

CXD2598Q

Data 4

D3

ATTCH

SEL

ATD10

ATD9 ATD8 ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0

Audio CTRL

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 5 Data 6

Attenuation data

400h 3FFh

3FEh

:

001h 000h

0dB

–0.0085dB

–0.017dB

:

–60.206dB

–∞

Audio output

The attenuation data consists of 11 bits each for the left and right channels, and the DAC ATT bit can be used to control the left and right channels with common attenuation data. When common attenuation data is specified, the left channel attenuation values are used.

The audio output from 001h to 400h is obtained using the following equation:

Audio output = 20 log [dB]

Command bit ATTCH SEL = 1 ATTCH SEL = 0

Right channel attenuation data can be set. Left channel attenuation data can be set.

Processing

Command bit

ATD10 to 0 Attenuation data.

Meaning

Attenuation data

1024

Command

– 48 –

CXD2598Q

$BX commands

This command sets the traverse monitor count.

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 2152142132122112102928272625242322212

0

Traverse monitor count setting

• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off.

• The traverse monitor count is set to monitor the traverse status using the SENS outputs COMP and COUT.

Command bit

MTSL1 MTSL0

Output data

XUGF MINT0

RFCK

XPCK MNT1 XPCK

GFS MNT2 XROF

C2PO MNT3

GTOP

0 0 1

0 1 0

Command

Data 5

Traverse monitor count setting

0

LRMIX

MTSL1 MTSL0

D3 D2 D1 D0

The monitor output is set as follows.

Command bit

LRMIX = 0

LRMIX = 1

LMUT and RMUT both operate normally. The AND signal of the left channel and right channel zero detection flags is output from

the LMUT pin. The OR signal of the left channel and right channel zero detection flags is output from the RMUT pin.

Processing

– 49 –

CXD2598Q

Spindle servo coefficient setting

CLV CTRL ($DX)

Gain

MDP1

Gain

MDP0

Gain

MDS1

Gain

MDS0

Gain

CLVS

Gain

MDS1

0 0 0 0 1 1

Gain

MDS0

0 0 1 1 0 0

Gain

CLVS

0 1 0 1 0 1

GCLVS

–12dB

–6dB –6dB

0dB 0dB

+6dB

Command

D3

Data 1

D2

D1

D0

Gain

DCLV0

Gain

DCLV1

PCC1

PCC0

D3

Data 2

D2

D1

D0

$CX commands

• CLVS mode gain setting: GCLVS

Gain

MDP1

0 0 1

Gain

MDP0

0 1 0

GMDP

–6dB

0dB

+6dB

Gain

DCLV1

0 0 1

Gain

DCLV0

0 1 0

GDCLV

0dB

+6dB

+12dB

Gain

MDS1

0 0 1

Gain

MDS0

0 1 0

GMDS

–6dB

0dB

+6dB

• CLVP mode gain setting: GMDP: GMDS

• DCLV overall gain setting: GDCLV

Command bit

PCC1 PCC0

Processing

The VPCO signal is output. The VPCO pin output is high impedance. The VPCO pin output is low. The VPCO pin output is high.

0 0 1 1

0 1 0 1

• This command controls the VPCO pin signal.

The VPCO output can be controlled with this setting.

– 50 –

CXD2598Q

Command

Data 3

D3

SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0

Spindle servo coefficient setting

D2 D1 D0 D3 D2 D1 D0

Data 4

∗

See "§4-2. Frame Sync Protection" regarding frame sync protection.

Command bit

SRP3 to 0 Sets the frame sync backward protection times. The setting range is 1 to F (Hex).

Processing

Command bit

SFP3 to 0 Sets the frame sync forward protection times. The setting range is 1 to F (Hex).

Processing

• The CXD2598Q can serially output the 40 bits (10 BCD codes) of error monitor data selected by EDC0 to EDC7 from the SQSO pin and monitor this data using a microcomputer. The C1 and C2 error rate settings are sent one at a time by the $C commands by setting the SOCT0 and SOCT1 commands of $8 to 1. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses.

Command

Data 5

D3

EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0

Spindle servo coefficient setting

D2 D1 D0 D3 D2 D1 D0

Data 6

– 51 –

CXD2598Q

$DX commands

See "$CX commands".

Command bit

TB = 0 TB = 1 TP = 0 TP = 1

Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

Description

Command

Data 1

CLV CTRL 0 TB TP

Gain

CLVS

D3 D2 D1 D0

Command bit

EDC7 = 0 EDC6

EDC5 EDC4 EDC3 EDC2 EDC1

EDC0

EDC7 = 1 EDC6

EDC5 EDC4 EDC3 EDC2 EDC1 EDC0

The [No C1 errors, pointer reset] count is output when 0. The [One C1 error corrected, pointer reset] count is output when 0. The [No C1 errors, pointer set] count is output when 0. The [One C1 error corrected, pointer set] count is output when 0. The [Two C1 errors corrected, pointer set] count is output when 0. The [C1 correction impossible, pointer set] count is output when 0. 7350-frame count cycle mode∗1when 1.

73500-frame count cycle mode∗2when 0. The [No C2 errors, pointer reset] count is output when 0. The [One C2 error corrected, pointer reset] count is output when 0. The [Two C2 errors corrected, pointer reset] count is output when 0. The [Three C2 errors corrected, pointer reset] count is output when 0. The [Four C2 errors corrected, pointer reset] count is output when 0. The [C2 correction impossible, pointer copy] count is output when 0. The [C2 correction impossible, pointer set] count is output when 0.

Processing

Error monitor commands

∗1

The value selected by C1 (EDC1 to EDC6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350 frames.

∗2

The value selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) is added to C1 and C2 and output every 73500 frames.

– 52 –

CXD2598Q

The rotational velocity R of the spindle can be expressed with the following equation.

R = × l

256 – n

32

∗

The above setting should be 0, 0 when not operating in the CAV-W mode.

Command bit

VPCTL1 VPCTL0

Processing

The setting of VP0 to VP7 is multiplied by 1. The setting of VP0 to VP7 is multiplied by 2. The setting of VP0 to VP7 is multiplied by 3. The setting of VP0 to VP7 is multiplied by 4.

0 0 1 1

0 1 0 1

Command

Data 2

CLV CTRL VP7 VP6 VP5 VP4

D3 D2 D1 D0

Data 3

VP3 VP2 VP1 VP0

D3 D2 D1 D0

Data 4

VP

CTL1VPCTL0

0 0

D3 D2 D1 D0

Command bit

Processing

VP0 to 7 Sets the spindle rotational velocity.

R: Relative velocity at normal speed = 1 n: VP0 to VP7 setting value 1: Multiple set by VPCTL0, 1

Command bit

VP0 to 7 = F0(H)

VP0 to 7 = E0(H)

VP0 to 7 = C0(H)

Playback at half (normal) speed

to

Playback at normal (double) speed

to

Playback at (quadruple) speed

Description

Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.

2. Values in parentheses are for when DSPB is 1.

F0 E0

0.5

1

1.5

2

R – Relative velocity [multiple]

VP0 to VP7 setting value [HEX]

D0

2.5

3

C0

3.5

4

DSPB = 0

DSPB = 1

The settings in CAV-W mode are as follows.

… …

– 53 –

CXD2598Q

Command bit

Processing

VPCTL1 to 0, VP7 to 0 Sets the pitch for the variable pitch mode.

The settings in variable pitch mode are as follows.

The pitch setting can be expressed with the following equation.

P = [%]

–n 10

P: Pitch setting value n: VPCTL1 and VPCTL0, VP7 to VP0 setting value

(two's complement, VPCTL1 = sign bit)

The pitch setting range is from –48.7 to +51.2%. The plus pitch setting should not exceed the playback speed given in the Recommended Operating Conditions.

An example of variable pitch mode commands is shown below.

$A4XXXXX (Setting to enable variable pitch mode.) $ACXXXXX (Turns on variable pitch mode. The internal clock uses the VCO2 reference.) $D60A00 (Sets the pitch to +1.0%.) $D60000 (Sets the pitch to 0.0%.) $A4XXXXX (Turns off variable pitch mode. The internal clock uses the crystal reference.)

VPCTL1

1

0

VPCTL0

0

1

0

1

VP7 to 0

00(H)

:

FF(H)

00(H)

:

FF(H)

00(H)

:

FF(H)

00(H)

:

E7(H)

Pitch setting value [%]

+51.2

to +25.7 +25.6

to

+0.1

0.0 to

–25.5 –25.6

to

–48.7

Command setting example

$D60080

:

$D6FF80

$D600C0

:

$D6FFC0

$D60000

:

$D6FF00

$D60040

:

$D6E740

Command bit

– 54 –

CXD2598Q

$EX commands

Command

Data 1

SPD mode CM3 CM2 CM1 CM0

D3 D2 D1 D0

Data 2

EPWM SPDC ICAP SFSL

D3 D2 D1 D0

Data 3

VC2C HIFC LPWR VPON

D3 D2 D1 D0

Command bit

CM3 CM2 CM1

Description

Spindle stop mode.

∗1

Spindle forward rotation mode.

∗1

Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.

∗1

Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range.

PLL servo mode. Automatic CLVS/CLVP switching mode.

Used for normal playback.

0 1

1

1 0

0 0

0

1

1 1

0 0

1

1 1

CM0

0 0

0

1 0

Mode

STOP

KICK

BRAKE

CLVS

CLVP CLVA

∗1

See Timing Charts 1-6 to 1-12.

When using the digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. This means that the CLVS mode cut-off frequency fc is 70Hz when the TB command of $D = 0 or 140Hz when the TB command of $D = 1.

Command bit

EPWM SPDC ICAP

Description

Crystal reference CLV servo. Used for normal-speed

playback in CLV-W mode.

∗2

Spindle control with VP0 to VP7.

Spindle control with the external PWM.

VCO control

∗3

0 0

0

1 0

0 0

1

0 0

1

1 0

SFSL

0 0

0

0 0

VC2C

0 1

0

0 0

HIFC

0 1

1

1 1

LPWR

0 0

0

0 0

VPON

0 0

1

1 1

INV

VPCO

0 0

0

0 1

Mode

CLV-N

CLV-W

CAV-W

CAV-W VCO-C

∗2

Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.

∗3

Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.

– 55 –

CXD2598Q

Mode

CLV-N

CLV-W

CAV-W

LPWR

0

1

0

1

Command

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b)

1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c)

Timing chart

Mode

CLV-N

CLV-W

CAV-W

LPWR

0 0 1 0 1 0 1

1-11 1-12

1-13 1-14 (EPWM = 0) 1-15 (EPWM = 0) 1-16 (EPWM = 1) 1-17 (EPWM = 1)

Timing chart

Command

SPD mode

Data 4

• This sets the gain when controlling the spindle with VP0 to VP7 in CAV-W mode.

Note) This setting is not valid when controlling the spindle with

the external PWM.

D3 D2 D1 D0

Gain

CAV1

Gain

CAV0

0

INV

VPCO

Gain

CAV1

0 0 1 1

Gain

CAV0

0 1 0 1

Gain

0dB

–6dB –12dB –18dB

See the previous page.

– 56 –

CXD2598Q

Timing Chart 1-3

Rch 16bit C2 Pointer Lch 16bit C2 Pointer

If C2 Pointer = 1,

data is NG

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Rch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Lch C2 Pointer

LRCK

WDCK

CDROM = 0

C2PO

CDROM = 1

C2PO

48 bit slot

– 57 –

CXD2598Q

Timing Chart 1-4

Level Meter Timing

96 clock pulses

WFCK

1 2 3

96 clock pulses

CRCF CRCF

1 2 3

Peak data of this section

16 bit

R/LL/R

96 bit data

Hold section

1 2 3 80 81 96

CRCF

SQCK

D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R

Peak data

L/R flag

Sub Q Data

See "Sub Code Interface"

15-bit peak-data

Absolute value display, LSB first

750ns to 120µs

SQCK

SQSO

– 58 –

CXD2598Q

Timing Chart 1-5

Measurement

Peak Meter Timing

96 clock pulses

CRCF

WFCK

1 2 3

Measurement Measurement

96 clock pulses

CRCF CRCF

1 2 3

SQCK

– 59 –

CXD2598Q

Timing Chart 1-6 CLV-N mode LPWR = 0

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

(c) STOP

Z

L

Z

Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

(c) STOP

Z

L

Z

Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

Z

STOP

MDP

(c) STOP

Z

Timing Chart 1-9 CAV-W mode LPWR = 0

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

(c) STOP

Z

L

Timing Chart 1-10 CAV-W mode LPWR = 1

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

Z

STOP

MDP

(c) STOP

Z

– 60 –

CXD2598Q

Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0

MDP

Acceleration

Z

Deceleration

264kHz

3.8µs

Timing Chart 1-11 CLV-N mode LPWR = 0

MDP

Acceleration

Z

Deceleration

132kHz

7.6µs

n · 236 (ns) n = 0 to 31

Timing Chart 1-12 CLV-W mode LPWR = 0

MDP

Acceleration

Z

Deceleration

264kHz

3.8µs

Timing Chart 1-13 CLV-W mode LPWR = 1

MDP

Acceleration

Z

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1

MDP

Acceleration

Z

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

– 61 –

CXD2598Q

Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0

PWMI

MDP

H

L

H

L

Acceleration

Deceleration

Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1

PWMI

MDP

H

L

H

Z

Acceleration

The BRAKE pulse is masked when LPWR = 1.

– 62 –

CXD2598Q

§2. Subcode Interface

There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high.

§2-1. P to W Subcode Readout

Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)

§2-2. 80-bit Sub-Q Readout

Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register.

• First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.

• 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded.

• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.

• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others.

• The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode.

• The absolute time after peak is stored in the memory in peak meter mode as noted in "Description of peak meter mode" on page 45. See Timing Chart 2-3.

• Clock input via the SQCK pin is necessary to perform these operations. The high and low intervals for SQCK input should be between 750ns and 120µs.

– 63 –

CXD2598Q

Timing Chart 2-1

Internal PLL clock

4.3218 ± ∆MHz

WFCK

SCOR

EXCK

SBSO

750ns max

S0 · S1 Q R

WFCK

SCOR

EXCK

SBSO

S0•S1 Q R S T U V W

S0•S1

P1 Q R S T U V W P1 P2 P3

Same Same

Subcode P.Q.R.S.T.U.V.W Read Timing

– 64 –

CXD2598Q

Block Diagram 2-2

888888888

Order

Inversion

16

Peak detection

LOAD CONTROL

Ring control 2

CRCF

Mix

Monostable

multivibrator

CRCC

ABS time load control

for peak value

16 bit P/S registerRing control 1

SO SI

SQSO

SQCKSHIFTSHIFT

SUBQ

LD

SO

H G F E D C B A

A B C D E F G H

SI

80 bit P/S Register

80 bit S/P Register

(AFRAM) (ASEC) (AMIN) ADDRS CTRL

SIN

SUBQ

– 65 –

CXD2598Q

Timing Chart 2-3

1

2

3

91 92 93 94

95 96 97

98

WFCK

SCOR

SQSO

SQCK

Monostable

Multivibrator

(Internal)

CRCF1

Determined by mode

CRCF2

80 or 96 Clock

Register load forbidder

270 to 400µs when SQCK = high.

750ns to 120µs

300ns max

CRCF

ADR0

ADR1

ADR2

ADR3

CTL0

CTL1

CTL2

CTL3

SQCK

SQSO

1

2

3

CRCF1

– 66 –

CXD2598Q

Timing Chart 2-4

Example: $802000 latch

Set SQCK high during this interval.

Internal signal latch

PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH

750ns or more

XLAT

SQCK

SQSO

ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF9VF7 VF8

Signal

PER0 to 7

FOK

GFS

LOCK

EMPH

ALOCK

VF0 to 9

RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.

Focus OK.

High when the frame sync and the insertion protection timing match.

GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output.

High when the playback disc has emphasis.

GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive

samples, a low signal is output.

Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB.

Description

C1F2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No C1 errors; C1 pointer reset

One C1 error corrected; C1 pointer reset

—

No C1 errors; C1 pointer set

One C1 error corrected; C1 pointer set

Two C1 errors corrected; C1 pointer set

C1 correction impossible; C1 pointer set

C1F1 C1F0 Description

C2F2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No C2 errors; C2 pointer reset

One C2 error corrected; C2 pointer reset

Two C2 errors corrected; C2 pointer reset

Three C2 errors corrected;C2 pointer reset

Four C2 errors corrected; C2 pointer reset

—

C2 correction impossible; C1 pointer copy

C2 correction impossible; C2 pointer set

C2F1 C2F0 Description

– 67 –

CXD2598Q

Timing Chart 2-5

Measurement interval (approximately 3.8µs)

Reference window

(132.2kHz)

Measurement pulse

(V16M/2)

Measurement counter

VF0 to 9

Load

m

The relative velocity R of the disc can be expressed with the following equation.

R = (R: Relative velocity, m: Measurement results)

VF0 to VF9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low).

m + 1

32

– 68 –

CXD2598Q

Timing Chart 2-6

18 17C1 MSB 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0537005370

C1 error rate C2 error rate

XLAT

SQCK

SQSO

– 69 –

CXD2598Q

§3. Description of Modes

This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below.

§3-1. CLV-N Mode

This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is ±150kHz.

§3-2. CLV-W Mode

This is the wide capture range mode. This mode allows the conventional PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to the V16M pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode.

Note) The capture range for this mode is theoretically up to the signal processing limit.

§3-3. CAV-W Mode

This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to quadruple speed. (See "$DX commands".) When controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement is a signal of 132.3kHz obtained by 1/128-frequency dividing XTAL (XTAI, XTAO) (384Fs). The velocity is obtained by counting half of the V16M pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VF0 to VP9). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with VP0 to VP7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc.

Note) The capture range for CAV-W mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode.

– 70 –

CXD2598Q

§3-4. VCO-C Mode

This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to VP7 commands and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation.

V16M =

The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation.

• When DSPB = 0

VCO1 = V16M ×

• When DSPB = 1

VCO1 = V16M ×

49 24

1(256 – n)

32

n: VP0 to VP7 setting value 1: VPCTL0, 1 setting value

49 16

– 71 –

CXD2598Q

CAV-W

CLVS

CLV-W

CLVP

Rotational velocity

Target speed

Operation mode

Spindle mode

Time

KICK

LOCK

ALOCK

Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode

CLV-W Mode

NO

YES

KICK $E8000 Mute OFF $A00XXXX

ALOCK = H ?

NO

YES

ALOCK = L ?

CLV-W MODE

START

CAV-W $E665X

(CLVA)

CLV-W $E60CX

(CLVA)

(WFCK PLL)

Fig. 3-2. CLV-W Mode Flow Chart

– 72 –

CXD2598Q

VCO-C Mode

R?

(How many minutes

of absolute time?)

Access START

Transfer

$E00510

n?

(Caluculate n)

Transfer

$DX XX

Track Jump

Subroutine

Transfer

$E66500

Access END

What is the playback speed when access ends?

Caluculate VP0 to VP7.

Switch to VCO control mode EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1

Transfer VP0 to VP7. ( corresponds to VP0 to VP7.)

Switch to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1

Fig. 3-3. Access Flow Chart Using VCO Control

– 73 –

CXD2598Q

§4. Description of other functions

§4-1. Channel Clock Recovery by Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, the PLL is necessary to recover the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 4-1. The CXD2598Q has a built-in three-stage PLL.

• The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. The output of this first-stage PLL is used as a reference for all clocks within the LSI.

• The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.

• The third-stage PLL is a digital PLL that recovers the actual channel clock.

• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the

secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such a case, turning off the secondary loop yields better playability. However, in this case the capture range becomes ±50kHz.

• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop.

– 74 –

CXD2598Q

Block Diagram 4-1

XTSL

1/2 1/32

1/n

1/2

Microcomputer control

n = 1 to 256

(VP7 to 0)

1/K

(KSL1, 0)

CLV-W CAV-W

Spindle rotation information

CLV-N

CLV-W CAV-W

/CLV-N

Phase comparator

Selector

LPF

2/1 MUX

VPON

1/M

1/N

VCOSEL2

VCO2

Phase comparator

VCO1

VCOSEL1

1/K

(KSL3, 2)

Digital PLL

RFPLL

VPCO

VCTL

V16M

PCO

FILI

FILO

CLTV

XTAI

Clock input

1/l

l = 1, 2, 3, 4

(VPCTL0, 1)

– 75 –

CXD2598Q

§4-2. Frame sync protection

• In normal speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.

• In the CXD2598Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 13∗, and the backward protection counter to 3∗. Concretely, when the disc is being played back normally and then the frame sync cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately.

∗

Default values. These values can be set as desired by the SFP3 to SFP0 and SRP3 to SRP0 commands of $C.

§4-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.

• The CXD2598Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2.

• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status during C1 error correction, the playback status of the EFM signal, and the operating status of the player.

• The correction status can be monitored externally. See Table 4-2.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data.

MNT3

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset

—

— No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset

— C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set

MNT2 MNT1 MNT0 Description

Table 4-2.

– 76 –

CXD2598Q

Timing Chart 4-3

Normal-speed PB

400 to 500ns

RFCK

MNT3

MNT1

MNT0

t = Dependent on error

condition

C1 correction C2 correction

Strobe

MNT2

§4-4. DA Interface

• The DA interface supports the 48-bit slot interface. 48-bit slot interface

This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.

– 77 –

CXD2598Q

Timing Chart 4-4

LRCK

(44.1K)

BCK

(2.12M)

WDCK

PCMD

LRCK

(88.2K)

BCK

(4.23M)

WDCK

PCMD

48-bit slot Normal-Speed Playback

1

24

R0

Lch MSB (15)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

Lch MSB (15)

24

Rch MSB

2 3 4 5 6 7 8 9 10 11 12

48-bit slot Double-Speed Playback

1 2

L0

R0

– 78 –

CXD2598Q

§4-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2598Q supports type 2 form 1. The CXD2598Q also supports two Digital Out generation methods: generation from the PCM data read out from the disc, and generation from the DA interface input (PCMDI, LRCKI, BCKI).

§4-5-1. Digital Out from PCM Data

Digital Out is generated from the PCM data read out from the disc. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in

CAV-W mode or variable pitch mode. In addition, Sub-Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz, XTSL is high and DSPB is set to 1 in CLV-N or CLV-W mode. Therefore, set the MD2 pin to 0 and turn DOUT off.

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 /1 0 0

0

ID0

ID1

COPY

Emph

0 0 0 0 1 0 0 0 0 0 0 0

From sub Q

0

16

32

48

176

Sub Q control bits that matched twice in succession with CRCOK

Digital Out C bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

VPON or VARION: 1 Crystal: 0

bits 0 to 3 bit 29

Table 4-5-1.

– 79 –

CXD2598Q

§4-5-2. Digital Out from DA Interface Input

Digital Out is generated from the DA interface input.

Validity Flag, User Data

The Validity Flag and User Data are fixed to 0.

Channel Status Data

Bits 0, 6 and 7 of the Channel Status Data are fixed to 0. In addition, the following items can be set by bits 1, 2, 3 and 8.

a) Digital data/audio data b) Digital copy allowed/prohibited c) Pre-emphasis on/off d) Category code (2 types)

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

A/D

SEL

COPY

En

EMPH

D

0 0 0 0

CAT

b8

0 0 0 0 0 0 0

0

16

32

48

176

Digital Out C bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Table 4-5-2.

Note) When using this generation method, turn DOUT off by first setting the MD pin to 0 and then setting the

DOUT EN command of $34A to 0.

– 80 –

CXD2598Q

Digital audio data input

The digital audio data input signal is input from the DAC input pins PCMDI, LRCKI and BCKI. The input format supports the 48-bit slot, MSB first.

Mute function

The audio data portion of the Digital Out output can be set to all zero without altering the Channel Status Data by setting command bit DOUT_DMUT to 1.

I/O sync circuit

The DAC is automatically synchronized to the input LRCK during normal operation, but synchronization may not be possible when the input data contains a large amount of jitter or during power-on, etc. In such a case, internal operation must be forcibly resynchronized by setting the DOUT WOD command of $34A to 1. Forced synchronization is also necessary when the operating frequency is switched such as when switching between CLV and CAV. When performing resynchronization, be sure to first return DOUT WOD to 0 and then set to 1.

∗

Resynchronization clears the internal frame counter, so the count starts over from frame 0 after the resynchronization processing. The resynchronization circuit can be disabled by setting the WINEN command of $34A to 0 so that resynchronization processing is not performed automatically or to perform resynchronization processing at the user's discretion.

DOUT circuit clock system

The DOUT block master clock is set using the clock control command MCSL ($A) used by the DAC block. Therefore, set MCSL = 1 when using 768fs, and MCSL = 0 when using 384fs.

– 81 –

CXD2598Q

LRCK

BCKI

PCMDI

48-bit slot

1

24

R0

Lch MSB (15)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

2 3 4 5 6 7 8 9 10 11 12

DOUT Block Input Timing Chart

– 82 –

CXD2598Q

§4-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ ON-OFF of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See "§1 $4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU.

(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E.

(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence.

• 1-track jump

When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5.

• 10-track jump

When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed an accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

– 83 –

CXD2598Q

• 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed an accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 2

16

tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used when N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

• Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump is made possible by controlling the sled. The track jump count N is set with register 7. N can be set to 216tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N - a in the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset.

• M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 216tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized.

– 84 –

CXD2598Q

Auto focus

Focus search up

FOK = H

NO

YES

FZC = H

NO

YES

FZC = L

NO

YES

END

Focus servo ON

Check whether FZC is continuosly high for the period of time E set with register 5.

Fig. 4-6-(a). Auto Focus Flow Chart

XLAT

$47 Latch

$03

Blind E

$08

FOK

FZC

BUSY

Command for

DSSP

Fig. 4-6-(b). Auto Focus Timing Chart

– 85 –

CXD2598Q

1 Track

NO

YES

END

Track FWD kick

sled servo OFF

WAIT

(Blind A)

COUT =

Track REV

kick

WAIT

(Brake B)

Track, sled

servo ON

(FWD kick for REV jump)

(REV kick for REV jump)

Fig. 4-7-(a). 1-Track Jump Flow Chart

XLAT

COUT

BUSY

Command for

DSSP

$48 (REV = $49) Latch

$28 ($2C)

Blind A

Brake B

$2C ($28)

$25

Fig. 4-7-(b). 1-Track Jump Timing Chart

– 86 –

CXD2598Q

10 Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = 5 ?

Track, REV

kick

Track, sled

servo ON

Checks whether the COUT cycle is longer than overflow C.

(Counts COUT × 5)

NO

YES

C = Overflow ?

Fig. 4-8-(a). 10-Track Jump Flow Chart

COUT

$4A (REV = $4B) Latch

Blind A

$2A ($2F)

COUT 5 count

$2E ($2B)

Overflow C

$25

XLAT

BUSY

Command for

DSSP

Fig. 4-8-(b). 10-Track Jump Timing Chart

– 87 –

CXD2598Q

2N Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT (MIRR) = N

Track REV

kick

Track servo

ON

NO

YES

C = Overflow

WAIT

(Kick D)

Sled servo

ON

Counts COUT for the first 16 times and MIRR for more times.

Fig. 4-9-(a). 2N-Track Jump Flow Chart

XLAT

Blind A

$2A ($2F)

COUT (MIRR)

N count

$2E ($2B)

Overflow C

Kick D

$26 ($27)

$25

$4C (REV = $4D) Latch

COUT

(MIRR)

BUSY

Command for

DSSP

Fig. 4-9-(b). 2N-Track Jump Timing Chart

– 88 –

CXD2598Q

Track Servo ON

Sled FWD Kick

Fine Search

WAIT

(Kick D)

Track Sled

FWD Kick

WAIT

(Kick F)

Traverse

Speed Ctrl

(Overflow G)

COUT = N ?

Track Servo ON

Sled REV Kick

WAIT

(Kick D)

Track Sled

Servo ON

END

YES

NO

Fig. 4-10-(a). Fine Search Flow Chart

Traverse Speed Control (Overflow G)

&

COUT N count

Kick FKick D

$26 ($27)

$2A ($2F)

$27 ($26)

$25

$44 (REV = $45) latch

XLAT

COUT

Kick D

BUSY

Command for

DSSP

Fig. 4-10-(b). Fine Search Timing Chart

– 89 –

CXD2598Q

M Track Move

NO

YES

END

Track Servo OFF

Sled FWD Kick

WAIT

(Blind A)

COUT (MIRR) = M

Track, Sled

Servo OFF

Counts COUT for M < 16. Counts MIRR for M ≥ 16.

Fig. 4-11-(a). M-Track Move Flow Chart

XLAT

Blind A

$22 ($23)

COUT (MIRR)

M count

$20

$4E (REV = $4F) Latch

COUT

(MIRR)

BUSY

Command for

DSSP

Fig. 4-11-(b). M-Track Move Timing Chart

– 90 –

CXD2598Q

§4-7. Digital CLV

Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable.

MDP

Digital CLV

CLVS U/D

MDS Error

MDP Error

CLV P/S

Measure

2/1 MUX

Over Sampling

Filter-1

Gain MDS

1/2

Mux

CLV P/S

Over Sampling

Filter-2

Noise Shape

Modulation

KICK, BRAKE, STOP

Mode Select

+

Gain DCLV

Gain MDP

LPWR

PWMI

Fig. 4-12. Block Diagram

CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo PWMI: Spindle drive signal from microcomputer for CAV servo

– 91 –

CXD2598Q

§4-8. CD-DSP Block Playback Speed

In the CXD2598Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.

Mode

1 2 3 4 5 6 7

XTAI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs

XTSL

1 1 0 0 0 0 1

DSPB

0 1 0 1 0 1 1

VCOSEL1

∗1

0/1 0/1

1

1 0/1 0/1 0/1

ASHS

0 0 1 1 0 0 0

Playback speed

1× 2× 2× 4× 1× 2× 1×

Error correction

∗2

C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double

∗1

Actually, the optimal value should be used together with KSL3 and KSL2.

∗2

When the ERC4 command of $8 = 1, C2 is quadruple correction even when DSPB = 1.

The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "§3. Description of Modes" for details.

§4-9. DAC Block Playback Speed

The operating speed of the DAC block is determined by the crystal and the MCSL command of $9X regardless of the operating conditions of the CD-DSP block. This allows the DAC and CD-DSP block playback modes to be set independently.

1-bit DAC block playback speed

X'tal

768Fs 768Fs 384Fs

1 0 0

1× 2× 1×

MCSL DAC block playback speed

Fs = 44.1kHz.

§4-10. DAC Block Input Timing

The DAC block input timing is shown in Timing Chart 4-12. The CXD2598Q enables data transfer from the CD signal processor block to the DAC block via an external route. This makes it possible to send data to the DAC block via an external audio DSP, etc. When the data is input to the DAC block without using an audio DSP, either EMPH, LRCK, BCK and PCMD must be connected directly with EMPHI, LRCKI, BCKI and PCMDI outside the LSI, or the OUTL0 command of $8X must be set to 1. Note that when the OUTL0 command of $8X is set to 1, the EMPH, LRCK, BCK and PCMD outputs are low.

§4-11. Description of DAC Block Functions Zero data detection

When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is performed independently for the left and right channels.

Mute flag output

The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X.

• When zero data is detected

• When a high signal is input to the SYSM pin

• When the DAC SMUTL and DAC SMUTR commands of $9X are set (The flags change independently for the left and right channels.)

The mute flag outputs during initialize are as follows. (When zero data is input from LRCKI, BCKI and PCMDI, and ZDPL of address $9 and MCSL of address $A are the initial values for the period in the figure below.)

– 92 –

CXD2598Q

A

Y1

B

Y3

C

Y2

23.2 [ms]

–∞ 000 (H)

0dB

400 (H)

XRST

LMUT

RMUT

Approximately 370ms when crystal = 16.9344MHz Approximately 185ms when crystal = 33.8688MHz

Attenuation operation

Assuming the attenuation commands X1, X3 and X2, the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches Y2. In addition, when the command X3 is sent before the audio output reaches Y2 (B or C in the figure), the audio output approaches Y3 from the value (B or C in the figure) at that point.

– 93 –

CXD2598Q

DAC block mute operation

Soft mute

Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

• When attenuation data of 000 (high) is set

• When the DAC SMUTL and DAC SMUTR commands of $9X are set to 1

• When a high signal is input to the SYSM input pin

Forced mute

Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low.

Zero detection mute

Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1.

Soft mute ON Soft mute OFFSoft mute OFF

23.2 [ms] 23.2 [ms]

0dB

–∞dB

– 94 –

CXD2598Q

DAC Block Input Timing

Normal-Speed Playback

LRCKI

(44.1k)

BCKI

(2.12M)

1

24

PCMDI

R0

Lch MSB (15)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB

PCMDI

LRCKI

(88.2k)

BCKI

(4.23M)

Double-Speed Playback

24

R0

Lch MSB (15)

Rch MSB

2 3 4 5 6 7 8 9 10 11 12

1

2

L0

Timing Chart 4-12

– 95 –

CXD2598Q

LRCK Synchronization

Synchronization is performed at the first rising edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases.

• When the XTSL pin switches between high and low

• When the DSPB command of $9X setting changes

• When the MCSL command of $AX setting changes

• When operation switches between CLV mode and CAV mode

LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in these cases as well. For resynchronization, set the XWOC command of $9X to 0, wait for one LRCK cycle or more, and then set XWOC to 1.

∗

When setting XWOC to 0, be sure to set the SYCOF command of $9X to 0 beforehand.

SYCOF

When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1. Normally, the memory proof, etc., is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting SYCOF of address 9 to 1 ignores when the LRCKI input synchronization is lost, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow and flutter in the LRCKI input.

∗

Set SYCOF to 0 other than when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI, respectively, and performing playback in CAV-W mode.

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CXD2598Q

Graph 4-13.

Digital Bass Boost

Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for this setting. See Graph 4-13 for the digital bass boost frequency response.

Normal DBB MID DBB MAX

10.00

–4.00

6.00

4.00

2.00

0.00

–2.00

8.00

–6.00

–8.00 –10.00 –12.00 –14.00

10 30 100 300 1k 3k 10k 30k

Digital Bass Boost Frequency Response [Hz]

[dB]

– 97 –

CXD2598Q

Analog out

C2

680p

12k

C1

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Vc

Fig. 4-14. LPF External Circuit

§4-12. LPF Block

The CXD2598Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (Vc) is (AVDD – AVSS) × 0.43.

The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc ≈ 40kHz.

The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference. The resistors' values do not change at this time.

• When fc ≈ 30kHz: C1 = 200pF, C2 = 910pF

• When fc ≈ 50kHz: C1 = 120pF, C2 = 560pF

LPF Block Application Circuit

– 98 –

CXD2598Q

§4-13. Asymmetry Correction

Fig. 4-15 shows the block diagram and circuit example.

ASYE

RFAC

R1

+ –

ASYO

ASYI

R1 2 R2 5

=

BIAS

R1

R2

+ –

Fig. 4-15. Asymmetry Correction Application Circuit.

– 99 –

CXD2598Q

§4-14. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1, the

CD TEXT demodulation circuit occupies the EXCK and SBSO pins, so connect EXCK to low and do not use the data output from SBSO. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.

• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK.

• The readable data are the CRC counting results for each pack and the CD TEXT data (16 bytes) except for CRC data.

• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Data which can be stored in the LSI is 1 packet (4 packs).

Fig. 4-16. Block Diagram of CD TEXT Demodulation Circuit

SQCK

SQSO

TXOUT

Subcode

Decoder

CD TEXT

Decoder

TXON

SBSO

EXCK

– 100 –

CXD2598Q

CRC

4

CRC

3

CRC

2

CRC

1

0

0 0 0

S2 R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 R3 W2 V2 U2 T2 W4 V4 U4 T4 S4

CRC Data

ID1 (Pack1)

ID2 (Pack1)

ID3 (Pack1)

16 Bytes

4 bits

Subcode Q Data

SCOR

TXOUT

(command)

SQCK

SQSO

SQCK

TXOUT

(command)

LSB

MSB

LSB MSB

LSB

CRC

0

Pack1

Pack2

Pack3

Pack4

CRCF

80 Clocks

SQSO

520 Clocks

Fig. 4-17. CD TEXT Data Timing Chart