Page 1
Description
The CXD3000R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 16× continuous playback possible with a
low external clock
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 16× playback by switching the built-
in VCO
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 16× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo
control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump function supporting micro two-axis
Digital Filter and DAC Blocks
• Digital de-emphasis
• Digital attenuation
• 4Fs oversampling filter
• Adoption of a secondary ∆∑ noise shaper
• Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD –0.3 to +4.6 V
• Input voltage VI –0.3 to +4.6 V
(VSS – 0.3V to VDD + 0.3V)
• Output voltage VO –0.3 to +4.6 V
• Storage temperature Tstg –40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage VDD
∗
3.0 to 3.6 V
• Operating temperature
Topr –20 to +75 °C
∗
The VDD (min.) for the CXD3000R varies
according to the playback speed and built-in VCO
selection. The VDD (min.) for the CXD3000R under
various conditions are as shown on the following
page.
– 1 –
CXD3000R
E96742A88
CD Digital Signal Processor with Built-in Digital Servo and DAC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
144 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
Page 2
– 2 –
CXD3000R
The maximum operating speed graph shows the playback speed VDD (min.) at various temperatures.
The playback conditions are high-speed VCO selected in CAV-W mode with DSPB = 1.
Maximum Operating Speed
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
[V]
[Multiple]
20
19
18
17
16
15
14
13
12
11
10
: +75°C
: +55°C
: +25°C
Page 3
– 3 –
CXD3000R
Block Diagram
Error
corrector
Noise
Shaper
Peak
detector
OpAmp
AnaSw
A/D
CONVERTER
32K RAM
Serial/parallel
processor
Digital PLL
Vari-Pitch
double speed
MUX
∗
CLV
processor
18-times
oversampling
filter
MIRR
Servo
Interface
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
Clock
Generator
Subcode
P to W
processor
Timing
Generator1
Subcode Q
processor
Servo
auto
sequencer
CPU interface
4fs Digital Filter
+
1 bit DAC
EFM
Demodulator
Sync
protector
Priority
encoder
D/A data
processor
Digital out
Register
Address
generator
Timing
Generator 2
SERVO DSP
FOCUS SERVO
TRACKING SERVO
SLED SERVO
8
DFCT
FOK
AO1R
AO2F
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
SENS
PSSL
DA01
to DA16
MUTE
COUT
MIRR
DFCT
FOK
DATA
CLOK
XLAT
DOUT
MD2
AO1F
AO2R
XTLO
XTLI
VPCO1
XWO
DAS0
PCMDI
BCKI
LRCKI
DTS1
DTS2
DAS1
VPCO2
XTSL
DAC Block
Signal Processor Block
Servo Block
TEST
TES2
TES3
DV
DD
1
AV
DD
1
AV
DD
2
AV
DD
3
AV
DD
4
AV
DD
5
DV
SS
0
DV
SS
1
AV
SS
1
AV
SS
2
AV
SS
3
XRST
ADIO
DV
DD
0
AV
SS
4
AV
SS
5
49 to 44,
42 to 31,
29, 27
MCKO
V16M
FSTO
C4M
C16M
VCTL
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
MON
FSW
MDP
MDS
EXCK
SBSO
SQCK
SQSO
RFDC
TE
SE
FE
VC
CE
PWMI
VCKI
101
103
104
105
106
112
113
114
115
116
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
138
139
140
141
142
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
20
21
22
23
26
28
30
51
52
55
56
57
59
60
70
69
67
63
64
65
66
61
62
82
83
75
77
78
87
86
79
100
99
95
91
92
OSC
Page 4
– 4 –
CXD3000R
Pin Configuration
36
35
34
313233
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
1
40
39
38
37
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
97
96
95
94
91
92
93
100
99
98
101
102
103
104
105
106
107
108
73
74
81
82
83
84
75
76
77
78
88
87
86
85
79
80
89
90
111
109
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
FSTO
NC
FSTI
MCKO
XTSL
DV
SS2
DA01
DA02
DA04
DA05
DA06
DV
DD2
DA07
DA08
DA09
DA10
NC
NC
SQCK
SQSO
EXCK
SBSO
SCOR
WFCK
MUTE
DOUT
MD2
DV
DD3
C16M
C4M
NC
DTS2
XRST
SCSY
NC
DA03
NC
NC
DFCT
MIRR
COUT
DV
SS
4
XLAT
DATA
XWO
ATSK
SCLK
DIRC
SENS
DV
DD
4
AV
DD
3
AO1R
AV
SS
3
AV
SS
5
XTLI
XTLO
AV
DD
5
AV
DD
4
AO2F
AO2R
DV
SS
3
DAS1
DAS0
DTS0
DTS1
NC
FOK
CLOK
AO1F
NC
AV
SS
4
NC
PWMI
FSW
MON
MDP
MDS
LOCK
SSTP
DV
SS5
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DV
DD5
NC
VCOO
VCOI
TEST
TES2
TES3
PDO
VCKI
V16M
AV
DD2
IGEN
AV
SS2
ADIO
RFDC
CE
TE
NC
NC
TESTA
NC
NC
NC
NC
SE
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AV
SS
1
RFAC
BIAS
ASYI
ASYO
AV
DD
1
NC
DV
DD
1
DV
SS
1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
DA14
DA13
DA12
DA11
NC
NC
VC
VPCO1
FE
BCKI
Page 5
– 5 –
CXD3000R
Pin Description
Pin
No.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
39
40
I
I
I
O
O
I
O
I
O
I
I
I
I
O
I
I
O
O
I
O
I
O
I
O
O
O
O
O
O
1, Z, 0
1, Z, 0
Analog
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E
command FCSW.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = VSS, high = VDD).
Analog power supply.
Digital power supply.
Digital GND.
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low: serial, high: parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 64-bit slot serial data output (two's
complement, LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AVSS1
RFAC
BIAS
ASYI
ASYO
AVDD1
DVDD1
DVSS1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
DA10
DA09
Symbol I/O Description
Page 6
– 6 –
CXD3000R
41
42
43
44
45
46
47
48
49
50
51
52
53
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
75
76
77
78
79
80
81
82
O
O
O
O
O
O
O
O
I
O
I
O
O
O
I
O
I
O
O
O
I
O
I
I
I
I
I
I
I
I
I
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
Digital power supply.
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
Digital GND.
Crystal selection input.
Clock output. Inverted output of XTLI.
2/3 frequency division input for XTLI pin.
2/3 frequency division output for XTLI pin. Does not change with variable pitch.
1/4 frequency division output for XTLI pin. Changes with variable pitch.
16.9344MHz output. Changes simultaneously with variable pitch.
Digital power supply.
Digital Out on/off control (low = off, high = on).
Digital Out output.
Mute (low: off, high: on).
WFCK (Write Frame Clock) output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
Sub Q 80-bit and PCM peak and level data 16-bit output.
SQSO readout clock input.
GRSCOR re-synchronization input.
System reset. Reset when low.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to low.
DAC sync window open input. Normally high, window open when low.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to low.
Digital GND.
Analog GND.
Channel 2 DAC PWM output (reversed phase).
DA08
DA07
DVDD2
DA06
DA05
DA04
DA03
DA02
DA01
DVSS2
XTSL
MCKO
FSTI
FSTO
C4M
C16M
DVDD3
MD2
DOUT
MUTE
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
SCSY
XRST
DTS2
DTS1
DTS0
XWO
DAS0
DAS1
DVSS3
AVSS4
AO2R
Pin
No.
Symbol I/O Description
Page 7
– 7 –
CXD3000R
83
84
85
86
87
88
89
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
111
112
113
114
115
116
117
118
119
120
121
122
O
O
I
O
O
O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
O
O
O
O
I/O
I
O
O
O
1, Z, 0
1, 0
1, Z, 0
1, Z, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Channel 2 DAC PWM output (forward phase).
Analog power supply.
Master clock power supply.
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
Master clock GND.
Analog GND.
Channel 1 DAC PWM output (forward phase).
Channel 1 DAC PWM output (reversed phase).
Analog power supply.
Digital power supply.
SENS output to CPU.
Used during 1-track jumps.
SENS serial data readout clock input.
Anti-shock pin.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Digital GND.
Track count signal I/O.
Mirror signal I/O.
Defect signal I/O.
Focus OK signal I/O.
Test pin. Leave this open.
Spindle motor external pin input.
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Spindle motor on/off control output.
Spindle motor servo control output.
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high.
Disc innermost track detection signal input.
Digital GND.
Sled drive output.
Sled drive output.
Tracking drive output.
AO2F
AVDD4
AVDD5
XTLO
XTLI
AVSS5
AVSS3
AO1F
AO1R
AVDD3
AVDD4
SENS
DIRC
SCLK
ATSK
DATA
XLAT
CLOK
DVSS4
COUT
MIRR
DFCT
FOK
TESTA
PWMI
FSW
MON
MDP
MDS
LOCK
SSTP
DVSS5
SFDR
SRDR
TFDR
Pin
No.
Symbol I/O Description
Page 8
– 8 –
CXD3000R
∗
In the CXD3000R, the following pins are NC.
Pins 1, 2, 19, 35, 36, 37, 38, 54, 71, 72, 73, 74, 90, 107, 108, 109, 110, 127, 143 and 144
Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
123
124
125
126
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
O
O
O
O
I
I
I
I
O
I
O
I
O
I
I
I
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, Z, 0
Tracking drive output.
Focus drive output.
Focus drive output.
Digital power supply.
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz
Set VCKI to low when the external clock is not input to this pin.
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
Connects the operational amplifier current source reference resistance connection.
Analog GND.
Operational amplifier output.
RF signal input.
Center servo analog input.
Tracking error signal input.
TRDR
FFDR
FRDR
DVDD5
VCOO
VCOI
TEST
TES2
TES3
PDO
VCKI
V16M
AVDD2
IGEN
AVSS2
ADIO
RFDC
CE
TE
Pin
No.
Symbol I/O Description
Page 9
– 9 –
CXD3000R
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Input leak current (1)
Input leak current (2)
Tri-state pin
output leak current
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
Input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input voltage (1)
Input voltage (2)
Input voltage (3)
Input voltage (4)
Input voltage (5)
Input voltage (6)
Output voltage (1)
Output voltage (2)
Output voltage (3)
Output voltage (4)
Output voltage (5)
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIH (3)
VIL (3)
VIH (4)
VIL (4)
VIN (5)
VIN (6)
VOH (1)
VOL (1)
VOH (2)
VOL (2)
VOH (3)
VOL (3)
VOL (4)
VOH (5)
VOL (5)
ILI (1)
ILI (2)
ILO
0.7VDD
0.7VDD
0.7VDD
0.7VDD
VSS
VSS
VDD – 0.4
0
VDD – 0.4
0
VDD – 0.2
0
0
VDD – 0.5
0
–10
–20
–5
0.2VDD
0.2VDD
0.2VDD
0.2VDD
VDD
VDD
VDD
0.4
VDD
0.4
VDD
0.4
0.4
VDD
0.4
10
20
5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
Conditions Min. Typ. Max. Unit
Applicable pins
Applicable pins
∗1
BCKI, DTS0, DTS1, DTS2, LRCKI, PCMDI, TES2, TES3, TEST
∗2
ASYE, FSTI, VCKI
∗3
ATSK, DATA, DIRC, MD2, PWMI, SSTP, XLAT, XTSL, XWO
∗4
CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST
∗5
ASYI, BIAS, CLTV, FILI, IGEN, RFAC, VCTL
∗6
CE, FE, SE, TE, VC, RFDC
∗7
ASYO, C16M, C4M, DA01 to DA16, DAS0, DAS1, DOUT, FFDR, FRDR, FSTO, LRCK, MON, PSSL,
SBSO, SCOR, SFDR, SQSO, SRDR, TFDR, TRDR, WDCK, WFCK
∗8
FSW
∗9
MCKO
∗10
AO1F, AO1R, AO2F, AO2R, MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2
∗11
FILO
∗12
COUT, DFCT, FOK, LOCK, MIRR
Schmitt input
VI ≤ 5.5V
VI ≤ 5.5V
Schmitt input
Analog input
Analog input
IOH = –8mA
IOL = 8mA
IOH = –4mA
IOL = 4mA
IOH = –2mA
IOL = 4mA
IOL = 4mA
IOH = –0.28mA
IOH = 0.36mA
VI = 0 to 5.5V
VI = 0.25VDD
to 0.75VDD
VO = 0 to 3.6V
∗1, ∗12
∗2
∗3
∗4
∗5
∗6
∗9
∗7, ∗10
∗12
∗7, ∗10
∗12
∗8
∗11
∗3, ∗4, ∗5
∗6
∗10
Page 10
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ±10%)
(b) When inputting pulses to XTLI and VCOI pins
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ±10%)
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ±10%)
– 10 –
CXD3000R
Oscillation
frequency
fMAX 7
34
MHz
Item Symbol Min. Typ. Max.
Unit
High level pulse
width
tWHX
13 500
ns
Low level pulse
width
tWLX
13 500
ns
Pulse cycle
tCX
26 1000
ns
Input high level VIHX VDD – 1.0
V
Input low level VILX 0.8
V
Rise time,
fall time
tR, tF
10
ns
Item Symbol Min. Typ. Max. Unit
Input amplitude VI 2.0 VDD + 0.3 Vp-p
Item Symbol Min. Typ. Max. unit
tR tF
tWHX
tWLX
tCX
VILX
VIHX × 0.1
V
IHX × 0.9
V
IHX
XTLI
V
DD/2
Page 11
– 11 –
CXD3000R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
30
30
30
30
750
750
16
0.65
MHz
ns
ns
ns
ns
ns
MHz
ns
Item Symbol Min. Typ. Max. Unit
tWCK tWCK
1/fCK
tH
tSU
tWL
tD
1/fT
tWT tWT
tH
tSU
CLOK
DATA
XLAT
EXCK
SQCK
SBSO
SQSO
Page 12
– 12 –
CXD3000R
(4) COUT, MIRR and DFCT pins
Operating frequency
(VDD = AVDD = 3.3V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
COUT maximum operating frequency
MIRR maximum operating frequency
DFCT maximum operating frequency
fCOUT
fMIRR
fDFCTH
40
40
5
kHz
kHz
kHz
∗1
∗2
∗3
Item Symbol Min. Typ. Max. Unit
Conditions
∗
1
When using a high-speed traverse TZC.
∗
2
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.11VDD to 0.23VDD
• ≤ 25%
∗
3
During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
(3) SCLK pin
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
31.3
15
16 MHz
ns
µs
Item Symbol Min. Typ. Max. Unit
tSPWtDLS
1/fSCLK
MSB LSB•••
•••
XLAT
SCLK
Serial Read Out Data
(SENS)
A
B
B
A + B
Page 13
– 13 –
CXD3000R
(5) BCKI, LRCKI and PCMDI pins (VDD = 3.3V ±10%, Topr = –20 to +75°C)
Input BCKI frequency
Input BCKI pulse width
Input data setup time
Input data hold time
Input LRCK setup time
Input LRCK hold time
tBCK
tWIB
tIDS
tIDH
tILRH
tILRS
100
10
15
10
15
4.5 MHz
ns
Item Symbol Min. Typ. Max. Unit
tILRH
tWIB tWIB
tIDHtIDS
tILRS
50%
BCKI
PCMDI
LRCKI
Page 14
– 14 –
CXD3000R
DAC Analog Characteristics
Measurement conditions
(Ta = 25°C, VDD = 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 768Fs)
S/N ratio
THD + N
Dynamic range
Channel separation
Output level
Difference in gain between channels
93
0.015
91
91
1.7028
0.1
dB
%
dB
dB
V (rms)
dB
Item
Typ.
Unit
(EIAJ)
∗
1
(EIAJ)
(EIAJ)
∗
1, ∗2
(EIAJ)
Remarks
CXD3000R
AO1F
AO1R
3.9k
130k
3.9k
3.9k
130k
3.9k
47p
47p
4.7k
4.7k
4.7k
820p
4.7k
820p
4.7k 4.7k
0.015
4.7k
1800p 82p
12k
100
22
OUTPUT
∗1
Using "A" weighting filter
∗2
–60 dB, 1kHz input
The analog characteristics measurement circuit is shown below.
AO1R
AO2F
AO2R
AO1F
TEST DISK
DATA
Audio Circuit
Analog
1ch
2ch
Audio Analyzer
SHIBASOKU (AM51A)768fs
CXD3000R
Block diagram of analog characteristics measurement
Page 15
– 15 –
CXD3000R
Contents
[1] CPU Interface
§1-1. CPU Interface Timing ........................................................................................................................16
§1-2. CPU Interface Command Table ........................................................................................................ 16
§1-3. CPU Command Presets ....................................................................................................................26
§1-4. Description of SENS Signals ............................................................................................................. 31
[2] Subcode Interface
§2-1. P to W Subcode Readout .................................................................................................................. 60
§2-2. 80-bit Sub Q Readout ........................................................................................................................ 60
[3] Description of Modes
§3-1. CLV-N Mode ...................................................................................................................................... 66
§3-2. CLV-W Mode ..................................................................................................................................... 66
§3-3. CAV-W Mode ..................................................................................................................................... 66
[4] Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 68
§4-2. Frame Sync Protection ...................................................................................................................... 70
§4-3. Error Correction ................................................................................................................................. 70
§4-4. DA Interface ....................................................................................................................................... 71
§4-5. Digital Out .......................................................................................................................................... 74
§4-6. Servo Auto Sequence ....................................................................................................................... 75
§4-7. Digital CLV ......................................................................................................................................... 83
§4-8. Playback Speed ................................................................................................................................ 84
§4-9. DAC Block Playback Speed .............................................................................................................. 85
§4-10. DAC Block Input Timing .................................................................................................................... 85
§4-11. Asymmetry Compensation ................................................................................................................ 86
§4-12. CXD3000 Clock System .................................................................................................................... 87
[5] Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of the Servo Signal Processing System ............................................................ 88
§5-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 89
§5-3. AVRG Measurement and Compensation .......................................................................................... 89
§5-4. E:F Balance Adjustment Function ..................................................................................................... 91
§5-5. FCS Bias Adjustment Function .......................................................................................................... 91
§5-6. AGCNTL Function ............................................................................................................................. 93
§5-7. FCS Servo and FCS Search ............................................................................................................. 95
§5-8. TRK and SLD Servo Control ............................................................................................................. 96
§5-9. MIRR and DFCT Signal Generation .................................................................................................. 97
§5-10. DFCT Countermeasure Circuit .......................................................................................................... 98
§5-11. Anti-Shock Circuit .............................................................................................................................. 98
§5-12. Brake Circuit ...................................................................................................................................... 99
§5-13. COUT Signal ................................................................................................................................... 100
§5-14. Serial Readout Circuit ...................................................................................................................... 100
§5-15. Writing to the Coefficient RAM ........................................................................................................ 101
§5-16. PWM Output .................................................................................................................................... 101
§5-17. DIRC Input Pin ................................................................................................................................. 103
§5-18. Servo Status Changes Produced by the LOCK Signal ................................................................... 104
§5-19. Description of Commands and Data Sets ....................................................................................... 104
§5-20. List of Servo Filter Coefficients ........................................................................................................ 117
§5-21. Filter Composition ............................................................................................................................ 119
§5-22. TRACKING and FOCUS Frequency Response .............................................................................. 126
[6] Application Circuit .................................................................................................................................. 127
Explanation of abbreviations AVRG: Average
AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
Page 16
– 16 –
CXD3000R
[1] CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C to D
E
8 bit
8 to 24 bit
16 bit
20 bit
24 bit
20 bit
28 bit
20 bit
16 bit
20 bit
Total bit length
30ns or more
D18 D19 D20 D21 D22 D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0 D1
Page 17
– 17 –
CXD3000R
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
1
1
0
0
0
0
1
0
—
—
—
—
—
—
0
1
—
—
—
—
0
—
1
0
—
—
—
—
—
—
0
1
1
1
—
—
—
—
0
1
—
—
—
—
—
—
0
1
—
—
—
—
—
—
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0 0 0 0
0 0 0 1
FOCUS
CONTROL
TRACKING
CONTROL
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Command Table ($0X to 1X)
—: Don’t care
Page 18
– 18 –
CXD3000R
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
SLED KICK LEVEL
(±1 × basic value) (Default)
SLED KICK LEVEL
(±2
×
basic value)
SLED KICK LEVEL
(±3
×
basic value)
SLED KICK LEVEL
(±4
×
basic value)
0
0
1
1
—
—
—
—
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
0
0
1
1
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
0 0 1 0
0 0 1 1
TRACKING
MODE
SELECT
Register
Command
Address
D23 to D20
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: Don’t care
Command Table ($2X to 3X)
Page 19
– 19 –
CXD3000R
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 0SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($340X)
Page 20
– 20 –
CXD3000R
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 1SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($341X)
Page 21
– 21 –
CXD3000R
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 0SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($342X)
Page 22
– 22 –
CXD3000R
KRAM DATA (K30)
FIX
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 1SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($343X)
Page 23
– 23 –
CXD3000R
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
NOT USED
KRAM DATA (K47)
NOT USED
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 1 0 0SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($344X)
Page 24
– 24 –
CXD3000R
0 0 1 1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
TZC/COUT
BOTTOM/MIRR
Filter
Others
3
0 0 1 1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
FBL9
FB9
TV9
FBL8
FB8
TV8
FBL7
FB7
TV7
FBL6
FB6
TV6
FBL5
FB5
TV5
FBL4
FB4
TV4
FBL3
FB3
TV3
FBL2
FB2
TV2
FBL1
FB1
TV1
—
—
TV0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
FT1
TDZC
FZSH
VCLM
DAC
0
SFO2
FT0
DTZC
FZSL
VCLC
SD6
FBON
SFO1
FS5
TJ5
SM5
FLM
SD5
FBSS
SDF2
FS4
TJ4
SM4
FLC0
SD4
FBUP
SDF1
FS3
TJ3
SM3
RFLM
SD3
FBV1
MAX2
FS2
TJ2
SM2
RFLC
SD2
FBV0
MAX1
FS1
TJ1
SM1
AGF
SD1
0
SFOX
FS0
TJ0
SM0
AGT
SD0
TJD0
BTF
FTZ
SFJP
AGS
DFSW
0
FPS1
D2V2
FG6
TG6
AGJ
LKSW
0
FPS0
D2V1
FG5
TG5
AGGF
TBLM
0
TPS1
D1V2
FG4
TG4
AGGT
TCLM
0
TPS0
D1V1
FG3
TG3
AGV1
FLC1
0
0
RINT
FG2
TG2
AGV2
TLC2
0
SJHD
0
FG1
TG1
AGHS
TLC1
0
INBK
0
FG0
TG0
AGHT
TLC0
0
MTI0
0
1
1
1
1
1
1
1
1
0
1
F1NM
0
F1DM
AGG4
F3NM
XT4D
F3DM
XT2D
T1NM
0
T1UM
DRR2
T3NM
DRR1
T3UM
DRR0
DFIS
0
TLCD
ASFG
0
0
LKIN
LPAS
COIN
SRO1
MDFI
SRO0
MIRI
AGHF
XT1D
0
1
1
0
0
0
1
COSS
0
COTS
0
CETZ
0
CETF
0
COT2
0
COT1
0
MOT2
0
0
0
BTS1
0
BTS0
0
MRC1
0
MRC0
0
0
0
0
0
0
0
0
0
SELECT
Register
Command
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Address
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
Command Table ($34FX to 3FX)
—: Don’t care
Page 25
– 25 –
CXD3000R
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence
(N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
AS3
TR3
SD3
32768
CD-
ROM
DCLV
ON/OFF
0
32768
Gain
MDP1
DCLV
PWM MD
CM3
AS2
TR2
SD2
16384
DOUT
Mute
DSPB
ON/OFF
0
16384
Gain
MDP0
TB
CM2
AS1
TR1
SD1
8192
DOUT
Mute-F
ASEQ
ON/OFF
Mute
8192
Gain
MDS1
TP
CM1
AS0
TR0
SD0
4096
WSEL
DPLL
ON/OFF
ATT
4096
Gain
MDS0
CLVS
Gain
CM0
MT3
0
KF3
2048
VCO
SEL
BiliGL
MAIN
PCT1
2048
Gain
DCLV1
VP7
EPWM
MT2
0
KF2
1024
ASHS
BiliGL
SUB
PCT2
1024
Gain
DCLV0
VP6
SPDC
MT1
0
KF1
512
SOCT
FLFC
DADS
512
PCC1
VP5
ICAP
MT0
0
KF0
256
VCO
SEL2
0
SOC2
256
PCC0
VP4
SFSL
LSSL
0
0
128
KSL3
DAC
EMP
AT1D7
128
0
VP3
VC2C
0
0
0
64
KSL2
DAC
ATT
AT1D6
64
0
VP2
HIFC
0
0
0
32
KSL1
0
AT1D5
32
0
VP1
LPWR
0
0
0
16
KSL0
0
AT1D4
16
0
VP0
VPON
—
—
—
8
VC01
CS1
PLM3
AT1D3
8
—
—
Gain
CAV1
—
—
—
4
VCO1
CS0
PLM2
AT1D2
4
—
—
Gain
CAV0
—
—
—
2
VCO2
THRU
PLM1
AT1D1
2
—
—
FCSW
—
—
—
1
0
PLM0
AT1D0
1
—
—
0
4
5
6
7
8
9
A
B
C
D
E
Register
Command
Address
D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
Data 1 Data 2 Data 3 Data 4
Command Table ($4X to EX)
—: Don’t care
MODE
specification
1 0 0 0 ERC4
SCOR
SEL
SCSY — — — — —8
Audio CTRL
1 0 1 0 AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0A
Register
Command
Address Data 1 Data 2 Data 3 Data 4
D7 D6 D5 D4 D3 D2 D1 D0
Data 5 Data 6
Page 26
– 26 –
CXD3000R
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
TRACKING SERVO OFF
SLED SERVO OFF
SLED KICK LEVEL
(±1 × basic value) (Default)
KRAM DATA
($3400XX to $344fXX)
0
0
0
0
0
0
0
0
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
0 0 0 0
0 0 0 1
0 0 1 0
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
MODE
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Register
Command
3 SELECT
Address
D23 to D20
0 0 1 1
0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".
0 0 0 0 — — — — — — — —
—
— — — — — — —
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D0 D0
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Address 3
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D0 D0
§1-3. CPU Command Presets
Command Preset Table ($0X to 34X)
—: Don’t care
Page 27
– 27 –
CXD3000R
0 0 1 1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
3
0 0 1 1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Filter
Others
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELECT
Register
Command
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Address
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
Command Preset Table ($34FX to 3FX)
—: Don’t care
Page 28
– 28 –
CXD3000R
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence
(N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
—
—
—
0
0
1
1
0
—
—
0
—
—
—
0
0
0
1
0
—
—
0
—
—
—
0
0
0
1
0
—
—
0
—
—
—
0
0
1
1
0
—
—
0
4
5
6
7
8
9
A
B
C
D
E
Register
Command
Address
D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
Data 1 Data 2 Data 3 Data 4
Command Preset Table ($4X to EX)
—: Don’t care
MODE
specification
1 0 0 0 0 0 0 — — — — —8
Audio CTRL
1 0 1 0 1 1 1 1 1 1 1 1A
Register
Command
Address Data 1 Data 2 Data 3 Data 4
D7 D6 D5 D4 D3 D2 D1 D0
Data 5 Data 6
Page 29
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CXD3000R
<Coefficient ROM Preset Values Table (1)>
ADDRESS
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix
∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
DATA CONTENTS
Page 30
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CXD3000R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
Fix
∗
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
DATA CONTENTS
∗
Fix indicates that normal preset values should be used.
Page 31
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CXD3000R
§1-4. Description of SENS Signals
SENS output
Microcomputer serial
register (latching not
required)
$0X
$1X
$2X
$38
$38
$30 to 37
$3A
$3B to 3F
$3904
$3908
$390C
$391C
$391D
$391F
$4X
$5X
$6X
$AX
$BX
$CX
$EX
$7X, 8X, 9X,
DX, FX
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
GFS
COMP
COUT
OV64
Z
FZC
AS
TZC
AGOK
∗
XAVEBSY
∗
SSTP
FBIAS Count STOP
SSTP
TE Avrg Reg.
FE Avrg Reg.
VC Avrg Reg.
TRVSC Reg.
FB Reg.
RFDC Avrg Reg.
XBUSY
FOK
0
GFS
COMP
COUT
OV64
0
—
—
—
—
—
—
—
—
9 bit
9 bit
9 bit
9 bit
9 bit
8 bit
—
—
—
—
—
—
—
—
ASEQ = 0 ASEQ = 1 Output data length
∗
$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
Page 32
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CXD3000R
Description of SENS Signals
The SENS pin is high impedance.
Low while the auto sequencer is in operation, high when operation terminates.
Outputs the same signal as the FOK pin.
High for "focus OK".
High when the regenerated frame sync is obtained with the correct timing.
Counts the number of tracks set with Reg.B.
High when Reg.B is latched, low when the initial Reg.B number is input by CNIN.
Counts the number of tracks set with Reg.B.
High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44
and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number.
Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
through the sync detection filter.
Z
XBUSY
FOK
GFS
COMP
COUT
OV64
SENS output
Page 33
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CXD3000R
The meaning of the data for each address is explained below.
$4X commands
Register name
4
Data 1
Command
Data 2
MAX timer value
Data 3
Timer range
AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 0
Command
Cancel
Fine Search
Focus-on
1-Track Jump
10-Track Jump
2N-Track Jump
M Track Move
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
RXF
1
RXF
RXF
RXF
RXF
AS3 AS2 AS1 AS0
RXF = 0 Forward
RXF = 1 Reverse
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence
is interrupted.
• To disable the MAX timer, set the MAX timer value to 0.
$5X commands
MAX timer value
MT3
23.2ms
1.49s
11.6ms
0.74s
5.8ms
0.37s
2.9ms
0.18s
0
1
0
0
0
0
0
0
MT2 MT1 MT0 LSSL 0 0 0
Timer range
Timer TR3 TR2 TR1
TR0
Blind (A, E), Overflow (C, G)
Brake (B)
0.18ms
0.36ms
0.09ms
0.18ms
0.045ms
0.09ms
0.022ms
0.045ms
Page 34
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CXD3000R
Command
Data 1 Data 2
Data 3 Data 4
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
2152142132122112102928272625242322212
0
Auto sequence track jump
count setting
This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is
executed and to set the jump count when fine search is executed for auto sequence.
• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
• When the track jump count is from 0 to 15, the COUT signal counted for 2N-track jumps and M-track moves;
when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted.
$7X commands
Auto sequence track jump count setting
$6X commands
Register name
6
Data 1
KICK (D)
Data 2
KICK (F)
SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0
Timer SD3 SD2 SD1 SD0
When executing KICK (D) $44 or $45
When executing KICK (D) $4C or $4D
23.2ms
11.6ms
11.6ms
5.8ms
5.8ms
2.9ms
2.9ms
1.45ms
Timer KF3 KF2 KF1 KF0
KICK (F) 0.72ms 0.36ms 0.18ms 0.09ms
Page 35
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CXD3000R
∗
See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions.
MD2
Other mute conditions
∗
DOUT Mute
D.out Mute F
DOUT output
OFF
0dB
– ∞dB
DA output
0dB
0dB
– ∞dB
0dB
– ∞dB
– ∞dB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Command
Data 1
MODE
specification
CD-
ROM
DOUT
Mute
DOUT
Mute-F
WSEL
D23 D22 D21 D20
Data 2
VCO
SEL1
ASHS SOCT
VCO
SEL2
D19 D18 D17 D16
Data 3
KSL3 KSL2 KSL1 KSL0
D15 D14 D13 D12
$8X commands
Command bit
DOUT Mute = 1
DOUT Mute = 0
When Digital Out is on (MD2 pin = 1), DOUT output is muted.
When Digital Out is on, DOUT output is not muted.
Processing
Command bit
D. out Mute F = 1
D. out Mute F = 0
When Digital Out is on (MD2 pin = 1), DA output is muted.
DA output mute is not affected when Digital Out is either on or off.
Processing
Command bit
CDROM = 1
CDROM = 0
C2PO timing
1-3
1-3
CDROM mode; average value interpolation and pre-value hold are not performed.
Audio mode; average value interpolation and pre-value hold are performed.
Processing
Page 36
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CXD3000R
Command bit
Sync protection window width
WSEL = 1
WSEL = 0
±26 channel clock
±6 channel clock
Anti-rolling is enhanced.
Sync window protection is enhanced.
Application
∗
In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Function
ASHS = 0
ASHS = 1
The command transfer rate to SSP is set to normal speed.
The command transfer rate to SSP is set to half speed.
Command bit
Function
SOCT = 0
SOCT = 1
Sub Q is output from the SQSO pin.
Each output signal is output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-4.)
Command bit
Processing
VCOSEL1 = 0
VCOSEL1 = 1
Multiplier PLL VCO1 is set to normal speed.
Multiplier PLL VCO1 is set to approximately twice the normal speed.
Command bit
KSL3 KSL2
Processing
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/1 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/2 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/4 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/8 frequency-divided.
0
0
1
1
0
1
0
1
Command bit
VCOSEL2 KSL1 KSL0
Processing
Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided.
Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided.
Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided.
Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided.
Wide-band PLL VCO2 is set to high speed*, and the output is 1/1 frequency-divided.
Wide-band PLL VCO2 is set to high speed*, and the output is 1/2 frequency-divided.
Wide-band PLL VCO2 is set to high speed*, and the output is 1/4 frequency-divided.
Wide-band PLL VCO2 is set to high speed*, and the output is 1/8 frequency-divided.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
∗
Approximately twice the normal speed
∗
See "§4-8. Playback Speed" for settings.
∗
This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0.
Page 37
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CXD3000R
Command bit
Processing
VCO2 THRU = 0
VCO2 THRU = 1
V16M output is connected internally to VCKI. Set VCKI to low.
V16M output is not connected internally. Input the clock from VCKI.
Command bit
Processing
ERC4 = 0
ERC4 = 1
C2 error double correction is performed when DSPB = 1.
C2 error quadruple correction is performed when DSPB = 1.
∗
This command is sets internal or external connection for the VCO2 used in CAV-W mode.
Command bit
Processing
SCOR SEL = 0
SCOR SEL = 1
FSW signal is output.
GRSCOR (protected SCOR) is output.
∗
Used when outputting GRSCOR from the FSW pin.
Command bit
Processing
SCSY = 0
SCSY = 1
No processing.
GRSCOR (protected SCOR) synchronization is applied again.
∗
Used to resynchronize GRSCOR.
The rising edge signal of this command bit is used internally. Therefore, when resynchronizing GRSCOR, first
return the setting to 0 and then set to 1.
GRSCOR is the crystal accuracy SCOR signal with the motor wow removed, and is synchronized with
PCMDATA.
The resynchronization conditions are when GTOP = high or when the SCSY pin = high.
(Same as when SCSY = 1 is sent by the $8X command.)
∗
The CXD3000R has two multiplier PLL VCO1, and this command selects one of these VCO1.
Command bit
VCO1CS1 VCO1CS0
Processing
Low speed multiplier PLL VCO1 selected.
Do not set.
High speed multiplier PLL VCO1 selected.
Do not set.
0
0
1
1
0
1
0
1
Command
Data 4
MODE
specification
VCO1
CS1
VCO1
CS0
VCO2
THRU
0
D11 D10 D9 D8
Data 5
ERC4
SCOR
SEL
SCSY
D7 D6
D5
0
D4
Page 38
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CXD3000R
Command
Data 1
Function
specification
DCLV
ON-OFF
DSPB
ON-OFF
A.SEQ
ON-OFF
D.PLL
ON-OFF
D23 D22 D21 D20
Data 2
BiliGL
MAIN
BiliGL
SUB
FLFC
D19 D18
D17
0
D16
$9X commands
Command bit
DCLV on/off = 0
In CLVS mode
FSW = low, MON = high, MDS = Z; MDP = servo control signal,
carrier frequency of 230Hz at TB = 0 and 460Hz at TB = 1.
FSW = Z, MON = high; MDS = speed control signal, carrier frequency of
7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz.
When DCLV PWM
and MD = 1
(Prohibited in CLV-W
and CAV-W modes)
MDS = PWM polarity signal, carrier frequency
of 132kHz
MDP = PWM absolute value output (binary),
carrier frequency of 132kHz
When DCLV PWM
and MD = 0
MDS = Z
MDP = ternary PWM output, carrier frequency
of 132kHz
In CLVP mode
In CLVS and
CLVP modes
DCLV on/off = 1
(FSW, MON not
required)
CLV mode Contents
When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches
simultaneously with the CLVP/CLVS switching.
Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1.
Command bit
DSPB = 0
DSPB = 1
Normal-speed playback, C2 error quadruple correction.
Double-speed playback, C2 error double correction. (quadruple correction when ERC = 1)
Processing
FLFC is normally 0.
FLFC is 1 in CAV-W mode, for any playback speed.
Page 39
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CXD3000R
Command bit
DPLL = 0
∗
DPLL = 1
RFPLL is analog. PDO, VCOI and VCOO are used.
RFPLL is digital. PDO is high impedance.
Meaning
Command bit
BiliGL SUB = 0
BiliGL SUB = 1
STEREO
SUB
MAIN
Mute
BiliGL MAIN = 0 BiliGL MAIN = 1
Definition of bilingual capable MAIN, SUB and STEREO
The left channel input is output to the left and right channels for MAIN.
The right channel input is output to the left and right channels for SUB.
The left and right channel inputs are output to the left and right channels for STEREO.
∗
External parts for the FILI, FILO and PCO pins are required even when analog PLL is selected.
Command
Data 3
Function
specification
DAC
EMPH
DAC
ATT
0 0
D15 D14 D13 D12
Data 4
PLM3 PLM2 PLM1
D11 D10
D9
PLM0
D8
These command bits control the DAC.
Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel.
Command bit
DAC EMPH = 1
DAC EMPH = 0
Applies digital de-emphasis. The emphasis constants are τ1 = 50µs and τ2 = 15µs
when Fs = 44.1kHz.
Turns digital de-emphasis off.
Processing
Command bit
DAC ATT = 1
DAC ATT = 0
Identical digital attenuation control is used for both channels 1 and 2. When common
attenuation data is specified, the attenuation values for channel 1 are used.
Independent digital attenuation control is used for both channels 1 and 2.
Processing
• DAC PLAY MODE
Command
DAC play mode PLM3 PLM2 PLM1 PLM0
D11 D10 D9 D8
By controlling these command bits, the DAC outputs channel 1 and channel 2 can be output in 16 different
combinations of left channel, right channel, left + right channel, and mute.
The relationship between the commands and the outputs is shown in the table on the following page.
Page 40
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CXD3000R
PLM3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mute
L
R
L + R
Mute
L
R
L + R
Mute
L
R
L + R
Mute
L
R
L + R
Mute
Mute
Mute
Mute
L
L
L
L
R
R
R
R
L + R
L + R
L + R
L + R
Mute
Reverse
Stereo
Mono
PLM2 PLM1 PLM0 Channel 1 output Channel 2 output Remarks
Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel.
The output data of L + R is (L + R)/2 to prevent overflow.
Page 41
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CXD3000R
Command
Data 1
Audio CTRL 0 0 Mute ATT
D23 D22 D21 D20
Data 2
PCT1 PCT2
D19 D18
DADS SOC2
D17 D16
$AX commands
Command bit
Mute = 0
Mute = 1
Mute off if other mute
conditions are not set.
Mute on. Peak register
reset.
Meaning
Command bit
ATT = 0
ATT = 1
Attenuation off
–12dB
Meaning
Mute conditions
(1) When register A mute = 1.
(2) When Mute pin = 1.
(3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1).
(4) When GFS stays low for over 35ms (during normal speed).
(5) When register 9 BiliGL MAIN = Sub = 1.
(6) When register A PCT1 = 1 and PCT2 = 0.
(1) to (4) perform zero-cross muting with a 1ms time limit.
Command bit
PCT1
0
0
1
1
PCT2
0
1
0
1
Normal mode
Level meter mode
Peak meter mode
Normal mode
× 0dB
× 0dB
Mute
× 0dB
C1: double; C2: quadruple
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: double
Meaning PCM Gain ECC error correction ability
Description of level meter mode (see Timing Chart 1-4.)
• When the LSI is set to this mode, it performs digital level meter functions.
• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.
The initial 80 bits are Sub Q data (see §2. Subcode Interface). The last 16 bits are LSB first, which are 15-bit
PCM data (absolute values) and an L/R flag.
The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right
channel.
• The PCM data is reset and the L/R flag is reversed after one readout.
Then maximum value measuring continues until the next readout.
Page 42
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CXD3000R
Description of peak meter mode (see Timing Chart 1-5.)
• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the
left or right channel.
The 96-bit clock must be input to SQCK to read out this data.
• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal
register again.
In other words, the PCM maximum value detection register is not reset by the readout.
• To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.
• The Sub Q absolute time is automatically controlled in this mode.
In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in
the memory. Normal operation is conducted for the relative time.
• The final bit (L/R flag) of the 96-bit data is normally 0.
• The pre-value hold and average value interpolation data are fixed to level (– ∞) in this mode.
SENS output switching
• This command enables the SQSO pin signal to be output from the SENS pin.
When SOC2 = 0, SENS output is performed as usual.
When SOC2 = 1, the SQSO pin signal is output from the SENS pin.
At this time, the readout clock is input to the SCLK pin.
Note) SOC2 should be switched when SQCK = SCLK = high.
Command bit
DADS = 0
DADS = 1
Set to 0 when crystal = 33.8688MHz.
Set to 1 when crystal = 16.9344MHz.
Processing
Command bit
SOC2 = 0
SOC2 = 1
The SENS signal is output from the
SENS pin as usual.
The SQSO pin signal is output from the
SENS pin.
Processing
Page 43
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CXD3000R
• DAC digital attenuator
Command
Data 3
D15
AT1D7AT1D6AT1D5AT1D4AT1D3AT1D2AT1D1AT1D0AT2D7AT2D6AT2D5AT2D4AT2D3AT2D2AT2D1AT2D
0
Audio
Ctrl
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data 4 Data 5 Data 6
Note) AT1D7 to AT1D0 are the channel 1 ATT control bits.
AT2D7 to AT2D0 are the channel 2 ATT control bits.
Command bits
AT1D7 to AT1D0
(AT2D7 to AT2D0)
FF (H)
FE (H)
↓
01 (H)
00 (H)
0dB
–0.034dB
↓
–48.131dB
– ∞
Audio output
The attenuation data consists of 8 bits each for channels
1 and 2; the DAC ATT bit can be used to control
channels 1 and 2 with common attenuation data. (When
common attenuation data is specified, the attenuation
values for channel 1 are used.)
An attenuation value, from 00 (H) to FF (H), is
determined according to the following equation:
ATT = 20 log [input data/255] dB
Example: When the attenuation data is FA (H):
ATT = 20 log [250/255] dB = –0.172dB
• Soft mute
With the soft mute function, when the attenuation data goes from FF (H) and 00 (H) and vice versa, muting is
turned on and off over the muting time of 1024Fs [s] = 23.2 [ms] (Fs = 44.1kHz).
• Attenuation
Assume the attenuation data ATT1, ATT2 and ATT3, where ATT1 > ATT3 > ATT2. First, assume ATT1 is
transferred and then ATT2 is transferred. If ATT2 is transferred before ATT1 is reached (state "A" in the
diagram), then the value continues approaching ATT2. Next, if ATT3 is transferred before ATT2 is reached
(state "B" or "C" in the diagram), the attenuation begins approaching ATT3 from the current point. Note that it
takes 1024/Fs [s] (Fs = 44.1kHz for CD players) to transit between attenuation data (from 0dB to – ∞).
ATT1
A
B
C
ATT2
0dB
ATT3
Handling of the Attenuation Value
Page 44
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CXD3000R
• I/O sync circuit
Related pins: LRCK and XWO
During normal operation, the I/O sync circuit automatically synchronizes with the input LRCK, and its operation
proceeds in phase with the serial input data. However, there is a chance that synchronization will not be
performed if there is a great deal of jitter in LRCK, or if the power has just been turned on, etc. In this case,
forced synchronization is possible by setting XWO low for 2/Fs or more. Forced synchronization must also be
performed when switching the clock system such as when switching from CLV mode to CAV mode and vice
versa, or when switching the operating frequency, etc. The forced synchronization operation is performed at
the second rising edge of LRCK after the XWO pin is set low.
$BX commands
This command sets the traverse monitor count.
Command
Data 1 Data 2
Data 3 Data 4
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
2152142132122112102928272625242322212
0
Traverse monitor count
setting
• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control
goes off.
• The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT.
Page 45
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CXD3000R
Servo coefficient
setting
CLV CTRL ($DX)
Gain
MDP1
Gain
MDP0
Gain
MDS1
Gain
MDS0
Gain
CLVS
Gain
MDS1
0
0
0
0
1
1
Gain
MDS0
0
0
1
1
0
0
Gain
CLVS
0
1
0
1
0
1
GCLVS
–12dB
–6dB
–6dB
0dB
0dB
+6dB
Command
D23
Data 1
D22
D21
D20
Gain
DCLV0
Gain
DCLV1
PCC1
PCC0
D19
Data 2
Description
Valid only when DCLV = 1.
Valid when DCLV = 1 or 0.
D18
D17
D16
$CX commands
The spindle servo gain is externally set when DCLV = 1.
• CLVS mode gain setting: GCLVS
Note) When DCLV = 0, the CLVS gain is as follows.
When Gain CLVS = 0, GCLVS = –12dB.
When Gain CLVS = 1, GCLVS = 0dB.
Gain
MDP1
0
0
1
Gain
MDP0
0
1
0
GMDP
–6dB
0dB
+6dB
Gain
DCLV1
0
0
1
Gain
DCLV0
0
1
0
GDCLV
0dB
+6dB
+12dB
Gain
MDS1
0
0
1
Gain
MDS0
0
1
0
GMDS
–6dB
0dB
+6dB
• CLVP mode gain setting: GMDP: GMDS
• DCLV overall gain setting: GDCLV
Command bit
PCC1 PCC0
Processing
The VPCO1 and 2 signals are output.
The VPCO1 and 2 pin outputs are high impedance.
The VPCO1 and 2 pin outputs are low.
The VPCO1 and 2 pin outputs are high.
0
0
1
1
0
1
0
1
• This command controls the VPCO1 and VPCO2 pin signals.
Identical control can be performed for both VPCO1 and VPCO2 output with this setting. However, VPCO2 can
also be set to high impedance with the $E command FCSW separately from this setting.
Page 46
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CXD3000R
$DX commands
See "$CX commands".
Command bit
DCLV PWM MD = 1
DCLV PWM MD = 0
Digital CLV PWM mode specified. Both MDS and MDP are used.
CLV-W and CAV-W modes cannot be used.
Digital CLV PWM mode specified. Ternary MDP values are output.
CLV-W and CAV-W modes can be used.
Description
Command bit
TB = 0
TB = 1
TP = 0
TP = 1
Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes.
Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes.
Peak hold at a cycle of RFCK/4 in CLVS mode.
Peak hold at a cycle of RFCK/2 in CLVS mode.
Description
Command
Data 1
CLV CTRL
DCLV
PWM MD
TB TP
Gain
CLVS
D23 D22 D21 D20
Data 2
VP7 VP6 VP5 VP4
D19 D18 D17 D16
Data 3
VP3 VP2 VP1 VP0
D15 D14 D13 D12
The rotational velocity R of the spindle can be expressed with the following equation.
R =
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
256 – n
32
Command bit
FCSW PCC1 PCC0
Processing
The VPCO1 signal is output and the VPCO2 pin is high impedance.
The VPCO1 and 2 pin outputs are high impedance.
The VPCO1 pin output is low and the VPCO2 pin is high impedance.
The VPCO1 pin output is high and the VPCO2 pin is high impedance.
The VPCO1 and 2 signals are output.
The VPCO1 and 2 pin outputs are high impedance.
The VPCO1 and 2 pin outputs are low.
The VPCO1 and 2 pin outputs are high.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
• Processing for the $CX commands PCC1 and PCC2 and the $EX command FCSW is shown below.
Page 47
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CXD3000R
Command bit
VP0 to 7 = F0 (H)
:
VP0 to 7 = E0 (H)
:
VP0 to 7 = C0 (H)
:
VP0 to 7 = A0 (H)
:
VP0 to 7 = 80 (H)
:
VP0 to 7 = 60 (H)
:
VP0 to 7 = 40 (H)
VP0 to 7 = 20 (H)
VP0 to 7 = 00 (H)
Playback at 1/2 (1) × speed
to
Playback at 1 (2) × speed
to
Playback at 2 (4) × speed
to
Playback at 3 (6) × speed
to
Playback at (8) × speed
to
Playback at (10) × speed
to
Playback at (12) × speed
Playback at (14) × speed
Playback at (16) × speed
Description
Notes)
1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688 MHz and XTSL is high.
2. Values in parentheses are for when DSPB is 1.
E0 C0 A0 80
2
4
6
8
R – Relative velocity [Multiple]
VP0 to 7 setting value [HEX]
60 40
10
12
20 00
14
16
DSPB = 1
DSPB = 0
Page 48
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CXD3000R
$EX commands
Command
Data 1
SPD mode CM3 CM2 CM1 CM0
D23 D22 D21 D20
Data 2
EPWM SPDC ICAP SFSL
D19 D18 D17 D16
Data 3
VC2C HIFC LPWR VPON
D15 D14 D13 D12
Command bit
CM3 CM2 CM1
Description
Spindle stop mode.
∗
Spindle forward rotation mode.
∗
Spindle reverse rotation mode. Valid only when LPWR = 0
in any mode.
∗
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RFPLL capture range.
PLL servo mode.
Automatic CLVS/CLVP switching mode.
Used for normal playback.
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
CM0
0
0
0
0
1
0
Mode
STOP
KICK
BRAKE
CLVS
CLVP
CLVA
∗
See Timing Charts 1-6 to 1-12.
Command bit
EPWM SPDC ICAP
Description
Crystal reference CLV servo.
Used for playback in CLV-W
mode.
∗
Spindle control with VP0 to 7.
Spindle control with the external
PWM.
0
0
0
1
0
0
1
0
0
0
1
1
SFSL
0
0
0
0
VC2C
0
1
0
0
HIFC
0
1
1
1
LPWR
0
0
0
0
VPON
0
0
1
1
Mode
CLV-N
CLV-W
CAV-W
CAV-W
∗
Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
Page 49
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CXD3000R
Mode DCLV
DCLV PWM MD
LPWR Command Timing chart
CLV-N
CLV-W
CAV-W
0
1
1
1
0
0
1
0
0
0
0
0
0
1
0
1
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
1-6 (a)
1-6 (b)
1-6 (c)
1-7 (a)
1-7 (b)
1-7 (c)
1-8 (a)
1-8 (b)
1-8 (c)
1-9 (a)
1-9 (b)
1-9 (c)
1-10 (a)
1-10 (b)
1-10 (c)
1-11 (a)
1-11 (b)
1-11 (c)
1-12 (a)
1-12 (b)
1-12 (c)
Mode DCLV
DCLV PWM MD
LPWR Timing chart
CLV-N
CLV-W
CAV-W
1
1
1
0
1
0
0
0
0
0
1
0
1
0
1
1-13
1-14
1-15
1-16
1-17 (EPWM = 0)
1-18 (EPWM = 0)
1-19 (EPWM = 1)
1-20 (EPWM = 1)
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes.
Page 50
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CXD3000R
Command bit
FCSW = 0
FCSW = 1
The VPCO2 pin is not used and it is high impedance.
The VPCO2 pin is used and the pin signal is the same as VPCO1.
Processing
Command
SPD mode
Data 4
• This sets the gain when controlling the spindle with the phase
comparator in CAV-W mode.
D11 D10 D9 D8
Gain
CAV1
Gain
CAV0
FCSW 0
Gain
CAV1
0
0
1
1
Gain
CAV0
0
1
0
1
Gain
0dB
–6dB
–12dB
–18dB
Page 51
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CXD3000R
Timing Chart 1-3
Rch 16bit C2 Pointer Lch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
C2 Pointer for upper 8bits C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits C2 Pointer for lower 8bits
Lch C2 Pointer
LRCK
WDCK
CDROM = 0
C2PO
CDROM = 1
C2PO
48 bit slot
Page 52
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CXD3000R
Timing Chart 1-4
Level Meter Timing
96 clock pulses
WFCK
1 2 3
96 clock pulses
CRCF CRCF
1 2 3
Peak data of this section
16 bit
R/LL/R
96 bit data
Hold section
1 2 3 80 81 96
CRCF
SQCK
D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R
Peak data
L/R flag
Sub Q Data
See "Sub Code Interface"
15-bit peak-data
Absolute value display, LSB first
750ns to 120µs
SQCK
SQSO
SQSO
Page 53
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CXD3000R
Timing Chart 1-5
Measurement
Peak Meter Timing
96 clock pulses
CRCF
WFCK
1 2 3
Measurement Measurement
96 clock pulses
CRCF CRCF
1 2 3
SQCK
Page 54
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CXD3000R
Timing Chart 1-6
CLV-N mode DCLV = DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
L
L
L
Timing Chart 1-7
CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
Z
L
Z
Page 55
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CXD3000R
Timing Chart 1-8
CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
STOP
MDS
MDP
FSW
L
MON
(c) STOP
L
L
H
L
L
L
H
Timing Chart 1-9
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
Z
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
L
Z
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (b).
Page 56
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CXD3000R
Timing Chart 1-10
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
Z
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
Timing Chart 1-11
CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
H
Page 57
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CXD3000R
Timing Chart 1-12
CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
H
Timing Chart 1-13
CLV-N mode DCLV PWM MD = LPWR = 0
Z
MDS
MDP
Acceleration
Z
Deceleration
132kHz
7.6µs
n · 236 (ns) n = 0 to 31
Timing Chart 1-14
CLV-N mode DCLV PWM MD = 1, LPWR = 0
MDS
MDP
Acceleration Deceleration
132kHz
7.6µs
n · 236 (ns) n = 0 to 31
Output Waveforms with DCLV = 1
Page 58
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CXD3000R
Timing Chart 1-15
CLV-W mode DCLV PWM MD = LPWR = 0
Z
MDS
MDP
Acceleration
Z
Deceleration
264kHz
3.8µs
Output Waveforms with DCLV = 1
Timing Chart 1-16
CLV-W mode DCLV PWM MD = 0, LPWR = 1
Z
MDS
MDP
Acceleration
Z
264kHz
3.8µs
Output Waveforms with DCLV = 1
The BRAKE pulse is masked when LPWR = 1.
Timing Chart 1-17
CAV-W mode EPWM = DCLV PWM MD = LPWR = 0
MDP
Acceleration
Z
Deceleration
264kHz
3.8µs
Timing Chart 1-18
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
MDP
Acceleration
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
Page 59
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CXD3000R
Timing Chart 1-19
CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0
PWMI
MDP
H
L
H
L
Acceleration
Deceleration
Timing Chart 1-20
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
PWMI
MDP
H
L
H
Z
Acceleration
The BRAKE pulse is masked when LPWR = 1.
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes.
Page 60
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CXD3000R
[2] Subcode Interface
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK.
Sub Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
§2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
§2-2. 80-bit Sub Q Readout
Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µ s. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial
register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others.
• The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial
register.
For ring control 1, input and output are shorted during peak meter and level meter modes.
For ring control 2, input and output are shorted during peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result, the 96-bit clock must be input in peak meter mode.
• The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.)
• The high and low intervals for SQCK should be between 750ns and 120µs.
Page 61
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CXD3000R
Timing Chart 2-1
Internal
PLL clock
4.3218±∆MHz
WFCK
SCOR
EXCK
SBSO
750ns max
S0 · S1 Q R
WFCK
SCOR
EXCK
SBSO
S0·S1
Q R S T U V W
S0
·S1
P1 Q R S T U V W P1 P2 P3
Same Same
Subcode P.Q.R.S.T.U.V.W Read Timing
Page 62
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CXD3000R
Block Diagram 2-2
888888888
Order
Inversion
16
Peak detection
LOAD CONTROL
Ring control 2
CRCF
Mix
Monostable
multivibrator
CRCC
ABS time load control
for peak value
16 bit P/S registerRing control 1
SO SI
SQSO
SQCK
SHIFT
SHIFT
SUBQ
LD
LD
LD
LD
LD
LD
LD
LD
SO
H G F E D C B A
A B C D E F G H
SI
80 bit P/S Register
80 bit S/P Register
(AFRAM) (ASEC) (AMIN) ADDRS CTRL
SIN
SUBQ
Page 63
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CXD3000R
Timing Chart 2-3
1
2
3
91 92 93 94
95 96 97
98
WFCK
SCOR
SQSO
SQCK
Monostable
Multivibrator
(Internal)
CRCF1
Determined by mode
CRCF2
80 or 96 Clock
Register load forbidder
270 to 400µs when SQCK = high.
750ns to 120µs
300ns max
CRCF
ADR0
ADR1
ADR2
ADR3
CTL0
CTL1
CTL2
CTL3
SQCK
SQSO
1
2
3
CRCF1
Page 64
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CXD3000R
Timing Chart 2-4
Example: $8020 latch
Set SQCK high during this interval.
Internal signal latch
PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH
750ns or more
XLAT
SQCK
SQSO
ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7
Signal
PER0 to 7
FOK
GFS
LOCK
EMPH
ALOCK
VF0 to 7
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
Focus OK
High when the frame sync and the insertion protection timing match.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low.
High when the playback disc has emphasis.
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low.
Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF7 = MSB.
Description
C1F2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No C1 errors; C1 pointer reset
One C1 error corrected; C1 pointer reset
—
—
No C1 errors; C1 pointer set
One C1 error corrected; C1 pointer set
Two C1 errors corrected; C1 pointer set
C1 correction impossible; C1 pointer set
C1F1 C1F0 Description
C2F2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No C2 errors; C2 pointer reset
One C2 error corrected; C2 pointer reset
Two C2 errors corrected; C2 pointer reset
Three C2 errors corrected; C2 pointer reset
Four C2 errors corrected; C2 pointer reset
—
C2 correction impossible; C1 pointer copy
C2 correction impossible; C2 pointer set
C2F1 C2F0 Description
Page 65
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CXD3000R
Timing Chart 2-5
Measurement interval (approximately 3.8µs)
Reference window
(132.2kHz)
Measurement pulse
(V16M/2)
Measurement counter
VF0 to 7
Load
m
The relative velocity of the disc can be obtained with the following equation.
R = (R: Relative velocity, m: Measurement results)
VF0 to 7 is the result obtained by counting VLKI/2 pulses while the reference signal (132.2kHz) generated from
XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it
is rotating at double speed (when DSPB is low).
m + 1
32
Page 66
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CXD3000R
[3] Description of Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
§3-1. CLV-N Mode
This mode is compatible with the CXD2510Q, and operation is the same as for conventional control (however,
variable pitch cannot be used). The PLL capture range is ±150kHz.
§3-2. CLV-W Mode
This is the wide capture range mode. This mode allows PLL to follow the rotational velocity of the disc. This
rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is
the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below.
(When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from
the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the
VCKI pin.)
When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is
stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc,
then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin.
CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must
return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow
according to the microcomputer software in CLV-W mode is shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set
high, deceleration pulses are not output, thereby achieving low power consumption mode.
CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode,
set DCLV PWM MD to low.
Note) The capture range for this mode is theoretically up to the signal processing limit.
§3-3. CAV-W Mode
This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the
desired rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external
PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E665X command and
controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to 6×
speed. (See "$DX commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is
binary input which becomes KICK during high intervals and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. The reference frequency for the velocity
measurement is a signal of 132.3kHz obtained by dividing XTAL (XTLI, XTLO) (384Fs) by 128. The velocity is
obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU
interface as 8 bits (VP0 to 7). These measurement results are 31 when the disc is rotating at normal speed or
127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with VP0 to 7.
(See Table 2-5 and Fig. 2-6.)
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc.
Note) The capture range for this mode is theoretically up to the signal processing limit.
Note) Set FLFC to 1 for this mode
Page 67
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CXD3000R
CAV-W
CLVS
CLV-W
CLVP
Rotational velocity
Target speed
Operation mode
Spindle mode
Time
KICK
LOCK
ALOCK
Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode
CLV-W Mode
NO
YES
KICK $E8000
Mute OFF $A00XXXX
ALOCK = H ?
NO
YES
ALOCK = L ?
CLV-W MODE
START
CAV-W $E665X
(CLVA)
CLV-W $E6C00
(CLVA)
(WFCK PLL)
Fig. 3-2. CLV-W Mode Flow Chart
Page 68
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CXD3000R
[4] Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,
T, that is the channel clock, is necessary.
In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the
spindle rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD3000R has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when
not using the internal VCO2, external LPF and VCO are necessary.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the
secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components
such as 3T and 4T may contain deviations. In such as case, turning the secondary loop off yields better
playability. However, in this case the capture range becomes ±50kHz.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
Page 69
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CXD3000R
Block Diagram 4-1
XTSL
1/2 1/32
1/n
1/2
Microcomputer
control
n = 1 to 256
(VP7 to 0)
1/K
(KSL1, 0)
CLV-W
CAV-W
Spindle rotation information
CLV-N
CLV-W
CAV-W
/CLV-N
LPF
2/1 MUX
VPON
1/M
1/N
VCOSEL2
VCO2
Phase comparator
VCO1
VCOSEL1
1/K
(KSL3, 2)
Digital PLL
RFPLL
VPCO1 to 2
VCTL
V16M
VCKI
PCO
FILI
FILO
CLTV
XTLI
Clock input
Phase comparator
Selector
Page 70
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CXD3000R
§4-2. Frame Sync Protection
• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD3000R, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths; one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the
backward protection counter to 3. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be
detected for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
§4-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD3000R uses refined super strategy to achieve double correction for C1 and quadruple correction for
C2.
• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the
C1 error status, the playback status of the EFM signal, and the operating status of the player.
• The correction status can be monitored externally. See Table 4-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No C1 errors; C1 pointer reset
One C1 error corrected; C1 pointer reset
—
—
No C1 errors; C1 pointer set
One C1 error corrected; C1 pointer set
Two C1 errors corrected; C1 pointer set
C1 correction impossible; C1 pointer set
No C2 errors; C2 pointer reset
One C2 error corrected; C2 pointer reset
Two C2 errors corrected; C2 pointer reset
Three C2 errors corrected; C2 pointer reset
Four C2 errors corrected; C2 pointer reset
—
C2 correction impossible; C1 pointer copy
C2 correction impossible; C2 pointer set
MNT2 MNT1 MNT0 Description
Table 4-2.
Page 71
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CXD3000R
Timing Chart 4-3
Normal-speed PB
400 to 500ns
RFCK
MNT3
MNT1
MNT0
t = Dependent on error
condition
C1 correction C2 correction
Strobe
Strobe
MNT2
§4-4. DA Interface
• The CXD3000R has two DA interface modes.
a) 48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
b) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
Page 72
– 72 –
CXD3000R
Timing Chart 4-4
LRCK
(44.1K)
DA15
(2.12M)
WDCK
DA16
LRCK
(88.2K)
DA15
(4.23M)
WDCK
DA16
48bit slot Normal-Speed Playback PSSL = L
1
24
R0
Lch MSB (15)
L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB
Lch MSB (15)
24
Rch MSB
2 3 4 5 6 7 8 9 10 11 12
48bit slot Double-Speed Playback
1 2
L0
R0
Page 73
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CXD3000R
Timing Chart 4-5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 R15 L ch LSB (0)R ch LSB (0)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 30 3231
DA12
(44.1K)
DA13
(2.82M)
DA14
64 Bit slot Normal Speed PB PSSL = L
1 L ch LSB
1 2 3 4 5 10 15 25
DA12
(88.2K)
DA13
(5.64M)
DA14
64 Bit slot Double- Speed PB
20 30 31 32
R ch LSB (0) 2 3 5 6 7 8 9 10 11 12 13 14 154
L15
Page 74
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CXD3000R
§4-5. Digital Out
There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,
and the type 2 form 2 format for the manufacture of software.
The CXD3000R supports type 2 form 1.
The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in
CAV-W mode. In addition, Sub Q data which are matched twice in succession after a CRC check are input to
the first four bits (bits 0 to 3).
DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode.
Therefore, set MD2 to 0 and turn DOUT off.
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0
0
ID0
ID1
COPY
Emph
0 0 0 0 1 0 0 0 0 0 0 0
From sub Q
0
16
32
48
176
Sub Q control bits that matched twice with CRCOK
Digital Out C bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VPON: 1 Crystal: 0
Bits 0 to 3
Bit 29
Table 4-6.
Page 75
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CXD3000R
§4-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move
are executed automatically.
The servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that
commands from the CPU are not transferred to the servo, but can be sent to the CXD3000R.
In addition, when using the auto sequence, turn the A.SEQ of register 9 on.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes
from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external
disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY
format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed
auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like
$40). See [1] "$4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by
inputting $4X0.
Although this command is explained in the format of $4X in the following command descriptions, the timer
value and timer range are actually sent together from the CPU.
(a) Auto focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts with
focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition,
blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling
edge of FZC after FZC has been continuously high for a longer time than E.
(b) Track jump
1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are
not involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance
with Fig. 4-9. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in
accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition,
after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the
actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT
cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.
Page 76
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CXD3000R
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in
accordance with Fig. 4-11. The track jump count N is set with register 7. Although N can be set to 216
tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of
jumps when N is less than 16, and MIRR is used with N is 16 or more.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• Fine search
When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed
in accordance with Fig. 4-12. The differences from a 2N-track jump are that a higher precision is achieved
by controlling the traverse speed, and a longer distance jump achieved by controlling the sled. The track
jump count is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse
speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5.
Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of
tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake
is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and
by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking
and sled servos are turned on.
Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should
be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For
example, set the target track count N – α for the traverse monitor counter which is set with register B, and
COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset.
• M-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in
accordance with Fig. 4-13. M can be set to 216 tracks. Like the 2N-track jump, COUT is used for counting
the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move
is executed by moving only the sled, and is therefore suited for moving across several thousand to several
ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted
through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator
has stabilized.
Page 77
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CXD3000R
Auto focus
Focus search up
FOK = H
NO
YES
FZC = H
NO
YES
FZC = L
NO
YES
END
Focus servo ON
Check whether FZC is
continuously high for the
period of time E set with
register 5.
Fig. 4-8-(a). Auto Focus Flow Chart
XLAT
$47 Latch
$03
Blind E
$08
FOK
SEIN (FZC)
BUSY
Command for
SSP
Fig. 4-8-(b). Auto Focus Timing Chart
Page 78
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CXD3000R
1 Track
NO
YES
END
Track kick
sled servo
WAIT
(Blind A)
COUT =
Track REV
kick
WAIT
(Brake B)
Track sled
servo ON
FWD kick for
REV jump
REV kick for
REV jump
Fig. 4-9-(a). 1-Track Jump Flow Chart
XLAT
COUT
BUSY
Command for
SSP
$48 (REV = $49) Latch
$28 ($2C)
Blind A
Brake B
$2C ($28)
$25
Fig. 4-9-(b). 1-Track Jump Timing Chart
Page 79
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CXD3000R
10 Track
NO
YES
END
Track, sled
FWD kick
WAIT
(Blind A)
COUT = 5 ?
Track, REV
kick
Track, sled
servo ON
Check whether the COUT cycle
is longer than overflow C.
Counts
COUT × 5
NO
YES
C = Overflow ?
Fig. 4-10-(a). 10-Track Jump Flow Chart
COUT
$4A (REV = $4B) Latch
Blind A
$2A ($2F)
COUT 5 count
$2E ($2B)
Overflow C
$25
XLAT
BUSY
Command for
SSP
Fig. 4-10-(b). 10-Track Jump Timing Chart
Page 80
– 80 –
CXD3000R
2N Track
NO
YES
END
Track, sled
FWD kick
WAIT
(Blind A)
COUT (MIRR) = N
Track REV
kick
Track servo
ON
NO
YES
C = Overflow
WAIT
(Kick D)
Sled servo
ON
Counts COUT for the first 16
times and MIRR for more times.
Fig. 4-11-(a). 2N-Track Jump Flow Chart
XLAT
Blind A
$2A ($2F)
COUT (MIRR)
N count
$2E ($2B)
Overflow C
Kick D
$26 ($27)
$25
$4C (REV = $4D) Latch
COUT
(MIRR)
BUSY
Command for
SSP
Fig. 4-11-(b). 2N-Track Jump Timing Chart
Page 81
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CXD3000R
Track Servo ON
Sled FWD Kick
Fine Search
WAIT
(Kick D)
Track Sled
FWD Kick
WAIT
(Kick F)
Traverse
Speed Ctrl
(Overflow G)
COUT = N ?
Track Servo ON
Sled REV Kick
WAIT
(Kick D)
Track Sled
Servo ON
END
YES
NO
Fig. 4-12-(a). Fine Search Flow Chart
Traverse Speed Control (Overflow G)
&
COUT N count
Kick FKick D
$26 ($27)
$2A ($2F)
$27 ($26)
$25
$44 (REV = $45) latch
XLAT
COUT
Kick D
BUSY
Fig. 4-12-(b). Fine Search Timing Chart
Page 82
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CXD3000R
M Track Move
NO
YES
END
Track Servo OFF
Sled FWD Kick
WAIT
(Blind A)
COUT (MIRR) = M
Track, Sled
Servo ON
Counts COUT for
M < 16. Counts MIRR
for M ≥ 16.
Fig. 4-13-(a). M-Track Move Flow Chart
XLAT
Blind A
$22 ($23)
COUT (MIRR)
M count
$20
$4E (REV = $4F) Latch
COUT
(MIRR)
BUSY
Command for
servo
Fig. 4-13-(b). M-Track Move Timing Chart
Page 83
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CXD3000R
§4-7. Digital CLV
Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the
sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
MDP
Digital CLV
CLVS U/D MDS Error MDP Error
CLV P/S
Measure
Measure
2/1 MUX
Over Sampling
Filter-1
Gain
MDS
1/2
Mux
CLV P/S
Over Sampling
Filter-2
Noise Shape
Modulation
KICK, BRAKE, STOP
MDS
Mode Select
Gain
DCLV
Gain
MDP
DCLVMD, LPWR
PWMI
Fig. 4-14. Block Diagram
CLVS U/D : Up/down signal from CLVS servo
MDS error: Frequency error for CLVP servo
MDP error: Phase error for CLVP servo
PWMI: Spindle drive signal from the microcomputer for CAV servo
Page 84
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CXD3000R
§4-8. Playback Speed
In the CXD3000R, the following playback modes can be selected through different combinations of XTLI, XTSL
pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division
commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.
Mode
1
2
3
4
5
6
7
XTLI
768Fs
768Fs
768Fs
768Fs
384Fs
384Fs
384Fs
XTSL
1
1
0
0
0
0
1
DSPB
0
1
0
1
0
1
1
VCOSEL1
∗1
0/1
0/1
1
1
0/1
0/1
0/1
ASHS
0
0
1
1
0
0
0
Playback speed
1×
2×
2×
4×
1×
2×
1×
Error correction
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: double
∗1
Actually, the optimal value should be used together with KSL3 and KSL2.
The playback speed can be varied by setting VP0 to 7 in CAV-W mode. See "§3. Description of Modes" for
details.
Page 85
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CXD3000R
§4-9. DAC Block Playback Speed
• The DAC block playback speed is controlled by sending the DADS command to the DSP block.
Mode
1
2
768fs
384fs
0
1
X'tal DADS
§4-10. DAC Block Input Timing
The DAC input timing chart is shown below.
Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3000R. This
is to allow data to be sent to the DAC block via the audio DSP, etc.
When the data is input to the DAC block without using the audio DSP, the data must be connected outside the
LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI,
respectively. (See the Application Circuit.)
Normal-Speed Playback
L15
Invalid
L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
24 2322212019 18 17 161514 1312 11 10 9 8 7 6 5 4 3 21
L0
LRCKI
(44.1k)
BCKI
(2.12M)
PCMDI
Page 86
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CXD3000R
§4-11. Asymmetry Compensation
Fig. 4-15 shows the block diagram and circuit example.
ASYE
RFAC
R1
R1
ASYO
ASYI
R1 2
R2 5
=
BIAS
R1
R1
R2
D3000
22
14
16
17
15
Fig. 4-15. Asymmetry Compensation Application Circuit.
Page 87
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CXD3000R
§4-12. CXD3000R Clock System
The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according
to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below; during
normal use, FSTO and FSTI are directly connected to each other.
384fs or
768fs
XTLI
XTLO
OSC
DADS
(command register)
Clock supplied to DAC
384fs
To DAC block
To CD signal processor block
XTSL
MCKO
To exterior
FSTO
FSTI
External
connection
To digital servo block
XT2D
XT4D
(command register)
1/2
1/2
2/3
1/2
1/4
XT1D
Page 88
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CXD3000R
[5] Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of the Servo Signal Processing System (VDD: Supply voltage)
Focus servo
Sampling rate: 88.2kHz (when MCK = 128Fs)
Input range: 1/4VDD to 3/4VDD
Output format: 7-bit PWM
Other: Offset cancel
Focus bias adjustment
Focus search
Gain-down function
Defect countermeasure
Auto gain control
Tracking servo
Sampling rate: 88.2kHz (when MCK = 128Fs)
Input range: 1/4VDD to 3/4VDD
Output format: 7-bit PWM
Other: Offset cancel
E:F balance adjustment
Track jump
Gain-up function
Defect countermeasure
Drive cancel
Auto gain control
Vibration countermeasure
Sled servo
Sampling rate: 345Hz (when MCK = 128Fs)
Input range: 1/4VDD to 3/4VDD
Output format: 7-bit PWM
Other: Sled move
FOK, MIRR, DFCT signal generation
RF signal sampling rate: 1.4MHz (when MCK = 128Fs)
Input range: 1/4VDD to 3/4VDD
Other: RF zero level automatic measurement
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CXD3000R
§5-2. Digital Servo Block Master Clock (MCK)
The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the
frequency of the signal input to FSTI. The frequency division ratio is 1, 1/2 or 1/4.
Table 5-1 below assumes that the crystal clock generated from the digital signal processor block which is 2/3
frequency-divided of XTLI is input to the FSTI pin by externally connecting the FSTI pin and the FSTO pin.
The XT4D and XT2D command can be set with D13 and D12 of $3F, and the XT1D command can be set with
D1 of $3E. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
1
2
3
4
5
6
7
384Fs
384Fs
384Fs
768Fs
768Fs
768Fs
768Fs
256Fs
256Fs
256Fs
512Fs
512Fs
512Fs
512Fs
∗
∗
0
∗
∗
∗
1
∗
∗
0
∗
∗
1
0
∗
1
0
∗
1
0
0
1
0
0
1
0
0
0
1
1/2
1/2
1
1/2
1/4
1/4
256Fs
128Fs
128Fs
512Fs
256Fs
128Fs
128Fs
XTLI FSTO (FSTI) XTSL XT4D XT2D XT1D Frequency division ratio MCK
Fs = 44.1kHz, ∗: Don’t care
Table 5-1.
§5-3. AVRG (Average) Measurement and Compensation
The CXD3000R has a circuit that measures AVRG of RFDC, VC, FE and TE and a circuit that compensates
these signals to control the servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD3000R, and is able to cancel the
offset.
The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11
(RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement takes the level applied to each analog input pin as the average of 256 samples, and then
loads each value into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is
received.
During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See Timing Chart 5-2.)
XLAT
SENS
(= XAVEBSY)
Max. 1µs
AVRG measurement completed
2.9 to 5.8ms
Timing Chart 5-2.
Page 90
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CXD3000R
<Measurement>
• VC AVRG
The offset can be canceled by measuring the VC level which is the center voltage for the system and using
that value to apply compensation to each input error signal.
• FE AVRG
The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output
from the SENS pin during FCS SEARCH (focus search) using these measurement results.
• TE AVRG
The TE signal DC level is measured.
• RF AVRG
The MIRR, DFCT and FOK signals are generated from the RF signal. Since the FOK signal is generated by
comparing the RF signal at a certain level, it is necessary to establish a zero level which becomes the
comparator level reference. Therefore, the RF signal is measured before playback, and is compensated to
take this level as the zero level.
An example of sending AVRG measurement and compensation commands is shown below.
(Example) $380800 (RF AVRG measurement on)
$382000 (FE AVRG measurement on)
$380010 (TE AVRG measurement on)
$388000 (VC AVRG measurement on)
(Complete each AVRG measurement before starting the next.)
$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)
(The required compensation should be turned on together; see Fig. 5-3.)
An interval of 5.8ms (when MCK = 128Fs) or more must be maintained between each command, or the SENS
pin must be monitored to confirm that the previous command has been completed before the next AVRG
command is sent.
<Compensation>
See Fig. 5-3 for the contents of each compensation below.
• RFLC
The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.
(00 is input when the RF signal is lower than the RF AVRG value.)
• TCL0
The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.
• TCL1
The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.
• VCLC
The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.
• FLC1
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.
• FLC0
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.
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CXD3000R
§5-4. E:F Balance Adjustment Function
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value
(subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 5-3.)
§5-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 5-3.)
When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit
value of D9 to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing
Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops if the FBIAS value the value set beforehand in
FLB9 to 1 of $34 matches. Also, if the upper 8 bits of the command register are $3A at this time, the counter
stop can be monitored through SENS.
A B C
FBIAS setting value (FB9 to 1)
LIMIT value (FLB9 to 1)
SENS pin
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
Here, assume the FBIAS setting value FB9 to 1
and the FBIAS LIMIT value FBL9 to 1 like status
A. For example, if command registers FBUP = 0,
FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from
this status, down count starts from status A and
approaches the set LIMIT value. When the
FBIAS value matches FBL9 to 1, the counter
stops and the SENS pin goes to high. Note that
the up/down counter counts at each sampling
cycle of the focus servo filter. The number of
steps by which the count value changes can be
selected from 1, 2, 4 or 8 steps by FBV1 and
FBV0. When converted to FE input, 1 step
corresponds to 1/512 × VDD/2.
Page 92
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CXD3000R
TE AVRG
register
TLC1
TRVSC
register
TLC2
– –
To TRK/SLD In register
VC AVRG
register
TLC0
–
VCLC
–
TE, SE from A/D
FE AVRG
register
FLC1
FBIAS
register
FBON
– +
To FCS In register
FLC0
To FZC register
FE from A/D
–
RFLC
–
To RF In registerRFDC from A/D
RF AVRG
register
Fig. 5-3.
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CXD3000R
§5-6. AGCNTL (Automatic Gain Control) Function
The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with
the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but
also obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS
pin. (See Timing Chart 5-4 and "Description of SENS Signals".)
Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
SENS
(= AGOK)
Max. 11.4µs
AGCNTL completion
Timing Chart 5-4.
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related settings
The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS; Self-stop on/off
AGJ; Convergence completion judgment time
AGGF; Internally generated sine wave amplitude (AGF)
AGGT; Internally generated sine wave amplitude (AGT)
AGV1; AGCNTL sensitivity 1 (during rough adjustment)
AGV2; AGCNTL sensitivity 2 (during fine adjustment)
AGHS; Rough adjustment on/off
AGHT; Fine adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for 0
dB at 1kHz. However, since convergence values vary according to the characteristics of each
constituent element of the servo loop, FG and TG values should be set as necessary.
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CXD3000R
AGCNTL and default operation have two stages.
In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select
256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.
The sensitivity at this time can be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with
relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the
second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops
changing, the CXD3000R confirms that the AGCNTL coefficient has not changed for a certain period of time
(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 5-5.
Initial value
SENS
AGCNTL
Start
AGCNTL
completion
Convergence value
AGCNTL
coefficient value
Slope AGV1
AGHT
AGJ
Slope AGV2
Fig. 5-5.
Page 95
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CXD3000R
§5-7. FCS Servo and FCS Search (Focus Search)
The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)
Register name
Command
D23 to D20
D19 to D16
1 0 ∗ ∗
1 1 ∗ ∗
0 ∗ 0 ∗
0 ∗ 1 ∗
0 ∗ 1 0
0 ∗ 1 1
FOCUS SERVO ON (FOCUS GAIN NORMAL)
FOCUS SERVO ON (FOCUS GAIN DOWN)
FOCUS SERVO OFF, 0V OUT
FOCUS SER VO OFF, FOCUS SEARCH VOLTAGE OUT
FOCUS SEARCH VOLTAGE DOWN
FOCUS SEARCH VOLTAGE UP
0 0 0 0
FOCUS
CONTROL
0
Table 5-6.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation.
Fig. 5-8 shows the signals for sending $08 (FCS on) after that.
FCSDRV
RF
FOK
FE
FZC
FZC comparator level
$00 $02 $03
0
0
FCSDRV
RF
FOK
FE
FZC
$00 $02 $03
0
$08
Fig. 5-7. Fig. 5-8.
∗: Don’t care
Page 96
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CXD3000R
§5-8. TRK (Tracking) and SLD (Sled) Servo Control
The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.)
When the upper 4 bits of the command register are 2 (Hex), TZC is output to the SENS pin.
D23 to D20
D19 to D16
0 0 ∗ ∗
0 1 ∗ ∗
1 0 ∗ ∗
1 1 ∗ ∗
∗ ∗ 0 0
∗ ∗ 0 1
∗ ∗ 1 0
∗ ∗ 1 1
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
0 0 1 0
TRACKING
MODE
2
Table 5-9.
TRK Servo
The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode.
The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the
anti-shock circuit (described hereafter) enabled.
CXD3000R has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See Table
5-17.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by
multiplying this value by 1×, 2×, 3× or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with
$3. (See Table 5-10.)
SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off
by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1.
D23 to D20
D19 to D16
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
SLED KICK LEVEL (basic value × ±1)
SLED KICK LEVEL (basic value × ±2)
SLED KICK LEVEL (basic value × ±3)
SLED KICK LEVEL (basic value × ±4)
0 0 1 1
SELECT
3
Table 5-10.
∗: Don’t care
Register name
Command
Register name
Command
Page 97
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CXD3000R
§5-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and
loaded. The MIRR and DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of this envelope waveform.
The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value
from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)
The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4,
respectively, of $3C.
RF
Peak Hold
Bottom Hold
Peak Hold
– Bottom Hold
MIRR
MIRR Comp
(Mirror comparator level)
H
L
RF
Peak Hold1
Peak Hold2
Peak Hold2
– Peak Hold1
DFCT
(Defect comparator level)
H
L
SDF
Fig. 5-11.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 5-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
Fig. 5-12.
Page 98
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CXD3000R
§5-10. DFCT Countermeasure Circuit
The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become
easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation
circuit, and when DFCT goes high, applying the low frequency element of the error signal before DFCT went
high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38
to 1.
Input register
Hold register
Hold Filter
Servo Filter
EN
Error signal
DFCT
Fig. 5-13.
§5-11. Anti-Shock Circuit
When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the
servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 5-14.)
The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator
level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 5-17.)
This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up
mode by inputting high level to the ATSK pin.
When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS
pin.
TE
Anti Shock
Filter
TRK Gain Up
Filter
TRK Gain Normal
Filter
TRK
PWM Gen
ATSK
SENS
Comparator
Fig. 5-14.
Page 99
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CXD3000R
§5-12. Brake Circuit
Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180°
offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the
track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.)
TRK
DRV
FWD
JMP
REV
JMP
Servo ON
RF
Trace
MIRR
TE
0
0
TZC
Edge
TRKCNCL
TRK
DRV
SENS
TZC out
Inner track Outer track
TRK
DRV
REV
JMP
FWD
JMP
Servo ON
RF
Trace
MIRR
TE 0
0
TZC
Edge
TRKCNCL
TRK
DRV
SENS
TZC out
Outer track Inner track
Fig. 5-15. Fig. 5-16.
D23 to D20
D19 to D16
1 0 ∗ ∗
0 ∗ ∗ ∗
∗ 1 ∗ ∗
∗ 0 ∗ ∗
∗ ∗ 0 ∗
∗ ∗ 1 ∗
∗ ∗ ∗ 1
∗ ∗ ∗ 0
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN NORMAL
TRACKING GAIN UP
TRACKING GAIN UP FILTER SELECT 1
TRACKING GAIN UP FILTER SELECT 2
0 0 0 1
TRACKING
CONTROL
1
Fig. 5-17.
∗: Don’t care
Register name
Command
Page 100
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CXD3000R
§5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among
three different phases for each COUT signal application.
• HPTZC: For 1-track jumps
Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a
cut-off 1kHz digital HPF; when MCK = 128Fs.)
• STZC: For COUT signal generation when MIRR is externally input and for applications other than
COUT generation.
This is generated from sampling TE at 700kHz. (when MCK = 128Fs)
• DTZC: For High-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and 14 of $3.
When D15 = 1 : STZC
When D15 = 0 and D14 = 0 : HPTZC
When D15 = 0 and D14 = 1 : DTZC
When the DTZC is selected, the delay can be selected from two values with D14 of $36.
§5-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".)
Specified commands
$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
$391F: RF AVRG measurement result
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
$391D: FBIAS register value
•••
•••
tDLS
tSPW
1/fSCLK
MSB LSB
XLAT
SCLK
Serial Read Out Data
(SENS)
Item
Symbol
Min.
Typ.
Max.
Unit
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
31.3
15
16
MHz
ns
µs
Table 5-19.
During readout, the upper 8 bits of the command register must be 39 (Hex).
Fig. 5-18.
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