Datasheet CXD2589Q Datasheet (Sony)

CD Digital Signal Processor

Description

The CXD2589Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters, zero detection circuit, 1-bit DAC, and analog low-pass filter on a single chip.

Features

Digital Signal Processor (DSP) Block

• Playback mode supporting CAV

(Constant Angular Velocity)

– Frame jitter-free

– Allows 0.5 to double-speed continuous playback

– Allows relative rotational velocity readout

– Supports external spindle control

• Wide capture range playback mode

– Spindle rotational velocity following method

– Supports normal-speed and double-speed playback

• 16K RAM

• EFM data demodulation

• Enhanced EFM frame sync protection

• SEC strategy-based error correction

• Subcode demodulation and Sub Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry compensation circuit

• Serial bus-based CPU interface

• Error correction monitor signals, etc. are output

from a new CPU interface.

• Servo auto sequencer

• Digital audio interface output

• Digital peak meter

CXD2589Q

80 pin QFP (Plastic)

Absolute Maximum Ratings

• Supply voltage VDD –0.3 to +7.0 V

• Input voltage VI –0.3 to +7.0 V

(Vss – 0.3V to VDD + 0.3V)

• Output voltage VO –0.3 to +7.0 V

• Storage temperature

Tstg –40 to +125 °C

• Supply voltage difference VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD, and AVSS includes XVSS.

Recommended Operating Conditions

• Supply voltage VDD 3.4 to 5.25 V

• Operating temperature

Topr –20 to +75 °C

Note) The VDD (min.) for the CXD2589Q varies

according to the playback speed selection.

Digital Filter, DAC, Analog Low-Pass Filter Block

• DBB (Digital Bass Boost)

• Supports double-speed playback

• Digital de-emphasis

• Digital attenuation function

• Zero detection function

• 8Fs oversampling digital filter

• S/N: 100dB or more (master clock: 384Fs typ.)

Logical value: 109dB

• THD + N: 0.007% or less (master clock: 384Fs typ.)

• Rejection band attenuation: –60dB or less

Applications

CD players

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

Playback speed

2× 1×

∗1

1×

∗1

When the internal operation of the CD-DSP side is set to double-speed mode and the crystal oscillation frequency is halved, normal-speed playback results.

Input/Output Capacitances

• Input capacitance CI 12 (max.) pF

• Output capacitance CO 12 (max.) pF Note) Measurement conditions VDD = VI = 0V

VCO high speed

3.4

3.4 3.5

VDD (min.) [V]

CD-DSP block DAC block

VCO normal speed

fM = 1MHz

4.5

3.4

E96Y02A73

Block Diagram

CXD2589Q

C4M

RF

ASYI

ASYO

BIAS

XPCK

FILO

FILI

PCO

CLTV

FOK

SEIN

CNIN

VPCO

XTSL

VCKI

51

26 27

25

52

35

37 38 36

48 30

31 29 33

18 10 11

Clock

Generator

Asymmetry

Corrector

Digital

PLL

Servo

Auto

Sequencer

V16M

OSC

VCTL

28

Interface

XUGF

47

demodurator

Sub Code Processor

CPU

49

GFS

EFM

54

EMPH

56

WFCK

Error

Corrector

16K

RAM

Digital

C2PO

50

39

D/A

Interface

CLV

LRCK

41

Digital

OUT

PCMD

BCK

43

EMPHI

55

Over Sampling

BCKI

PCMDI

LRCKI

40

Serial-In Interface

Digital Filter

PWM PWM

62

42

44

3rd-Order

Noise Shaper

SYSM

Timing

Logic

24

TES1 TEST

23

79

XRST

3

RMUT

2

LMUT

70

XTAI

71

XTAO

12

13

DATO

14

XLTO

CLKO

6

SENS

7

DATA

8

XLAT

9

CLOK

15

16

SPOA

17

SPOB

57

XLON

58

SCOR

59

SBSO

5

EXCK

4

SQSO

SQCK

21

MDP

22

PWMI

53

DOUT

74

LOUT2

75

AIN2

76

AOUT2

67

LOUT1

66

AIN1

65

AOUT1

– 2 –

Pin Configuration

60

Vss

59

SBSO

EXCK

58

SCOR

57

WFCK

56

EMPHI

55

EMPH

54

DOUT

53

52

C4M

51

XTSL

50

C2PO

49

GFS

48

XPCK

47

DD

V

XUGF

46

45

Vss

44

BCKI

43

BCK

PCMD

PCMDI

4142

CXD2589Q

VDD

SYSM

AVss

DD

AV

AOUT1

AIN1

LOUT1

AVss

DD

XV

XTAI

XTAO

XVss AVss

LOUT2

AIN2

AOUT2

DD

AV AVss

XRST

DD

V

61 62 63 64 65 66 67 68

69

70 71

72

73

74 75 76 77 78 79 80

1

Vss

2

LMUT

3

RMUT

4

SQCK

5

SQSO

6

SENS

7

DATA

8

XLAT

9

CLOK

10

11

SEIN

12

CNIN

13

XLTO

DATO

14

15

CLKO

16

SPOB

SPOA

17

18

XLON

19

FOK

DD

V

20

Vss

40 39

38 37 36 35

34 33 32

31 30

29

28

27

26

25

24

23

22

21

LRCKI LRCK ASYO ASYI BIAS RF

DD

AV CLTV AVss FILI FILO PCO VCTL V16M VCKI VPCO TES1 TEST PWMI MDP

– 3 –

Pin Description

CXD2589Q

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

Symbol I/O Description

GND

VSS LMUT RMUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA

—

O O

O O O

— 1, 0 1, 0

I

1, 0 1, 0

I I I I I

1, 0 1, 0 1, 0

I

Left-channel zero detection flag. Right-channel zero detection flag. SQSO readout clock input. Sub Q 80-bit serial output. SENS output to CPU. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP.

Microcomputer extended interface (input A). 16 17

18 19

20 21 22 23 24 25 26 27 28 29 30 31

SPOB XLON

FOK VDD

VSS MDP PWMI TEST TES1 VPCO VCKI V16M VCTL PCO FILO FILI

O

— —

O

O O

I

I I I

I

1, 0

— —

1, Z, 0

1, 0

1, Z, 0

Analog

Microcomputer extended interface (input B).

Microcomputer extended interface (output).

Focus OK input.

Used for SENS output and the servo auto sequencer.

Power supply (+5V).

GND

Spindle motor servo control.

Spindle motor external control input.

TEST pin; normally GND.

Charge pump output for the wide-band EFM PLL.

VCO2 oscillation input for the wide-band EFM PLL.

VCO2 oscillation output for the wide-band EFM PLL.

VCO2 control voltage input for the wide-band EFM PLL.

Master PLL charge pump output.

Master PLL (slave = digital PLL) filter output.

Master PLL filter input. 32 33 34 35

AVSS CLTV AVDD RF

—

Analog GND.

—

I

Master VCO control voltage input.

Analog power supply (+5V).

—

EFM signal input.

– 4 –

CXD2589Q

Pin No.

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Symbol I/O Description

BIAS ASYI ASYO LRCK LRCKI PCMD PCMDI BCK BCKI VSS VDD XUGF XPCK GFS C2PO

O O

O

— — O O O O

I I

1, 0 1, 0

I

1, 0

I

1, 0

I

—

— 1, 0 1, 0 1, 0 1, 0

Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). D/A interface. LR clock output f = Fs. LR clock input. D/A interface. Serial data output (two's complement, MSB first). D/A interface. Serial data input (two's complement, MSB first). D/A interface. Bit clock output. D/A interface. Bit clock input. GND Power supply (+5V). XUGF output. Switched to MNT1 or RFCK output by a command. XPLCK output. Switched to MNT0 output by a command. GFS output. Switched to MNT3 or XRAOF output by a command.

C2PO output. Switched to GTOP output by a command. 51 52 53

54

55 56

57 58 59 60 61 62 63 64 65

XTSL C4M DOUT

EMPH

EMPHI WFCK

SCOR SBSO EXCK VSS VDD SYSM AVSS AVDD AOUT1

O O

O

O O O

— —

— — O

I

1, 0 1, 0

1, 0

I

1, 0 1, 0 1, 0

I

— —

I

— —

Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz.

4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode.

Digital Out output.

Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis.

Inputs a high signal when de-emphasis is on, and a low signal when

de-emphasis is off.

WFCK output.

Outputs a high signal when either subcode sync S0 or S1 is detected.

Sub P to W serial output.

SBSO readout clock input.

GND

Power supply (+5V).

Mute input. Active when high.

Analog GND.

Analog power supply (+5V).

Left-channel analog output. 66 67 68 69 70 71

AIN1 LOUT1 AVSS XVDD XTAI XTAO

O —

O

I

Left-channel operational amplifier input.

Left-channel LINE output.

—

Analog GND.

Power supply for master clock.

I

Crystal oscillation circuit input. Input the external master clock via this pin.

Crystal oscillation circuit output.

– 5 –

CXD2589Q

Pin No.

72 73 74 75 76 77 78 79 80

Symbol I/O Description

XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS XRST VDD

—

O

O — —

—

I

— —

I

—

GND for master clock. Analog GND. Right-channel LINE output. Right-channel operational amplifier input. Right-channel analog output. Analog power supply (+5V). Analog GND. System reset. Reset when low. Power supply (+5V).

Notes) • PCMD is an MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)

• XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before sync protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.

• GFS goes high when the frame sync and the insertion protection timing match.

• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed).

• C2PO represents the data error status.

• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

– 6 –

CXD2589Q

Electrical Characteristics DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Conditions

Min. Typ.

Max.

Unit

Applicable

pins

∗

Input voltage (1)

Input voltage (2)

Input voltage (3)

Output voltage (1)

Output voltage (2)

Output voltage (4)

High level input voltage Low level input voltage High level input voltage Low level input voltage

Input voltage High level output voltage

Low level output voltage High level output voltage Low level output voltage High level output voltage

Low level output voltage Input leak current Tri-state pin output leak current

VIH (1) VIL (1) VIH (2) VIL (2)

VIN (3) VOH (1)

VOL (1) VOH (2) VOL(2) VOH (4) VOL (4) ILI ILO

Schmitt input

Analog input IOH = –1mA

IOL = 1mA IOH = –1mA IOL = 2mA IOH = –0.28mA IOL = 0.36mA VI = 0 to 5.50V VO = 0 to 5.50V

0.7VDD

0.8VDD

Vss

VDD – 0.5

0

VDD – 0.5

0

VDD – 0.5

0 –5 –5

0.3VDD

0.2VDD VDD VDD

0.4

VDD

0.4

VDD

0.4 5 5

V V V V

V V

V V V V

V µA µA

∗

∗1,∗2,∗ ∗

Applicable pins

∗

1

XTSL, DATA, XLAT, PWMI, SYSM, EMPHI, PCMDI

∗

2

CLOK, XRST, EXCK, SQCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, SPOA, SPOB

∗

3

CLTV, FILI, RF, VCTL, AIN1, AIN2

∗

4

MDP, PCO, VPCO

∗

5

ASYO, DOUT, C4M, SBSO, SQSO, SCOR, EMPH, DATO, CLKO, XLTO, SENS, WFCK, V16M, LMUT, RMUT, XLON, LRCK, PCMD, BCK, XUGF, XPCK, GFS, RFCK, C2PO

∗

6

FILO

∗

7

SENS, PCO, VPCO

1

2

3

4

5

6

3

7

∗

note) : XVDDand XVSSare included for AV

Those are the same for the explanation from the next page.

and AV

PP

respectively.

SS

,

– 7 –

AC Characteristics

1. XTAI pin

(1) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

CXD2589Q

Item

Symbol Min. Typ.

Max. Unit

Oscillation frequency fMAX 15 34 MHz

(2) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. High level pulse width Low level pulse width Pulse cycle Input high level

tWHX tWLX

tCK

VIHX Input low level VILX Rise time, fall time

tR, tF

13 500 13

26

VDD – 1.0

tCK

tWHX

Max. Unit

500

1,000

0.8 10

tWLX

ns ns ns

V V

ns

XTAI

tR tF

(3) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item

Symbol Min. Typ. Max. Unit

Input amplitude V1 2.0 VDD + 0.3 Vp-p

VIHX

IHX × 0.9

V

DD/2

V

VIHX × 0.1

VILX

– 8 –

2. CLOK, DATA, XLAT, CNIN, SQCK and EXCK pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

CXD2589Q

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width

fCK

tWCK tSU tH tD tWL

fT fWT

CLK

DATA

XLT

EXCK

CNIN

SQCK

SQSO

SBSO

750 300 300 300 750

750

tSU

∗

1/fCK

tWCK tWCK

tH

tWT tWT

1/fT

tH

0.65

tD

MHz

ns ns ns ns ns

∗

MHz

ns

tWL

∗

In pseudo double-speed playback mode, except when SQSO is Sub Q Read, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.

3. BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol

BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time

BCKI

PCMDI

tW tSU tH tSU

Conditions

tW(BCKI)tW(BCKI)

VDD/2 VDD/2

tSU

(PCMDI)

Min.

94 18 18 18

t

H

Typ.

tSU

(LRCKI)

Max. Unit

ns ns ns ns

LRCKI

– 9 –

1-bit DAC, LPF Block Analog Characteristics

Analog Characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)

CXD2589Q

Item

Total harmonic distortion

S/N ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

(using A-weighting filter)

Crystal

384Fs 768Fs 384Fs 768Fs

Min.

96 96

For both items, Fs = 44.1kHz. The total harmonic distortion and S/N ratio measurement circuits are shown below.

150p

12k

680p

12k

22µ

100k

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Typ.

0.0050

0.0045

Max.

0.0070

0.0065 100 100

SHIBASOKU (AM51A)

Audio Analyzer

Unit

%

dB

TEST DISC

LPF External Circuit Diagram

768Fs/384Fs

Rch A

DATA RF

CXD2589Q

Lch B

Block Diagram for Measuring Analog Characteristics

Audio Analyzer

– 10 –

(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = – 20 to +75°C)

CXD2589Q

Item Symbol Output voltage Load resistance

∗

Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is

VOUT RL

Min.

8

Typ.

1.12

Max.

∗

Vrms

Applicable pins

Unit

kΩ

output.

Applicable pins

∗1

LOUT1, LOUT2

∗1 ∗1

– 11 –

Description of Functions

1. CPU Interface and Commands

• CPU Interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

750ns or more

CLOK

CXD2589Q

DATA

XLAT

Registers 4 to E

D1 D2 D3 D0 D1 D2 D3

Data

Address

750ns or more

Valid

300ns max

• Information on each address and the data is provided in Table 1-1.

• The internal registers are initialized by a reset when XRST is low; the initialization data is shown in Table 1-2. Note) When XLAT is low, SQCK must be set high.

– 12 –

CXD2589Q

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

D2 D1 D0

D3

D2 D1 D0

D3

D1 D0

D3 D2

D1 D0

D3 D2

D0

D3 D2 D1

D0

D3 D2 D1

—

AS0

AS1

AS2

AS3 0

—

0.02ms

0.05ms

0.09ms

0.18ms

0.36ms

1

—

1.45ms

2.9ms

5.8ms

11.6ms 0

—

1

2

4

8

16

32

64

128

256

512

1024

2048

4096

8192

16384

32768 1

—

0

1

0

KSL0

KSL1

KSL2

KSL3

VCO

SEL2

SOCT 0

VCO

SEL1

WSEL

DOUT

ON/OFF

Mute

DOUT

CDROM 0

—

0

—

0

—

DCOF 0

—

0

—

0

—

ZMUT

ZDPL

0

MCSL

DSPB

ON/OFF

1

SYCOF 0

0

ON/OFF

0

1

OPSL10OPSL1

SYCOF 0

0

DSPB

0

1

—

AD0

AD1

AD2

AD3

OPSL20OPSL2

AD4

AD5

AD6

AD7

AD8

AD9 0

SMUT

EMPH

0

ATT

Mute 0

0

BBSL

BSBST

LRWO

FMUT

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9 0

SMUT

EMPH

1

0

ATT

Mute 0

0

—

0

MTSL0

MTSL1

TRMO

TRMI 0

CPUSR SL0

SL1 1

—

Gain

0

MDS0

MDS1

MDP0

MDP1

—

VP0

VP1

VP2

VP3

VP4

VP5

VP6

VP7

Gain

TP

TB 0

1

CLVS

—

0

Gain

VPON

LPWR

HIFC

VC2C

SFSL

ICAP

SPDC

EPWM

CM0

CM1

CM2

CM3 0

CAV0

CAV1

Table 1-1

0

Address

Command

Command Table

1

0

D3 D2 D1 D0

Auto sequence

Register name

4

0

1

0

Blind (A, E),

Overflow (C)

Brake (B)

5

1

0

Kick (D)

Auto sequence

6

1

0

7

0

1

(N) track jump

count

MODE

specification

8

0

1

Function

9

– 13 –

0

1

specification

1

0

1

Audio CTRL A

1

0

1

0

1

Serial bus

CTRL

B

0

1

Servo coefficient

C

setting

0

1

CLV CTRL D

1

CLV mode E

CXD2589Q

Data 6

Data 5

Data 4

D3 D2 D1 D0

D2 D1 D0

D3

D2 D1 D0

D3

—

0

—

0

—

0

—

0

—

0

1

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

Data 3

Data 2

Data 1

D2 D1 D0

D3

D1 D0

D3 D2

D1 D0

D3 D2

D0

0

1

—

0

—

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

—

0

—

0

—

1

—

1

—

1

—

0

1

0

1

0

1

0

1

Table 1-2

Address

Command

Reset Initialization

1

0

D3 D2 D1

Auto sequence

Register name

4

1

0

Blind (A, E),

Overflow (C)

Brake (B)

5

1

0

Kick (D)

Auto sequence

6

1

0

1

(N) track jump

count setting

MODE

specification

7

8

0

1

Function

specification

9

– 14 –

0

1

Audio CTRL

Serial bus

A

B

1

CTRL

Servo coefficient

setting

C

1

CLV CTRL

D

1

CLV mode

E

1-1. The meaning of the data for each address is explained below. $4X commands

CXD2589Q

Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE

AS3

0 0 1 1 1 1

AS2

0 1 0 0 1 1

AS1

0 1 0 1 0 1

AS0

0

1 RXF RXF RXF RXF

RXF = 0 FORWARD RXF = 1 REVERSE

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting Setting timers: A, E, C, B

Command

Blind (A, E), Over flow (C)

D3

0.18ms

D2

0.09ms

D1

0.05ms

D0

0.02ms

Brake (B)

0.36ms

0.18ms

Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)

A = E = C = 0.11ms B = 0.23ms

$6X commands

Auto sequence timer setting Setting timer: D

Command

KICK (D)

D3

11.6ms

D2

5.8ms

Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms

$7X commands

Auto sequence track jump/move count setting (N)

Data 1 Data 2

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Auto sequence track jump count setting

2152142132122112102928272625242322212

0.09ms

D1

2.9ms

0.05ms

D0

1.45ms

Data 3 Data 4

0

This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence.

• The maximum track count is 65,535, but note that with 2N-track jumps the maximum track jump count is determined by the mechanical limitations of the optical system.

• The number of tracks jumped is counted according to the signals input from the CNIN pin.

– 15 –

$8X commands

CXD2589Q

Command

MODE specification

Command bit

CDROM = 1

CDROM = 0

Data 1

D3

CDROM

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

DOUT

Mute

DOUT

ON/OFF

WSEL

Data 4

D3

D2 D1 D0

0010

C2PO timing

See Timing Chart 1-1.

VCO

SEL1

Data 2

0

SOCT

VCO

SEL2

KSL3 KSL2 KSL1 KSL0

Data 3

See the $BX commands.

Processing

CDROM mode; average value interpolation and pre-value hold are not performed.

Audio mode; average value interpolation and pre-value hold are performed.

Command bit DOUT Mute = 1 DOUT Mute = 0

Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.

Command bit DOUT ON/OFF = 1 DOUT ON/OFF = 0

Command bit

WSEL = 1 WSEL = 0

∗

1

In normal-speed playback, channel clock = 4.3218MHz.

Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin.

Sync protection window width ±26 channel clock

∗1

±6 channel clock

Processing

Application Anti-rolling is enhanced. Sync window protection is enhanced.

– 16 –

CXD2589Q

Command bit

VCOSEL1

0

1

∗1

Approximately twice the normal speed.

KSL3 KSL2

0

1

0

1

0

1

0

1

0

1

0

1

Processing

Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8 frequency-divided.

Command bit

VCOSEL2

0

1

∗2

Approximately twice the normal speed.

KSL1 KSL0

0

1

0

1

0

1

0

1

0

1

0

1

Processing

Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/1 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/2 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/4 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/8 frequency-divided.

– 17 –

If C2 Pointer = 1,

data is NG

CXD2589Q

Rch 16bit C2 Pointer Lch 16bit C2 Pointer

Lch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Rch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Timing Chart 1-1

LRCK

C2PO

CDROM = 0

– 18 –

C2PO

CDROM = 1

CXD2589Q

$9X commands (OPSL1= 0)

Data 1

Command

D3

Function specification

D2 D1 D0 D3

DSPB

0

ON/OFF

$9X commands (OPSL1= 1)

Data 1

Command

D3

Function specification

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

DSPB

0

ON/OFF

∗

Data 2 D0 and subsequent data are DF/DAC function settings.

Data 2

D3 to D1

0

0 0 MCSL 0 0

000

D0

SYCOF

Data 3

D2

D1 D0 D3 D2 D1 D0

ZDPL

OPSL1

D3

—

∗

Data 2 D0 and subsequent data are DF/DAC function settings.

Data 3

D3 to D1

0

000

0

D0

SYCOF

1 MCSL 0 0 ZDPL ZMUT 0 0

OPSL1

Data 4

ZMUT — —

Data 5

D2 D1 D0

———

Data 4Data 2

Data 5

Command bit

DSPB = 1 DSPB = 0

Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block)

Command bit

SYCOF = 1 SYCOF = 0

∗

Set SYCOF = 0 in advance when setting the $AX command LRWO to 1.

LRCK asynchronous mode Normal operation

Command bit

OPSL1 = 1 OPSL1 = 0

DCOF can be set. DCOF cannot be set.

Processing

D3

D2 D1 D0

0 DCOF 0 0

Command bit

MCSL = 1 MCSL = 0

Processing DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)

– 19 –

CXD2589Q

Command bit

ZDPL = 1 ZDPL = 0

∗

See "Mute flag output" for the mute flag output conditions.

LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted.

Command bit

ZMUT = 1 ZMUT = 0

Zero detection mute is on. Zero detection mute is off.

Command bit

DCOF = 1 DCOF = 0

∗

DCOF can be set when OPSL1 = 1.

∗

Set DC offset to off when zero detection mute is on.

DC offset is off. DC offset is on.

Processing

$AX commands (OPSL2 = 0)

Data 1

Command

D3

Audio CTRL

D1 D0

AD9 AD8

D2 D1 D0 D3

0

0 Mute ATT 0 0 0 EMPH

D3

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

$AX commands (OPSL2 = 1)

Data 1

Command

D3

Audio CTRL

D2 D1 D0 D3 D2 D1 D0

0 0 Mute

∗

Data 2 and subsequent data are DF/DAC function settings.

Data 2

D2 D1

D0

OPSL2

Data 4

D2

D1 D0

∗

D3 D2 D1

Data 2 and subsequent data are DF/DAC function settings.

Data 5

Data 2

ATT 0 0 1 EMPH

Data 3

D3 D2

SMUT 0

D0

Data 3

D3 D2

SMUT

Data 6Data 3

D3 D2 D1 D0

————

0

Data 3

D1 D0

AD9

AD8

Data 4

D3

D2 D1 D0

AD7 AD6

AD5 AD4

OPSL2

Data 5

D3

D2

D1

D0

D3 D2

AD3 AD2 AD1 AD0 FMUT LRWO

– 20 –

Data 6

BSBST

D1 D0

BBSL

CXD2589Q

Command bit

Mute = 1 Mute = 0

Command bit

ATT = 1 ATT = 0

Command bit

OPSL2 = 1 OPSL2 = 0

Command bit

EMPH = 1

Processing CD-DSP block mute is on. 0 data is output from the CD-DSP block. CD-DSP block mute is off.

Processing CD-DSP block output is attenuated (–12dB). CD-DSP block attenuation is off.

Meaning FMUT, LRWO, BSBST and BBSL can be set. FMUT, LRWO, BSBST and BBSL cannot be set.

Processing

De-emphasis is on.

EMPH = 0

∗

If either the EMPHI pin or EMPH is high, de-emphasis is on.

De-emphasis is off.

Command bit

SMUT = 1 SMUT = 0

∗

If either the SMUT pin or SMUT is high, soft mute is on.

Soft mute is on. Soft mute is off.

Command bit

AD9 to 0 Attenuation data.

The attenuation data consists of 10 bits, and is set as follows.

Attenuation data

3FFh 3FEh

3FDh

Audio output

0dB

–0.0085dB

–0.017dB

The attenuation data (AD9 to AD0) consists of 10bits, and can be set in 1023 different ways. The audio output from 001h to 3FFh is obtained using the following equation.

:

001h 000h

–60.198dB

– ∞

Audio output = 20 log [dB]

Processing

Meaning

Attenuation data

1024

– 21 –

CXD2589Q

Command bit

FMUT = 1 FMUT = 0

∗

FMUT can be set when OPSL2 = 1.

Forced mute is on. Forced mute is off.

Command bit

LRWO = 1 LRWO = 0

∗

LRWO can be set when OPSL2 = 1.

Forced synchronization mode Normal operation.

Note)

Meaning

Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need

to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.

Command bit

BSBST = 1 BSBST = 0

∗

BSBST can be set when OPSL2 = 1.

Bass boost is on. Bass boost is off.

Processing

Command bit

BBSL = 1 BBSL = 0

∗

BBSL can be set when OPSL2 = 1.

Bass boost is Max. Bass boost is Mid.

Processing

– 22 –

CXD2589Q

D0

D1

D2

D3

D0

D1

Data 1 Data 2

D2

D3

MTSL0

MTSL1

TRM0

TRM1

0

CPUSR

SL0

SL1

The SQSO pin output can be switched to the various

signals by setting the SOCT command of $8X and the SL1

and SL0 commands of $BX. Set SQCK to high at the

falling edge of XLAT.

Except for Sub Q and peak meter, the signals are loaded

to the register when they are set at the falling edge of

XLAT. Sub Q is loaded to the register with each SCOR,

and Peak meter is loaded when a peak is detected.

mode

SubQ

Peak meter

SL0

SL1

SENSDSubQAB

0

1

0

1

0

1

0

1

0

C

0

1

PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F1 0C1F2 C2F1 0C2F2 FOK LOCKGFS EMPH VF0ALOCK VF1 VF2 VF3 VF4 VF5 VF6 VF7PER0

VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 ALOCK C1F1 C1F2 0 C2F1 0C2F2 FOK LOCKGFS EMPH

LOCKEMPH RFCKWFCK SCOR00SPOB GTOP

PER1 PER2 PER3 PER4 PER5 PER6 PER7PER0 C1F1 C1F2 0 C2F1 0C2F2 FOK LOCKGFS EMPH0

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

SPOA C1F1 C1F2 C2F1 C2F2XRAOFFOKGFS

Command

$BX commands

Serial bus

CTRL

0

SOCT

XLAT

0

1

SQCK

mode A

mode B

mode C

mode D

Peak meter

– 23 –

CXD2589Q

Signal

PER0 to 7

FOK GFS

LOCK

EMPH

ALOCK

VF0 to 7 SPOA, B

WFCK SCOR

GTOP RFCK

XRAOF

L0 to L7, R0 to R7

Description RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight

consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is

output. If GFS is low eight consecutive samples, a low signal is output. Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)

VF0 = LSB, VF7 = MSB. SPOA and B pin inputs. Write frame clock output. High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output. Low when the built-in 16K RAM exceeds the ±4 frame jitter margin. Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak

data. L0 and R0 are LSB.

C1F1

0 1 1

Command bit

CPUSR = 1 CPUSR = 0

C1F2 C1 correction status C2F1

0 0 1

No Error Single Error Correction Irretrievable Error

0 1 1

Processing XLON pin is high. XLON pin is low.

C2F2 C2 correction status

0 0 1

No Error Single Error Correction Irretrievable Error

– 24 –

Peak meter

XLAT

SQCK

CXD2589Q

SQSO

(Peak meter)

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is restarted 270µs to 400µs after SQCK input.

The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak detection register.

Peak detection can also be performed for previous value hold and average value interpolation data.

Traverse monitor count value setting

These bits are set when monitoring the traverse condition of the SENS output according to the CNIN frequency division.

Command bit

TRM1

0 0 1 1

TRM0

0 1 0 1

1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division

Processing

Monitor output switching

The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.

Mode description

Command bit

MTSL1

0 0 1

Pin No.

MTSL0

0 1 0

47

XUGF MNT1 RFCK

48

XPCK MNT0 XPCK

49

GFS MNT3 XROF

50

C2PO C2PO GTOP

– 25 –

$CX commands

CXD2589Q

Command

Servo coefficient setting

D3

Gain

MDP1

CLV CTRL ($DX)

• CLV mode gain setting: GCLVS Gain

MDS1

0 0 0 0 1 1

Gain

MDS0

0 0 1 1 0 0

Gain

CLVS

0 1 0 1 0 1

GCLVS

–12dB

–6dB –6dB

0dB 0dB

+6dB

• CLVP mode gain setting: GMDP: GMDS

D2

Gain

MDP0

D1

Gain

MDS1

D0

Gain

MDS0

Gain

CLVS

Gain

MDP1

0 0 1

Gain

MDP0

0 1 0

GMDP

–6dB

0dB

+6dB

Gain

MDS1

0 0 1

Gain

MDS0

0 1 0

GMDS

–6dB

0dB

+6dB

– 26 –

$DX commands

CXD2589Q

Data 1

Data 2

Command

CLV CTRL

D3

0

D2 D1 D0 D3 D2 D1 D0 D3 D2 TB TP

Gain

CLVS

VP7 VP6 VP5 VP4

See the $CX commands.

Command bit Description

TB = 0 TB = 1 TP = 0 TP = 1

Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

The rotational velocity R of the spindle can be expressed with the following equation.

Command bit Description

VP0 to 7 = F0 (H)

:

VP0 to 7 = E0 (H)

Playback at half (normal) speed

to Playback at normal (double) speed

R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value

R =

256 – n

32

Data 3

D1 D0

VP3 VP2 VP1

VP0

Note) • Values in parentheses are for when DSPB is 1.

• Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.

• VP0 to 7 setting values are valid in CAV-W mode.

2

1.5

1

0.5

R – Relative velocity [multiple]

F0 E0

VP0 to 7 setting value [HEX]

Fig. 1-1

DSPB = 1

DSPB = 0

– 27 –

$EX commands

CXD2589Q

Command

Data 1

D3 D2 D1

CLV mode CM3 CM2 CM1 CM0

Command bit

CM3

0 1

1

1 0

∗1

See Timing Charts 1-2 to 1-6.

CM2 CM1

0 0

0

1

1 1

0 0

1

1 1

CM0

0 0

0

1 0

D0

Mode

STOP

KICK

BRAKE

CLVS

CLVP CLVA

Data 2

D3

D2 D1 D0

EPWM SPDC ICAP SFSL

D3

VC2C HIFC LPWR VPON

Data 3

D2 D1

Description

Spindle stop mode. Spindle forward rotation mode.

∗1

Spindle reverse rotation mode. Valid only when LPWR = 0, in any mode.

∗1

Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range.

PLL servo mode. Automatic CLVS/CLVP switching mode.

Used for normal playback.

D0

Command bit

Mode

EPWM SPDC

0 0 0 1

∗2

Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.

ICAP

0 0 1 0

SFSL

0 0 1 1

VC2C

0 0 0 0

HIFC

0 1 0 0

LPWR

0 1 1 1

VPON

0 0 0 0

0 0 1 1

CLV-N CLV-W CAV-W CAV-W

Crystal reference CLV servo. Used for normal-speed

playback in CLV-W mode. Spindle control with VP0 to 7. Spindle control with the external

PWM.

Description

∗2

– 28 –

CXD2589Q

Command

SPD mode

Gain

CAV1

0 0 1 1

Mode

CLV-N

Gain

CAV1

Gain

CAV0

0 1 0 1

D3 D2

Gain

CAV0

Gain

0dB

–6dB –12dB –18dB

LPWR

0

Data 4

D1

0

D0

0

• This sets the gain when controlling the spindle with the phase comparator in CAV-W mode.

Command

KICK

BRAKE

STOP

Timing chart

1-2 (a) 1-2 (b) 1-2 (c)

CLV-W

CAV-W

Mode

CLV-N

CLV-W

0

1

0

1

LPWR

0 0 1

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

Timing chart

1-3 (a) 1-3 (b) 1-3 (c) 1-4 (a) 1-4 (b) 1-4 (c) 1-5 (a) 1-5 (b) 1-5 (c) 1-6 (a) 1-6 (b) 1-6 (c)

1-7 1-8 1-9

CAV-W

0 1 0 1

1-10 (EPWM = 0) 1-11 (EPWM = 0) 1-12 (EPWM = 1) 1-13 (EPWM = 1)

– 29 –

Timing Chart 1-2 CLV-N mode LPWR = 0

CXD2589Q

MDP

KICK

H

Z

(a) KICK

MDP

BRAKE

Z

L

(b) BRAKE

Timing Chart 1-3 CLV-W mode (when following the spindle rotational velocity) LPWR = 0

MDP

KICK

H

Z

(a) KICK

MDP

BRAKE

Z

L

(b) BRAKE

Timing Chart 1-4 CLV-W mode (when following the spindle rotational velocity) LPWR = 1

MDP

KICK

H

Z

MDP

BRAKE

Z

MDP

STOP

Z

(c) STOP

STOP

Z

(c) STOP

STOP

Z

(a) KICK

Timing Chart 1-5 CAV-W mode LPWR = 0

KICK

MDP

H

(a) KICK

Timing Chart 1-6 CAV-W mode LPWR = 1

KICK

MDP

H

(a) KICK

MDP

(b) BRAKE

BRAKE

L

(b) BRAKE

BRAKE

Z

(b) BRAKE

MDP

(c) STOP

STOP

Z

(c) STOP

STOP

Z

(c) STOP

– 30 –

Timing Chart 1-7 CLV-N mode LPWR = 0

Acceleration

CXD2589Q

n · 236 (ns) n = 0 to 31

MDP

132kHz

7.6µs

Timing Chart 1-8 CLV-W mode LPWR = 0

Acceleration

MDP

264kHz

3.8µs

Timing Chart 1-9 CLV-W mode LPWR = 1

Acceleration

MDP

264kHz

3.8µs

Z

Deceleration

Z

Deceleration

Z

Timing Chart 1-10 CAV-W mode EPWM = LPWR = 0

Acceleration

MDP

264kHz

3.8µs

Timing Chart 1-11 CAV-W mode EPWM = LPWR = 1

Acceleration

MDP

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

Z

Deceleration

Z

– 31 –

The BRAKE pulse is masked when LPWR = 1.

Timing Chart 1-12 CAV-W mode EPWM = 1, LPWR = 0

H

CXD2589Q

PWMI

H

MDP

L

Timing Chart 1-13 CAV-W mode EPWM = LPWR = 1

H

PWMI

H

MDP

L

Z

Acceleration

Deceleration

Acceleration

The BRAKE pulse is masked when LPWR = 1.

– 32 –

CXD2589Q

1-2. Description of SENS Output

The following signals are output from SENS, depending on the microcomputer serial register value (latching not required).

Microcomputer serial register value (latching not required)

$0X, 1X, 2X, 3X $4X

$5X $6X

$AX $EX $7X, 8X, 9X, BX, DX, FX

$CX

SENS output

SEIN XBUSY

FOK SEIN

GFS OV64 “L” CNIN

division

Meaning

SEIN, a signal input to this LSI from the SSP, is output. Low while the auto sequencer is in operation, high when operation

terminates. Outputs the signal input to the FOK pin. Normally, FOK (from RF) is

input. High for "focus OK". SEIN, a signal input to this LSI from the SSP, is output. High when the regenerated frame sync is obtained with the correct timing. Low when the EFM signal, after passing through the sync detection

filter, is lengthened by 64 channel clock pulses or more. SENS pin is fixed to low. Calculates the number of tracks from the frequency division ratio set

by $B.High when $C is latched; toggles each time CNIN is input the number of times set in register B.

Note that the SENS output can be read out from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0. (See the $BX commands.)

2. Subcode Interface

This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2589Q. Sub Q can be read out after checking the CRC of the 80bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high.

2-1. P to W Subcode Readout

Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)

2-2. 80-bit Sub Q Readout

Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.

• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.

• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80bits are loaded into the parallel/serial register. When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the CPU determines that new data (which passed the CRC check) has been loaded.

• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

• The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.

• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.)

• The high and low intervals for SQCK should be between 750ns and 120µs.

– 33 –

Timing Chart 2-1

Internal PLL clock

4.3218 ± ∆MHz

WFCK

SCOR

EXCK

CXD2589Q

400ns max

SBSO

WFCK

SCOR

EXCK

SBSO

S0 · S1 Q R

S0·S1 Q R S T U V W

Same Same

S0·S1

P1 Q R S T U V W P1 P2 P3

Sub Code P.Q.R.S.T.U.V.W Read Timing

– 34 –

ADDRS CTRL

CXD2589Q

SO

SQCK

8

SQSO

LD

(AMIN)

8

80bit S/P Register

8

LD

80bit P/S Register

LD

SHIFT

Mono/Multi

CRCF

Mix

(ASEC)

(AFRAM)

A B C D E F G H

SIN

SUBQ

Fig. 2-1. Block Diagram

Order

Inversion

8

LD

H G F E D C B A

SI

SUBQ

CRCC

– 35 –

CTL3

CXD2589Q

98

91 92 93 94

95 96 97

CRCF2

CTL2

CTL1

L

CTL0

3

ADR3

2

1

Determined by mode

270µs to 400µs for SQCK = High

ADR2

80 Clock

Order

Inversion

3

2

1

CRCF1

WFCK

SCOR

SQSO

Registere load forbidder

SQCK

750ns to 120µs

Mono/multi (Internal)

SQCK

ADR1

ADR0

CRCF

SQSO

300ns max

Timing Chart 2-2

– 36 –

Timing Chart 2-3

Reference window

(132.2kHz)

CXD2589Q

Measurement interval (approximately 3.8µs)

Measurement pulse

Measurement counter

(VCKI/2)

VF0 to 7

Load

m

The relative velocity R of the disc can be expressed with the following equation.

m + 1

R = (R: Relative velocity, m: Measurement results)

32

VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low).

– 37 –

CXD2589Q

3. Description of Modes

This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below.

3-1. CLV-N Mode

This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control. The PLL capture range is ±150kHz.

3-2. CLV-W Mode

This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to the VCKI pin.) While starting to rotate a disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. This is because the capture range for CLV-W mode is wider than the conventional lock range. Concretely, first send $E6650 to set CAV-W mode and kick the disc, then send $E60C0 to set CLV-W mode when ALOCK is high. Playback is normally performed in CLV-W mode. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode.

Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit.

3-3. CAV-W Mode

This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low-speed to double-speed. (See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. These values match those of the 256-n for control with VP0 to 7. In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc (excluding DATO, CLKO and XLTO).

Note) The capture range for this mode is theoretically up to the signal processing limit.

– 38 –

CXD2589Q

Rotational velocity

Target velocity

LOCK

ALOCK

CAV-W

CLVS

KICK

CLV-W

CLVP

Operation mode

Spindle mode

Time

CLV-W Mode

Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode

CLV-W MODE

START

KICK $E8000 Mute OFF $A0XXXXX

CAV-W $E6650

(CLVA)

NO

ALOCK = H ?

YES

CLV-W $E60C0

(CLVA)

(WFCK PLL)

ALOCK = L ?

NO

YES

Fig. 3-2. CLV-W Mode Flow Chart

– 39 –

CXD2589Q

4. Description of Other Functions

4-1. Channel Clock Regeneration by the Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 4-1. The CXD2589Q has a built-in three-stage PLL.

• The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. The output of this first-stage PLL is used as a reference for all clocks within the LSI.

• The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.

• The third-stage PLL is a digital PLL that regenerates the actual channel clock.

• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition

to the conventional secondary loop.

– 40 –

Block Diagram 4-1

CXD2589Q

CLV-W CAV-W

Spindle rotation information

X'tal

XTSL

OSC

2/1 MUX

1/2 1/32

1/2

Microcomputer

control

VPON

1/n

n = 1 to 256

(VP7 to 0)

1/K

(KSL1, 0)

1/M

Phase comparator

VCOSEL2

VCO2

CLV-N

CLV-W CAV-W

Selector

/CLV-N

VPCO

LPF

VCTL

V16M

VCKI

Digital PLL

(KSL3, 2)

CXD2589Q

1/N

1/K

RFPLL

Phase comparator

VCO1

VCOSEL1

PCO

FILI

FILO

CLTV

– 41 –

CXD2589Q

4-2. Frame Sync Protection

• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.

• In the CXD2589Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately.

4-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the

code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.

• The CXD2589Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability.

• The correction status can be monitored externally. See Table 4-1.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data.

MNT3

0 0 0 1 1 1

MNT1

0 0 1 0 0 1

MNT0

0 1 1 0 1 1

Table 4-1.

Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible

– 42 –

Timing Chart 4-1

Normal-speed PB

MNT3

MNT1

MNT0

CXD2589Q

t = Dependent on error condition

C1 correction C2 correction

Strobe

4-4. DA Interface

• The CXD2589Q DA interface is as described below.

This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.

– 43 –

24

CXD2589Q

23456789101112

Rch MSB

24

L0

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB

Lch MSB (15)

Timing Chart 4-2

1

R0

LRCK

(44.1k)

BCK

(2.12M)

PCMD

48bit slot Normal-Speed Playback

12

48bit slot Double-Speed Playback

LRCK

(88.2k)

BCK

(4.23M)

– 44 –

R0

PCMD

CXD2589Q

4-5. Digital Out

There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2589Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3) of the channel status.

Digital Out C bit

0

12 3456 78 9101112131415

0

16

32

48

From sub Q

COPY

Emph

ID1

ID0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0

0 0 0 0 1 0 0 0 0 0 0 0

0

176

Bits 0 to 3...Sub Q control bits that matched twice with CRCOK

Bit 29..........1 when VPON is 1

Table 4-2.

4-6. Servo Auto Sequencer

This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jumps, and N-track move are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but can be sent to the CXD2589Q. Connect the CPU, RF and SSP as shown in Fig. 4-2. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).

– 45 –

CXD2589Q

(a) Auto Focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts with focus search-up, and the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E.

Connection diagram for using auto sequencer (example)

RF

SSP

FOK

C. out SENS DATA

CLK

XLT

FOK

CXD2589Q

CNIN SEIN

DATO CLKO XLTO

Fig. 4-2.

Auto focus

Focus search up

DATA CLOK

XLAT

SENS

Micro-computer

FOK = H

YES

FZC = H

YES

FZC = L

YES

Focus servo ON

END

NO

(Checks whether FZC is continuously high for the period of time E set with register 5)

NO

Fig. 4-3-(a). Auto Focus Flow Chart

– 46 –

XLT

FOK

SEIN (FZC)

BUSY

CXD2589Q

$47latch

Command for SSP

$03

Blind E

$08

Fig. 4-3-(b). Auto Focus Timing Chart

(b) Track Jump

1, 10, and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence.

• 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-4. Set blind A and brake B with register 5.

• 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-5. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through CNIN, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

• 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-6. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

• N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 4-7. N can be set to 216 tracks. CNIN is used for counting the number of jumps. This N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks.

– 47 –

Track

CXD2589Q

Track FWD kick

sled servo OFF

WAIT

(Blind A)

CNIN =

YES

Track REV

kick

WAIT

(Brake B)

Track, sled

servo ON

END

(REV kick for REV jump)

NO

(FWD kick for REV jump)

Fig. 4-4-(a). 1-Track Jump Flow Chart

XLT

CNIN

BUSY

Command for SSP

$48 (REV = $49) latch

Blind A

$28 ($2C)

Fig. 4-4-(b). 1-Track Jump Timing Chart

$2C ($28)

Brake B

$25

– 48 –

10 Track

Track, sled

FWD kick

CXD2589Q

WAIT

(Blind A)

CNIN = 5 ?

YES

Track, REV

kick

C = Overflow ?

YES

Track, sled

servo ON

END

(Counts CNIN × 5)

NO

(Checks whether the CNIN cycle

NO

is longer than overflow C)

Fig. 4-5-(a). 10-Track Jump Flow Chart

XLT

CNIN

BUSY

Command for SSP

$4A (REV = $4B) latch

Blind A

$2A ($2F)

Fig. 4-5-(b). 10-Track Jump Timing Chart

CNIN 5 count

$2E ($2B)

Overflow C

$25

– 49 –

2N Track

Track, sled

FWD kick

WAIT

(Blind A)

CXD2589Q

CNIN = N

Track REV

kick

C = Overflow

Track servo

ON

WAIT

(Kick D)

Sled servo

ON

END

NO

YES

NO

YES

Fig. 4-6-(a). 2N-Track Jump Flow Chart

XLT

CNIN

BUSY

Command for SSP

$4C (REV = $4D) latch

Blind A

$2A ($2F)

Fig. 4-6-(b). 2N-Track Jump Timing Chart

CNIN

N count

$2E ($2B)

– 50 –

Overflow

$26 ($27)

Kick D

$25

N Track move

Track servo OFF

Sled FWD kick

WAIT

(Blind A)

CXD2589Q

XLT

CNIN

Fig. 4-7-(a). N-Track Move Flow Chart

$4E (REV = $4F) latch

CNIN = N

YES

Track, sled

servo OFF

END

NO

BUSY

Command for SSP

$22 ($23)

Blind A

CNIN N count

Fig. 4-7-(b). N-Track Move Timing Chart

– 51 –

$20

CXD2589Q

4-7. Digital CLV

Fig. 4-8 shows the Block Diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the signal sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable.

Digital CLV

CLVS U/D

MDS Error

MDP Error

CLV P/S

Gain MDS

2/1 MUX

Measure

Over Sampling

Filter-2

Noise Shape

Measure

Over Sampling

Filter-1

Gain MDP

1/2

MUX

CLV P/S

KICK, BRAKE, STOP

LPWR

CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo PWMI: Spindle drive signal from the microcomputer for CAV servo

Modulation

PWMI

Mode Select

MDP

Fig. 4-8. Block Diagram

– 52 –

4-8. Asymmetry Compensation

R1

RF

35

R1

CXD2589Q

47

CXD2589Q

ASYO

R1

46

R1

BIAS

R2

36

Fig. 4-9. Example of Asymmetry Compensation Application Circuit

ASYI

R1 2

=

R2 5

– 53 –

CXD2589Q

5. 1bit DAC Block

5-1. DAC Block Input Timing

Timing Chart 5-1 shows the input timing for the DAC block. Audio data is not transferred from the CD signal processer block to the DAC block inside the CXD2589Q. This is to allow data to be sent to the DAC block via the audio DSP, etc. When data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI. In this case, EMPH, LRCK, BCK and PCMD can be connected directly with EMPHI, LRCKI, BCKI and PCMDI, respectively.

5-2. Description of DAC Block Functions

Zero data detection

When the condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued for approximately 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels.

Mute flag output

The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected by the ZDPL command of $9X.

• When zero data is detected

• When a high signal is input to the SYSM pin

• When the SMUT command of $AX is set

Attenuation operation

Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point.

0dB

7F (H)

A

Y1

B

Y3

C

Y2

– ∞

23.2 [ms]

00 (H)

– 54 –

DAC block mute operation

Soft mute

Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

• When attenuation data of "000" (high) is set

• When the SMUT command of $AX is set to 1

• When a high signal is input to the SYSM input pin

Soft mute on Soft mute offSoft mute off

0dB

– ∞dB

23.2 [ms] 23.2 [ms]

CXD2589Q

Forced mute

Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low.

∗

When setting FMUT, set OPSL2 to 1. (See the $AX commands.)

Zero detection mute

Forced mute is applied when the $9X command ZMUT is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".)

– 55 –

24

CXD2589Q

23456789101112

1

Rch MSB

24

L0

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB

Input Timing for DAC Block

Lch MSB (15)

2 1

Timing Chart 5-1

BCKI

LRCKI

(44.1k)

Normal-Speed Playback

(2.12M)

R0

PCMDI

LRCKI

Double-Speed Playback

(88.2k)

– 56 –

BCKI

(4.23M)

R0

PCMDI

CXD2589Q

LRCK Synchronization

Synchronization is performed at the first falling edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases.

• When the XTSL pin switches between high and low

• When the DSPB command of $9X setting changes

• When the MCSL command of $9X setting changes

LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in this case as well. For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set LRWO to 0.

∗

When setting LRWO, set OPSL2 to 1. (See the $AX commands.)

SYCOF

When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1. Normally, the memory proof, etc., is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting SYCOF of address 9 to 1 ignores that the LRCKI input synchronization is lost, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the LRCKI input.

∗

Set SYCOF to 0 except when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI, respectively, and performing playback in CAV-W mode.

∗

Set SYCOF to 0 in advance when LRCK resynchronization is applied with LRWO=1.

Digital Bass Boost

Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 5-2 for the digital bass boost frequency response.

[dB]

10.00

8.00

6.00

4.00

2.00

0.00 –2.00 –4.00 –6.00 –8.00

–10.00 –12.00 –14.00

10 30 100 300 1k 3k 10k 30k

Digital Bass Boost Frequency Response [Hz]

Normal DBB MID DBB MAX

Graph 5-2.

– 57 –

CXD2589Q

6. LPF Block

The CXD2589Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD – AVSS)/2.

The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc ≈ 40kHz.

The external capacitors' values when fc = 30kHz and 50 kHz are noted below as a reference. The resistors' values do not change at this time.

• When fc ≈ 30kHz: C1 = 200pF, C2 = 910pF

• When fc ≈ 50kHz: C1 = 120pF, C2 = 560pF

LPF Block Application Circuit

AOUT1 (2)

AIN1 (2)

Vc

LOUT1 (2)

12k

C1

150p

12k

Fig. 6-1. LPF External Circuit

C2

680p

Analog out

– 58 –

7. Setting Method of the CXD2589Q Playback Speed (in CLV-N mode)

(A) CD-DSP block

The playback modes shown below can be selected by the combination of the crystal, XTSL pin and DSPB command of $9X.

CD-DSP block playback speed

CXD2589Q

X'tal 768Fs 768Fs 384Fs 384Fs 384Fs

XTSL DSPB CD-DSP block playback speed

1×

1× 2× 1× 2×

∗1

1 1 0 0 1

0 1 0 1 1

Fs = 44.1kHz

∗1

Low power consumption mode. The CD-DSP processing speed is halved, allowing the power consumption to be decreased.

(B) 1-bit DAC block

The operating speed of the DAC block is determined by the crystal and the MCSL command of $9X regardless of the operating conditions of the CD-DSP block mentioned above. This allows the playback mode for the DAC block and CD-DSP block to be set independently.

1-bit DAC block playback speed

X'tal 768Fs

768Fs 384Fs

Fs = 44.1kHz

MCSL DAC block playback speed

1 0 0

1× 2× 1×

– 59 –

60

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

DD

BCK

Vss

V

GFS

C4M

Vss

40

PCMD

PCMDI

BCKI

XUGF

XPCK

C2PO

XTSL

DOUT EMPH

EMPHI WFCK SCOR SBSO

EXCK

DD

V 61

39

LRCK

LRCKI

SYSM 62

38

37

ASYI

ASYO

AVss

AVDDAOUT1

63

64

36

BIAS

65

RF

35 RF

AIN1 66

34

33

DD

AV

CLTV

LOUT1

AVss

67

68

32

AVss

DD

XV 69

31

FILI

XTAI 70

30

FILO

XTAO 71

29

PCO

XVss 72

28

VCTL

AVss 73

27

26

VCKI

V16M

LOUT2

AIN2

74

75

25

24

TES1

VPCO

DD

AOUT2

AV 77

76

23

TEST

AVss 78

22

PWMI

XRST 79

DRIVER

21

MDP

DD

XLON SPOB

DATO CNIN SEIN

SENS SQSO SQCK

DD

V 80

Vss

20

V

19

FOK

18 17 16

SPOA

15

CLKO

14

XLTO

13 12 11 10

CLOK

9

XLAT

8

DATA

7 6 5 4

RMUT

3

LMUT

2

Vss

1

LS

SSP

CXD2589Q

Application circuits shown are typical examples illustrating the operation of the

devices. Sony cannot assume responsibility for any problems arising out of the

use of these circuits or for any infringement of third party patent and other right

due to same.

Vss

V

DD

MUTE SCOR

SQCK SQSO GFS

CLK XLAT DATA

XRST SENS FOK

Application Circuit

– 60 –

Package Outline Unit: mm

60

16.0 ± 0.4 + 0.4

14.0 – 0.1

80PIN QFP (PLASTIC)

41

+ 0.35

1.5 – 0.15 + 0.1

0.127 – 0.05

CXD2589Q

0.1

61

80

1

0.65

SONY CODE EIAJ CODE JEDEC CODE

+ 0.15

0.3 – 0.1

QFP-80P-L03 LQFP080-P-1414

40

21

20 ± 0.12

M

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

+ 0.15

0.1 – 0.1

0° to 10°

EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY

0.6g

(15.0)

0.5 ± 0.2

– 61 –